August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 1
doc.: IEEE 802.11-04/0953r0
Submission
Flexible Coding for 802.11n MIMO Systems
Keith Chugg and Paul Gray
TrellisWare Technologies
Bob Ward
SciCom Inc.
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 2
doc.: IEEE 802.11-04/0953r0
Submission
Overview• FEC Requirements for IEEE 802.11n• Introduction to TrellisWare’s F-LDPC Codes• F-LDPC Turbo/LDPC dual interpretation• IEEE 802.11n PHY Layer FEC proposal
– Description
– Features
– Performance
– Complexity
• Conclusions
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 3
doc.: IEEE 802.11-04/0953r0
Submission
FEC Requirements for IEEE 802.11n• There are a number of essential features that an FEC solution must
possess to satisfy the requirements of IEEE 802.11n• Frame size flexibility
– Packets from MAC can be any number of bytes– Packets may be only a few bytes in length
• Code rate flexibility– Need fine rate control to make efficient use of the available capacity
• Good performance– Need codes that can operate as close as possible to theory
• High Speed– Need decoders that can operate at 300-500 Mbps
• Low Complexity– Need to do all this without being excessively complex
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 4
doc.: IEEE 802.11-04/0953r0
Submission
FEC Requirements for IEEE 802.11n (2)
• Benefits of flexibility in IEEE 802.11n:– Allows one to future-proof the design – i.e., don’t let the FEC
eliminate operational modes in the future
– Can hit best throughput that the channel allows• maximize spectral efficiency
• Support various multiple antenna Tx/Rx strategies equally well
• Eliminate the need for stuff/padding to accommodate inflexible FEC
– Flexibility comes nearly for free with TrellisWare’s F-LDPC
• Flexibility of the F-LDPC means that it can easily be configured to operate in 20 MHz or 40 MHz systems, or with any number of transmit and receive antennas
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 5
doc.: IEEE 802.11-04/0953r0
Submission
TrellisWare’s F-LDPC Codes• A Flexible-Low Density Parity Check Code (F-LDPC)• Serial concatenation of the following elements:
– Outer code: 2-state rate ½ non-recursive convolutional code– Flexible algorithmic interleaver– Single Parity Check (SPC) code– Inner Code: 2-state rate 1 recursive convolutional code– Systematic code overall
OuterCode I
SPC
InnerCode…
J bits wide
P/S (2:1) S/P (1:J)
F-LDPC Encoder
parity bits
systematic bits
input bits
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 6
doc.: IEEE 802.11-04/0953r0
Submission
TrellisWare’s F-LDPC Codes (2)• Use of 2-state constituent codes means very low decoder
complexity– Outer code polynomials: (1+D, 1+D)– Inner code polynomial: (1/(1+D))– Outer code uses tail-biting termination– Inner code is unterminated
• For K-bit frames the interleaver is fixed at 2K bits, regardless of rate.– Any good algorithmic interleaver will give frame size
programmability down to bit level
• SPC forms single-parity check of J bits. – Different code rates are achieved by only varying J– Code rate = J/(J+2)– Inner code runs at 1/J fraction of speed of outer code
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 7
doc.: IEEE 802.11-04/0953r0
Submission
TrellisWare’s F-LDPC Codes (3)• The F-LDPC offers outstanding flexibility and performance• Code rate flexibility is achieved by simply varying the SPC J parameter
– Many different code rates are supported– Good performance even for rates above 0.95
• Frame size flexibility is achieved independently by changing the interleaver size– Byte-level frame size programmability is simple– Good performance even for frames as small as a few bytes
• Performance is very close to finite block size performance bounds across a huge range of code rates and frame sizes
• Unique features of code make it well suited to low complexity, high speed decoder architectures
– Can be decoded by either LDPC or Turbo code decoder architectures– Similar logic complexity as typical LDPC decoders with less memory and faster convergence
(and more flexibility)• Proven technology
– A number of F-LDPC variants have been implemented in FPGA– A high speed ASIC is near completion that uses a 4-state variant of the F-LDPC called a
FlexiCode (with 4-state codes floors are below 10-10 BER)
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 8
doc.: IEEE 802.11-04/0953r0
Submission
F-LDPC Duality Interpretations
• Proposed code can be viewed as either– Concatenation of two-state convolutional codes with a
single-parity check (SPC) block code– Punctured irregular-LDPC (IR-LDPC)– IR-LDPC
• Proposed code can be decoded using– Forward-backward algorithm (BCJR) type SISO
decoders (typically associated with concatenated convolutional codes)
– Parallel “check node” and “variable node” processors (typically associated with LDPC codes)
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 9
doc.: IEEE 802.11-04/0953r0
Submission
F-LDPC Duality Interpretations (2)
• Performance is comparable to good IR-LDPC code– Near best performance of best known codes over wide range of
block sizes and code rates
• Decoding complexity (measured by operation counts) is very low– Similar to that of DVB-S2 IR-LDPC
– Significantly less that of an 8-state PCCC (e.g., 3GPPP)
• LDPC and “turbo” architectures apply– Third parties with good solutions for concatenated convolutional
codes and LDPC codes can apply their technology
– Yields high degree of freedom for trade-off between parallelism, memory architectures, etc.
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 10
doc.: IEEE 802.11-04/0953r0
Submission
F-LDPC as Concatenated CCs
1+D
1+DI
SPC
1/(1+D)…
J bits wide
P/S (2:1) S/P (1:J)
“zig-zag” code
OuterSISO
I-1 SPCSISO
InnerSISO…
J bits wide “zig-zag” SISO
IHard decisions
Channel Metrics (LLRs)for systematic bits
><
0
Encoder
Decoder (standard rules of iterative decoding)Channel Metrics (LLRs)for parity bits
V=(2K)/J parity bits
K systematic bits
K input bits
Rate=J/(J+2)
Note: activation begins with outer code
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 11
doc.: IEEE 802.11-04/0953r0
Submission
F-LDPC as Punctured IR-LDPC
c = Gb e + Sp = 0
G: generator of outer (1+D) code (K x K)S: “staircase” accumulator block (V x V)T: repeat outer code bit twice (2K x K)P: permutation of interleaver (2K x 2K)J: SPC mapping (V x 2K )
e = JPTc
1+D
1+DI
SPC
1/(1+D)…
J bits wide “zig-zag” code
Recall: Encoder
b
b
pc Tc e
(K x 1) (K x 1) (2K x 1)
G
0
I
JPT
0
Spcb
V
V
K
K K
= 0
Low Density Parity Check: Hc’ = 0
PTc
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 12
doc.: IEEE 802.11-04/0953r0
Submission
F-LDPC as Punctured IR-LDPC (2)
1 1 … 1
1 1 … 1
1 1 … 1
1 1 … 1 …
1 1 … 1
0
0
J
1 0 0 … 0 0 11 1 0 0 … 0 0 00 1 1 0 0 … 0 00 0 1 1 0 0 … 00 0 0 1 1 0 … 0
0 0 … 0 0 1 1 00 0 0 … 0 0 1 1
G =
1 0 0 … 0 0 01 1 0 0 … 0 0 00 1 1 0 0 … 0 00 0 1 1 0 0 … 00 0 0 1 1 0 … 0
0 0 … 0 0 1 1 00 0 0 … 0 0 1 1
S =
1 0 0 … 0 0 01 0 0 0 … 0 0 00 1 0 0 0 … 0 00 1 0 0 0 0 … 00 0 1 0 0 0 … 00 0 1 0 0 0 … 00 0 0 1 0 0 … 00 0 0 1 0 0 … 0
0 0 … 0 0 0 1 00 0 0 … 0 0 1 00 0 … 0 0 0 0 10 0 0 … 0 0 0 1
T =
(V x V)(K x K)
(V x 2K)
(2K x K)
J =
0 0 0 0 … 1 0 00 0 0 1 … 0 0 01 0 0 0 0 … 0 0
0 0 … 1 0 0 0 00 1 0 … 0 0 0 0
(2K x 2K)
P =
(pseudo-random permutation matrix)
G
0
I
JPT
0
SH =
This element is 1 if outer code is tail-bit; 0 if unterminated
This element is 1 if outer code is tail-bit; 0 if unterminated
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 13
doc.: IEEE 802.11-04/0953r0
Submission
F-LDPC as Punctured IR-LDPC (3)
I/I-1
J
2 2 2 2 2
J J J J
Present if inner code it tail-bit
Present if outer code it tail-bit
…
…
Inner (zig-zag) code
Outer code
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 14
doc.: IEEE 802.11-04/0953r0
Submission
F-LDPC as Punctured IR-LDPC (4)
Structured Permutation
J+2
…
J+2
…
J+2
3 3 3 3 3…2 2 2 2 2… 2 2 2 2 2…
J+2 J+233333
b: K Systematic Bits (dv=2) c: K (hidden) bits (dv=3) p: V=(2K/J) parity bits (dv=2)
K check nodes (from outer code); (dc=3) V=(2K/J) check nodes (from inner code); (dc=J+2)
dv Frac. of 2K(1+1/J) total
2 (J+2)/(2J+2)
3 J/[2(J+1)] (hidden)
dc Frac. of K(1+2/J) total
3 J/ (J+2)
J+2 2/(J+2)
Note: this assumes inner and outer codes are tail-bit. If not, there will be a small difference as implied in the previous slides
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 15
doc.: IEEE 802.11-04/0953r0
Submission
F-LDPC as Punctured IR-LDPC (5)
Code Numer of Edges/KRate TW's F-LDPC DVB-S20.50 7 70.67 6 6.875
Example of degree distribution for various code rates
• Complexity is roughly measured by number of edges in the parity check graph– TW’s F-LDPC has edge complexity
slightly less than the DVB-S2 IR-LDPC code
J Rate (after punct) Rate (before punc.) frac(dv=2) frac(dv=3) frac(dc=3) J+2 frac(dc=J+2)2 0.5 0.333333333 0.666666667 0.333333333 0.5 4 0.54 0.666666667 0.4 0.6 0.4 0.666666667 6 0.3333333338 0.8 0.444444444 0.555555556 0.444444444 0.8 10 0.2
16 0.888888889 0.470588235 0.529411765 0.470588235 0.888888889 18 0.111111111
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 16
doc.: IEEE 802.11-04/0953r0
Submission
F-LDPC as Punctured IR-LDPC (6)
• Decoder Activation schedules– “Standard LDPC”: parallel variable-node, parallel
check node• Number of internal messages stored = number of edges (~7K)
– “Piecewise Parallel (green-red-blue)” schedule • Number of internal messages stored (~2K)
– “Standard Concantenated Convolutional Code” schedule• Same as discussed when interpreting F-LDPC as CCC• Number of internal messages stored (~2K)
– Piecewise Parallel and Standard CCC exploit structure of the punctured IR-LDPC permutation
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 17
doc.: IEEE 802.11-04/0953r0
Submission
F-LDPC as Punctured IR-LDPC (7)
I/I-1
3 3 3 3 3…2 2 2 2 2… 2 2 2 2 2…
J+2
…
J+2
…
J+2 J+2 J+233333
Structure of permutation enables potential memory savings and different high-speed decoding architectures
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 18
doc.: IEEE 802.11-04/0953r0
Submission
1 2
Standard LDPC schedule
1 2 3 4 5678
Piecewise Parallel (green-red-blue) schedule
Standard CCC schedule (Outer SISO -> Inner SISO)
1 2 1 2 1 2 1 2 1 2
Outer SISO Inner SISO
F-LDPC as Punctured IR-LDPC (8)
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 19
doc.: IEEE 802.11-04/0953r0
Submission
F-LDPC as Punctured IR-LDPC (9)
• Schedule properties– All are examples of the same standard iterative
message-passing decoding rules with different activation schedules
– Each have the same computational complexity per iteration
– Iteration convergence, degree of parallelism,memory needs, etc. vary with schedule
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 20
doc.: IEEE 802.11-04/0953r0
Submission
F-LDPC as IR-LDPC
• Possible to eliminate hidden variables– Formulates the F-LDPC as in a standard IR-
LDPC format• i.e., N variable nodes, V=(N-K) check nodes
G
0
I
JPT
0
Spcb
V
V
K
K K
= 0 JPTGSp
b=
V
V
K
V
K
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 21
doc.: IEEE 802.11-04/0953r0
Submission
F-LDPC as IR-LDPC (2)
• Degree distribution– For high-spread interleaver and K>>J
• V variable nodes with dv=2
• K variable nodes with dv=4
• All checks have dc=2J+2– Example: r=1/2: 50% dv=2, 50% dv=4, dc=6
• This form has many four-cycles– Modified schedule or H-matrix transformations
likely required for good performance based on this graphical model
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 22
doc.: IEEE 802.11-04/0953r0
Submission
IEEE 802.11n PHY Layer FEC Proposal
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 23
doc.: IEEE 802.11-04/0953r0
Submission
Proposal Description• A single, flexible encoder that is suitable for use in a
variety of MIMO-OFDM systems• F-LDPC encoder is coupled with a simple puncture circuit
for fine rate control, a bit channel interleaver, and a flexible mapper
• Code rate and modulation profile can be tuned to maximize throughput
F-LDPCEncoder Puncture
BitInterleaver
I…
S/P (1:M)
11n Encoder
parity bits
systematic bitsinput bits
P/S (2:1)
FlexibleMapper
Q
outputsymbols
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 24
doc.: IEEE 802.11-04/0953r0
Submission
Proposal Description (2)• F-LDPC Encoder
– Code words of 3-1024 bytes– Larger packets transmitted by concatenating multiple code words of near equal
length (avoids small code words)– 5 Coarse rates of r = 1/2, 2/3, 4/5, 8/9, and 16/17
• Puncture for fine rate control– Needed for code rates between ½ and 2/3– 9 Fine rates of p = 16/16, 15/16,…., 8/16– Overall rate of r/(r+p(1-r))– 45 code rates from 1/2 to 32/33
• Interleaver– Bit interleaving of a single code word– A simple relative prime interleaver is used here (the size of this interleaver must be
very flexible)• Flexible Mapper
– 5 modulations of BPSK, QPSK, 16QAM, 64QAM, and 256QAM– Gray mapping– Bit-loading is easily supported
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 25
doc.: IEEE 802.11-04/0953r0
Submission
Rate Adaptation• A single encoder is recommended, regardless of the
number of sub-carriers and the number of spatial channels.• A simple rate adaptation algorithm is used to determine the
optimal code rate given the SNR profile of the channel, and to provide a modulation profile (bit loading)
• The modulation can be the same on all sub-carriers, but better performance is achieved if the modulation is varied across sub-carriers and spatial channels
• The fine code rate control can be used to eliminate or minimize pad bits. The code rate is decreased slightly to reduce the number of pad bits
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 26
doc.: IEEE 802.11-04/0953r0
Submission
Code Rate Flexibility• The following slides demonstrate the code rate flexibility
of the F-LDPC• Firstly PER vs. SNR curves are shown for a range of code
rates and modulation orders.– AWGN channel– 8000 information bit code word length– 32 iterations (with early stopping 32 iteration performance can be
achieved with considerably less iterations in practice)• 1% PER can be achieved from -2 dB to 27 dB SNR in
approximately 0.25 steps• Next the bandwidth efficiency is shown against SNR
required to achieve a PER of 1%, for the full range of code rate, modulation types, and frame sizes (from 128 to 8000 information bits)
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 27
doc.: IEEE 802.11-04/0953r0
Submission
0.001
0.01
0.1
1
0 5 10 15 20 25 30
PE
R
SNR (dB)
TrellisWare F-LDPC AWGN Performance - 8000 Information bits 32 Iterations
All Modulations
Rate 1/2 BPSK – 32/33 256QAM
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 28
doc.: IEEE 802.11-04/0953r0
Submission
0
1
2
3
4
5
6
7
8
-5 0 5 10 15 20 25 30
Ba
nd
wid
th E
ffici
en
cy (
info
bits
/sym
bo
l)
Required SNR for 1% PER (dB)
TrellisWare F-LDPC AWGN Performance - 32 Iterations
128 bits
256 bits
512 bits
1024 bits
2048 bits
8000 bits
Rate 1/2 - 32/33
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 29
doc.: IEEE 802.11-04/0953r0
Submission
Frame Size Flexibility• The following slides demonstrate the frame size flexibility • The coding and modulation is fixed at rate 4/5 16QAM• Firstly PER vs. SNR curves are shown for a range of frame sizes from
8 to 1000 bytes– AWGN channel– 8000 information bit code word length– 32 iterations (with early stopping 32 iteration performance can be
achieved with considerably less iterations in practice)• Next the SNR required to achieve a PER of 1% is shown against frame
size– Both automated search and hand tuned interleaver parameters are shown.
It is expected that performance matching that of the hand tuned parameters will be achieved everywhere eventually
– The finite block size performance bound is also plotted, showing that the automated search parameters are within 1 dB of this bound, and the hand tuned parameters are with 0.75 dB (see the performance section for a description of this bound)
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 30
doc.: IEEE 802.11-04/0953r0
Submission
0.001
0.01
0.1
1
10.5 11 11.5 12 12.5 13 13.5 14
PE
R
SNR (dB)
TrellisWare F-LDPC AWGN Performance - rate 4/5 16QAM 32 Iterations
8 bytes1000 bytesFrame Size
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 31
doc.: IEEE 802.11-04/0953r0
Submission
10
10.5
11
11.5
12
12.5
13
13.5
0 1000 2000 3000 4000 5000 6000 7000 8000
Re
qu
ired
SN
R fo
r 1
% P
ER
(d
B)
Frame Size (bits)
TrellisWare F-LDPC AWGN Performance - rate 4/5 16QAM 32 Iterations
Automated search parameters
Hand tuned parameters
Finite block bound
Modulation constrained capacity
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 32
doc.: IEEE 802.11-04/0953r0
Submission
Early Stopping• F-LDPC codes can use early-stopping to reduce the average number of
iterations and increase the data throughput– The hard decisions from the outer code are re-encoded and compared to hard
decisions of the extrinsic information from the outer code– If all bits in a codeword agree then no more iterations are performed– More iterations can be performed when needed– Requires a larger input buffer and flow-control algorithm to avoid buffer overflow
• The following plot shows that the performance with early stopping is almost as good as that with 32 iterations
– Flow control algorithm active with early stopping results– 50% larger input buffer is assumed
• The next plot shows the average throughput as a function of required SNR for a 1% PER, for a range of modulation schemes and code rates
– With early stopping the average number of iterations is less than 12– Note also that the average number of iterations reduces dramatically as the code rate
increases
• With early stopping we can achieve 32 iteration performance from a decoder capable of an average of less than 12 iterations
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 33
doc.: IEEE 802.11-04/0953r0
Submission
0
1
2
3
4
5
6
7
8
-5 0 5 10 15 20 25 30
Ba
nd
wid
th E
ffici
en
cy (
info
bits
/sym
bo
l)
Required SNR for 1% PER (dB)
TrellisWare F-LDPC Early Stopping - 8000 information bits
BPSK 32 its
QPSK 32 its
16QAM 32 its
64QAM 32 its
256QAM 32 its
BPSK Early Stopping
QPSK Early Stopping
16QAM Early Stopping
64QAM Early Stopping
256QAM Early Stopping
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 34
doc.: IEEE 802.11-04/0953r0
Submission
6.5
7
7.5
8
8.5
9
9.5
10
10.5
11
11.5
12
-5 0 5 10 15 20 25 30
Ave
rag
e It
era
tion
s
Required SNR for 1% PER (dB)
TrellisWare F-LDPC AWGN Average Iterations - 8000 information bits
BPSK Early Stopping
QPSK Early Stopping
16QAM Early Stopping
64QAM Early Stopping
256QAM Early Stopping
1/2
2/3
4/5
8/9
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 35
doc.: IEEE 802.11-04/0953r0
Submission
Finite Block Size Performance Bound• Useful to compare results to finite block size performance bound
• We use a symmetric information rate (SIR) and sphere packing bound approximation with a constellation constraint (equation (11) from [1])
• This gives an Eb/No penalty (in dB) for a finite input block size. This is a function of rate, target PER, and input block size.
• Dolinar, et. al. demonstrate that this penalty approximation is accurate for no modulation constraint for most cases of interest.
• We observed that this is true relative to constrained constellations as well. Specifically, adding this penalty to the min. Eb/No(dB) predicted by the SIR yields performance limits that are useful.
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 36
doc.: IEEE 802.11-04/0953r0
Submission
AWGN Performance• The following plot shows AWGN performance with an
8000 information bit code word for a range of code rates and modulation types.
• 32 iterations are shown, but with early stopping 32 iteration performance can be achieved with an average of less than 12 iterations
• All results are for max-log MAP decoding• Also shown are the finite block size bounds and capacity• Performance is very good compared to bound
– Except for low code rate, higher order modulation schemes– This could be improved by iterating the soft-demapper, but this
would increase the complexity significantly• This plot also demonstrated the fine code rate granularity
possible
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 37
doc.: IEEE 802.11-04/0953r0
Submission
0
1
2
3
4
5
6
7
8
9
-5 0 5 10 15 20 25 30
Ba
nd
wid
th E
ffici
en
cy (
info
bits
/sym
bo
l)
Required SNR for 1% PER (dB)
TrellisWare F-LDPC AWGN Performance - 8000 information bits 32 Iterations
BPSK
QPSK
16QAM
64QAM
256QAM
BPSK Bound
QPSK Bound
16QAM Bound
64QAM Bound
256QAM Bound
log2(1 + SNR)
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 38
doc.: IEEE 802.11-04/0953r0
Submission
Non-AWGN Performance• Non-AWGN results were generated using SVD with perfect channel
information
• Channel was the IST project IST-2000-30148 I-METRA Matlab model
• The following plots assume a 801.11a/g OFDM structure:– 64 sub-carriers/20 MHz sampling rate
– Same sub-carrier structure
– 48 sub-carriers for data, 4 sub-carriers for pilot
– “DC” sub-carrier empty, 11 sub-carriers for guard band
– 3.2 µs symbol, 800 ns cyclic prefix
• Bit-loading of each sub-carrier is performed, with the rate adaptation algorithm determining the code rate and modulation profile
• Tests run with nominal SNR into the rate adaptation algorithm of 0, 5, 10, 15, 20, and 25 dB
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 39
doc.: IEEE 802.11-04/0953r0
Submission
Well suited to MIMO Environment• FLDPC
– Facilitates variable length packet transmissions, with same byte level resolution as viterbi coded systems
– Consistent performance across wide variety of code rates
– Supports increased capacity operation with single encoder achitecture adapting across multiple MIMO channels
– Applied in 802.11n modelled environment as well UCLA testbed demonstrating these principles with excellent performance
PCWidebandTx DPU
2.4GHzRadio
2.4GHzRadio
2.4GHzRadio
2.4GHzRadio
2.4GHzRadio
WidebandRx DPU
PC
REFCLK
REFCLK
IF 70MHz IF 70MHz
UCLA
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 40
doc.: IEEE 802.11-04/0953r0
Submission
0.001
0.01
0.1
1
-5 0 5 10 15 20 25 30
PE
R
SNR (dB)
TrellisWare F-LDPC Fading Performance - 2x2 Channel E LOS - 8000 information bits 32 Iterations
Nominal 0 dB
Nominal 5 dB
Nominal 10 dB
Nominal 15 dB
Nominal 20 dB
Nominal 25 dB
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 41
doc.: IEEE 802.11-04/0953r0
Submission
0
2e+07
4e+07
6e+07
8e+07
1e+08
1.2e+08
1.4e+08
1.6e+08
-5 0 5 10 15 20 25 30
Ave
rag
e T
hro
ug
hp
ut (
bp
s)
SNR Required for 1% PER (dB)
TrellisWare F-LDPC Fading Performance - 2x2 Channel E LOS - 8000 information bits 32 Iterations
Nominal 0 dB
Nominal 5 dB
Nominal 10 dB
Nominal 15 dB
Nominal 20 dB
Nominal 25 dB
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 42
doc.: IEEE 802.11-04/0953r0
Submission
22 24 26 28 30 32 34 36 38 40 4210
-3
10-2
10-1
100
2x2, 1000 bytes, Flexi Code Len=2048, 64QAM, Rate=5/6, No Stopping, Channel Model: D, s2 threshold=90000
Preamble based PSAM (Length = 2) designed for channel model F
FE
R
SNR, dB
PCSI, 10 IterationsPCSI, 20 IterationsPCSI, 30 Iterations
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 43
doc.: IEEE 802.11-04/0953r0
Submission
22 24 26 28 30 32 34 36 38 40 4210
-4
10-3
10-2
10-1
100
2x2, 1000 bytes, Flexi Code Len=8000, 64QAM, Rate=5/6, No Stopping, Channel Model: D, s2 threshold=90000
Preamble based PSAM (Length = 2) designed for channel model F
FE
R
SNR, dB
PCSI, 10 IterationsPCSI, 20 IterationsPCSI, 30 Iterations
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 44
doc.: IEEE 802.11-04/0953r0
Submission
14 16 18 20 22 24 26 28 30 32 3410
-5
10-4
10-3
10-2
10-1
100
2x3, 1000 bytes, Flexi Code Len=512, 64QAM, Rate=5/6, No Stopping, Channel Model: D, s2 threshold=90000
Preamble based PSAM (Length = 2) designed for channel model F
FE
R
SNR, dB
PCSI, 10 IterationsPCSI, 20 IterationsPCSI, 30 Iterations
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 45
doc.: IEEE 802.11-04/0953r0
Submission
14 16 18 20 22 24 26 28 30 3210
-4
10-3
10-2
10-1
100
2x3, 1000 bytes, Flexi Code Len=2048, 64QAM, Rate=5/6, No Stopping, Channel Model: D, s2 threshold=90000
Preamble based PSAM (Length = 2) designed for channel model F
FE
R
SNR, dB
PCSI, 10 IterationsPCSI, 20 IterationsPCSI, 30 Iterations
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 46
doc.: IEEE 802.11-04/0953r0
Submission
15 20 25 3010
-4
10-3
10-2
10-1
100
2x3, 1000 bytes, Flexi Code Len=8000, 64QAM, Rate=5/6, No Stopping, Channel Model: D, s2 threshold=90000
Preamble based PSAM (Length = 2) designed for channel model F
FE
R
SNR, dB
PCSI, 10 IterationsPCSI, 20 IterationsPCSI, 30 Iterations
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 47
doc.: IEEE 802.11-04/0953r0
Submission
15 20 25 3010
-4
10-3
10-2
10-1
100
2x3, 1000 bytes, Flexi Code Len=2048, 64QAM, Rate=5/6, Genie Aided, Channel Model: D, s2 threshold=90000
Preamble based PSAM (Length = 2) designed for channel model F
FE
R
SNR, dB
PCSI, 10 IterationsPCSI, 20 IterationsPCSI, 30 Iterations
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 48
doc.: IEEE 802.11-04/0953r0
Submission
20 22 24 26 28 30 32 34 36 38 4010
-2
10-1
100
2x2, 1000 bytes, Flexi Code Len=8000, 64QAM, Rate=5/6, Genie Aided, Channel Model: B, s2 threshold=90000
Preamble based PSAM (Length = 2) designed for channel model F
FE
R
SNR, dB
PCSI, 20 Iterations
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 49
doc.: IEEE 802.11-04/0953r0
Submission
22 24 26 28 30 32 34 36 38 40 4210
-5
10-4
10-3
10-2
10-1
100
2x2, 1000 bytes, Flexi Code Len=8000, 64QAM, Rate=5/6, Genie Aided, Channel Model: E, s2 threshold=90000
Preamble based PSAM (Length = 2) designed for channel model F
FE
R
SNR, dB
PCSI, 20 Iterations
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 50
doc.: IEEE 802.11-04/0953r0
Submission
24 26 28 30 32 34 36 38 40 42
100
4x4, 1000 bytes, Flexi Code Len=8000, 64QAM, Rate=5/6, Genie Aided, Channel Model: B, s2 threshold=90000
Preamble based PSAM (Length = 2) designed for channel model F
FE
R
SNR, dB
PCSI, 20 Iterations
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 51
doc.: IEEE 802.11-04/0953r0
Submission
24 26 28 30 32 34 36 38 40 4210
-4
10-3
10-2
10-1
100
4x4, 1000 bytes, Flexi Code Len=8000, 64QAM, Rate=5/6, Genie Aided, Channel Model: E, s2 threshold=90000
Preamble based PSAM (Length = 2) designed for channel model F
FE
R
SNR, dB
PCSI, 20 Iterations
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 52
doc.: IEEE 802.11-04/0953r0
Submission
6 8 10 12 14 16 18 2010
-2
10-1
100
2x2, 1000 bytes, Flexi Code Len=8000, QPSK, Rate=5/6, Genie Aided, Channel Model: D, s2 threshold=90000
Preamble based PSAM (Length = 2) designed for channel model F
FE
R
SNR, dB
PCSI, 20 Iterations
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 53
doc.: IEEE 802.11-04/0953r0
Submission
6 8 10 12 14 16 18 2010
-4
10-3
10-2
10-1
100
2x2, 1000 bytes, Flexi Code Len=8000, QPSK, Rate=3/4, Genie Aided, Channel Model: D, s2 threshold=90000
Preamble based PSAM (Length = 2) designed for channel model F
FE
R
SNR, dB
PCSI, 20 Iterations
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 54
doc.: IEEE 802.11-04/0953r0
Submission
7 7.5 8 8.5 9 9.5 10 10.5 1110
-3
10-2
10-1
100
2x2, 1000 bytes, Flexi Code Len=8000, QPSK, Rate=1/2, Genie Aided, Channel Model: D, s2 threshold=90000
Preamble based PSAM (Length = 2) designed for channel model F
FE
R
SNR, dB
PCSI, 20 Iterations
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 55
doc.: IEEE 802.11-04/0953r0
Submission
26 27 28 29 30 31 32 33 34 35 3610
-4
10-3
10-2
10-1
100
4x4, 1000 bytes, Flexi Code Len=8000, 64QAM, Rate=3/4, No Stopping, Channel Model: D, s2 threshold=90000
Preamble based PSAM (Length = 2) designed for channel model F
FE
R
SNR, dB
PCSI, 10 IterationsPCSI, 20 IterationsPCSI, 30 Iterations
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 56
doc.: IEEE 802.11-04/0953r0
Submission
22 24 26 28 30 32 34 3610
-4
10-3
10-2
10-1
100
2x3, 1000 bytes, Flexi Code Len=8000, 256QAM, Rate=5/6, Genie Aided, Channel Model: D, s2 threshold=90000
Preamble based PSAM (Length = 2) designed for channel model F
FE
R
SNR, dB
PCSI, 10 IterationsPCSI, 20 IterationsPCSI, 30 Iterations
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 57
doc.: IEEE 802.11-04/0953r0
Submission
24 26 28 30 32 34 3610
-5
10-4
10-3
10-2
10-1
100
4x4, 1000 bytes, Flexi Code Len=8000, 64QAM, Rate=3/4, No Stopping, Channel Model: D, s2 threshold=90000
Preamble based PSAM (Length = 2) designed for channel model F
FE
R
SNR, dB
PCSI, 10 IterationsPCSI, 20 IterationsPCSI, 30 Iterations
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 58
doc.: IEEE 802.11-04/0953r0
Submission
10 12 14 16 18 20 22 2410
-4
10-3
10-2
10-1
100
2x2, 1000 bytes, Flexi Code Len=2048, QPSK, Rate=5/6, No Stopping, Channel Model: D, s2 threshold=90000
Preamble based PSAM (Length = 2) designed for channel model F
FE
R
SNR, dB
PCSI, 10 IterationsPCSI, 20 IterationsPCSI, 30 Iterations
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 59
doc.: IEEE 802.11-04/0953r0
Submission
17 18 19 20 21 22 23 24 25 26 2710
-4
10-3
10-2
10-1
100
2x2, 1000 bytes, Flexi Code Len=8000, 64QAM, Rate=1/2, Genie Aided, Channel Model: D, s2 threshold=90000
Preamble based PSAM (Length = 2) designed for channel model F
FE
R
SNR, dB
PCSI, 20 Iterations
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 60
doc.: IEEE 802.11-04/0953r0
Submission
14 16 18 20 22 24 26 2810
-3
10-2
10-1
100
2x2, 1000 bytes, Flexi Code Len=8000, 16QAM, Rate=3/4, Genie Aided, Channel Model: D, s2 threshold=90000
Preamble based PSAM (Length = 2) designed for channel model F
FE
R
SNR, dB
PCSI, 20 Iterations
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 61
doc.: IEEE 802.11-04/0953r0
Submission
16 18 20 22 24 26 28 3010
-3
10-2
10-1
100
2x2, 1000 bytes, Flexi Code Len=8000, QPSK, Rate=5/6, Genie Aided, Channel Model: D, s2 threshold=90000
Preamble based PSAM (Length = 2) designed for channel model F
FE
R
SNR, dB
PCSI, 20 Iterations
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 62
doc.: IEEE 802.11-04/0953r0
Submission
11 12 13 14 15 16 17 18 19 20 2110
-4
10-3
10-2
10-1
100
2x2, 1000 bytes, Flexi Code Len=8000, 16QAM, Rate=1/2, Genie Aided, Channel Model: D, s2 threshold=90000
Preamble based PSAM (Length = 2) designed for channel model F
FE
R
SNR, dB
PCSI, 20 Iterations
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 63
doc.: IEEE 802.11-04/0953r0
Submission
Decoder Throughput• Structure of the code lends it to low complexity, high speed decoding
– Similar complexity to DVB-S2 LDPC– Significantly lower complexity than 3GPP TC
• TrellisWare is near completion of a high speed ASIC implementation of a 4-state variant of this code
• Based upon this experience the following decoder throughputs have been calculated
• We have used a baseline high speed architecture with a nominal degree of parallelism of P=1. An architecture with a degree of parallelism of P=n is n approximately n times as complex as the baseline, with approximately n times the throughput
• Plots are given for both throughput normalized to the system clock (bps per clk) and actual throughput with a number of system clock assumptions
• We are currently developing an P=8 FPGA prototype which can operate with a system clock of 100 MHz and is expected to achieve a throughput of at least 300 MHz.
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 64
doc.: IEEE 802.11-04/0953r0
Submission
0
2
4
6
8
10
5 10 15 20 25 30
De
cod
er
Th
rou
gh
pu
t (b
ps
pe
r cl
ock
)
Iterations
TrellisWare F-LDPC Throughput - 8000 information bits
P = 1
P = 2
P = 4
P = 8
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 65
doc.: IEEE 802.11-04/0953r0
Submission
0
100
200
300
400
500
600
5 10 15 20 25 30
De
cod
er
Th
rou
gh
pu
t (M
bp
s)
Iterations
TrellisWare F-LDPC Throughput - 8000 information bits
P=4 f=100 MHz
P=8 f=100 MHz
P=4 f=150 MHz
P=8 f=150 MHz
P=4 f=200 MHz
P=8 f=200 MHz
P=4 f=250 MHz
P=8 f=250 MHz
P=4 f=300 MHz
P=8 f=300 MHz
<0.2 dB from 32 iterations
FPGA Prototype:
300 Mbps
August 2004
Keith Chugg, et al, TrellisWare Technologies
Slide 66
doc.: IEEE 802.11-04/0953r0
Submission
Comparion Criteria/11n Requirements are supported well
• As a partial proposal– Supports overall phy layer demanding requirements– High Through-put operation – 300 500 Mbps– Increased capacity – higher spectral efficiences– Reliable performance PERs below 1%– Non Awgn environment– Applies equally well to larger bandwidth operation
20/40 Mhz– Supports backwards compatibility with variable length
PDU performance
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