Digital Integrated Digital Integrated Digital Integrated Digital Integrated CircuitsCircuits
IntroductionIntroductionIntroductionIntroduction
EE141© Digital Integrated Circuits2nd Introduction1
Wh t i thi l tWh t i thi l t b t?b t?What is this lectureWhat is this lecture about?about?Introduction to digital integrated circuits + low power circuits
Issues in digital designThe CMOS inverterC bi ti l l i t tCombinational logic structuresSequential logic gatesDesign methodologiesInterconnect: R, L and CInterconnect: R, L and CTimingArithmetic building blocksMemories and array structuresL i itLow power circuits
What will you learn?Understanding designing and optimizing digital circuitsUnderstanding, designing, and optimizing digital circuits cost, speed, power dissipation, and reliability
EE141© Digital Integrated Circuits2nd Introduction2
M ’ LM ’ LMoore’s LawMoore’s LawIn 1965, Gordon Moore noted that the number of transistors on a ,chip doubled every 18 to 24 months. He made a prediction that semiconductor technology will double its effectiveness every 18 months
1 61 51 41 31 2O
F FUN
CTI
ON
its effectiveness every 18 months
1 21 11 0
987THE
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ER O
R IN
TEG
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TED
765432
LOG
2 OF
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NEN
TS P
ER
10
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
CO
M
EE141© Digital Integrated Circuits2nd Introduction3
Electronics, April 19, 1965.
Evolution in ComplexityEvolution in ComplexityEvolution in ComplexityEvolution in Complexity
EE141© Digital Integrated Circuits2nd Introduction4
Transistor CountsTransistor CountsTransistor CountsTransistor Counts1 Billion1 Billion
1,000,000K
1 Billion 1 Billion TransistorsTransistors
100,000
10,000 Pentium® IIPentium® III1 Million 1 Million
TransistorsTransistors1,000
100 i386i486
Pentium®Pentium® Pro
10
100
808680286
i386
Source: IntelSource: Intel11975 1980 1985 1990 1995 2000 2005 2010
Source: IntelSource: Intel
P j t dP j t d
EE141© Digital Integrated Circuits2nd Introduction5
ProjectedProjected
Courtesy, Intel
Moore’s law in MicroprocessorsMoore’s law in MicroprocessorsMoore s law in MicroprocessorsMoore s law in Microprocessors1000
10
100M
T)2X growth in 1.96 years!
386486 Pentium® proc
P61
10
sist
ors
(M
80808085 8086
286386
0.01
0.1
Tran
s
400480088080
0.001
0.01
1970 1980 1990 2000 20101970 1980 1990 2000 2010Year
Transistors on Lead Microprocessors double every 2 years
EE141© Digital Integrated Circuits2nd Introduction6
Courtesy, Intel
Die Size GrowthDie Size GrowthDie Size GrowthDie Size Growth100
mm
)
8080 8086286
386486 Pentium ® procP6
10
e si
ze (m
40048008
80808085
8086
Die ~7% growth per year
~2X growth in 10 years
11970 1980 1990 2000 2010
Year
Die size grows by 14% to satisfy Moore’s Law
EE141© Digital Integrated Circuits2nd Introduction7
Courtesy, Intel
FrequencyFrequencyFrequencyFrequency10000
D bl
P6
1000M
hz)
Doubles every2 years
P6Pentium ® proc
4863862868086808510
100
quen
cy (
28680868085
80808008
1Freq
800840040.1
1970 1980 1990 2000 2010YYear
Lead Microprocessors frequency doubles every 2 years
EE141© Digital Integrated Circuits2nd Introduction8
Courtesy, Intel
Power DissipationPower DissipationPower DissipationPower Dissipation100
P6Pentium ® proc
48610at
ts)
486386
2868086
808580801ower
(Wa
808080084004
1Po
0.11971 1974 1978 1985 1992 2000
YearYear
Lead Microprocessors power continues to increase
EE141© Digital Integrated Circuits2nd Introduction9
Courtesy, Intel
Power will be a major problemPower will be a major problemPower will be a major problemPower will be a major problem5KW
18KW 100000
5KW 1.5KW
500W 1000
10000W
atts
)
80858086
286386
486
Pentium® proc
10
100
ower
(W
4004800880808085 386
1
10P
0.11971 1974 1978 1985 1992 2000 2004 2008
YearYear
Power delivery and dissipation will be prohibitive
EE141© Digital Integrated Circuits2nd Introduction10
Courtesy, Intel
Power densityPower densityPower densityPower density10000
) Rocket
1000
(W/c
m2
Nuclear
RocketNozzle
100
Den
sity
Reactor
400480088080
8085
8086
286 386486
Pentium® procP610
Pow
er
Hot Plate
8080 286 48611970 1980 1990 2000 2010
YearYear
Power density too high to keep junctions at low temp
EE141© Digital Integrated Circuits2nd Introduction11
Courtesy, Intel
Not Only MicroprocessorsNot Only MicroprocessorsNot Only MicroprocessorsNot Only Microprocessors
C llCellPhone
Small Signal RF
PowerRF
Digital Cellular Market(Phones Shipped)
1996 1997 1998 1999 2000Power
Management
1996 1997 1998 1999 2000
Units 48M 86M 162M 260M 435M Analog Baseband
Digital Baseband
(DSP + MCU)
(data from Texas Instruments)(data from Texas Instruments)
EE141© Digital Integrated Circuits2nd Introduction12
Challenges in Digital DesignChallenges in Digital DesignChallenges in Digital DesignChallenges in Digital Design
“Microscopic Problems”Ult hi h d d i
“Macroscopic Issues”• Time to Market• Ultra-high speed design
• Interconnect• Noise, Crosstalk• Reliability Manufacturability
• Time-to-Market• Millions of Gates• High-Level Abstractions• Reuse & IP: Portability• Reliability, Manufacturability
• Power Dissipation• Clock distribution.
Reuse & IP: Portability• Predictability• etc.
Everything Looks a Little Different…and There’s a Lot of Them!??
EE141© Digital Integrated Circuits2nd Introduction13
Productivity TrendsProductivity TrendsProductivity TrendsProductivity Trends10,000,000 100,000,00010,000(M
)100,000
100,000
1,000,000
1,000,000
10,000,000Logic Tr./ChipTr./Staff Month.
1,000
100
r per
Chi
p
1,000
10,000
ty f -M
o.
xity
1,000
10,000
10,000
100,00058%/Yr. compoundedComplexity growth rate10
1
Tra
nsis
tor
10
100
Prod
uctiv
itTr
ans.
/Sta
ff
Com
plex
10
100
100
1,000xxx
xxx
x21%/Yr. compound
Productivity growth rate
x0.1
0.01
0 001
Logi
c
0 01
0.1
1
P(K
) T
1
2003
1981
1983
1985
1987
1989
1991
1993
1995
1997
1999
2001
2005
2007
2009
100.001 0.01
S S t hSource: Sematech
Complexity outpaces design productivity
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Courtesy, ITRS Roadmap
Why Scaling?Why Scaling?Why Scaling?Why Scaling?Technology shrinks by 0.7/generationTechnology shrinks by 0.7/generationWith every generation can integrate 2x more functions per chip; chip cost does not increasefunctions per chip; chip cost does not increase significantlyCost of a function decreases by 2xCos o a u c o dec eases byBut …
How to design chips with more and more functions?How to design chips with more and more functions?Design engineering population does not double every two years…
Hence, a need for more efficient design methodsExploit different levels of abstraction
EE141© Digital Integrated Circuits2nd Introduction15
Design Abstraction LevelsDesign Abstraction LevelsggSYSTEM
MODULE
+
GATE
MODULE
CIRCUIT
GATE
GDEVICE
n+n+S
GD
EE141© Digital Integrated Circuits2nd Introduction16
Design MetricsDesign MetricsDesign MetricsDesign Metrics
H t l t f fHow to evaluate performance of a digital circuit (gate, block, …)?
CostReliabilityyScalabilitySpeed (delay, operating frequency)Speed (delay, operating frequency) Power dissipationEnergy to perform a functionEnergy to perform a function
EE141© Digital Integrated Circuits2nd Introduction17
C t f I t t d Ci itC t f I t t d Ci itCost of Integrated CircuitsCost of Integrated Circuits
NRE (non-recurrent engineering) costsdesign time and effort mask generationdesign time and effort, mask generationone-time cost factor
Recurrent costssilicon processing packaging testsilicon processing, packaging, testproportional to volume
ti l t hiproportional to chip area
EE141© Digital Integrated Circuits2nd Introduction18
NRE Cost is IncreasingNRE Cost is IncreasingNRE Cost is IncreasingNRE Cost is Increasing
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Di C tDi C tDie CostDie Cost
Single dieg
WaferWafer
Going up to 12” (30cm)
EE141© Digital Integrated Circuits2nd Introduction20From http://www.amd.com
C t T i tC t T i tCost per TransistorCost per Transistor
cost: cost: ¢¢--perper--transistortransistor
0.010.01
0.10.111
¢¢ perper transistortransistor
Fabrication capital cost per transistor (Moore’s law)
0.00010.0001
0.0010.001
0.010.01
0.0000010.000001
0.000010.00001
0.00000010.000000119821982 19851985 19881988 19911991 19941994 19971997 20002000 20032003 20062006 20092009 20122012
EE141© Digital Integrated Circuits2nd Introduction21
YieldYield%100
per waferchipsofnumber Totalper wafer chips good of No.
×=Ypp
yieldDieper waferDiescostWafer cost Die×
=yieldDieper waferDies ×
( )areadie2
diameterwafer areadie
diameter/2wafer per wafer Dies2
××π
−×π
=areadie2areadie ×
EE141© Digital Integrated Circuits2nd Introduction22
DefectsDefectsDefectsDefects
α−⎞⎛ diitd f t⎟⎠⎞
⎜⎝⎛
α×
+=areadieareaunit per defects1yield die
is approximatel 3 α is approximately 3
4area)(diecostdie f=
EE141© Digital Integrated Circuits2nd Introduction23
area)(diecost die f=
Some Examples (1994)Some Examples (1994)Some Examples (1994)Some Examples (1994)Chip Metal
lLine id h
Wafer Def./ 2
Area 2
Dies/f
Yield Die layers width cost cm2 mm2 wafer cost
386DX 2 0.90 $900 1.0 43 360 71% $4
486 DX2 3 0.80 $1200 1.0 81 181 54% $12
Power PC 4 0.80 $1700 1.3 121 115 28% $53601
$ $
HP PA 7100 3 0.80 $1300 1.0 196 66 27% $73
DEC Alpha 3 0.70 $1500 1.2 234 53 19% $149
Super Sparc 3 0 70 $1700 1 6 256 48 13% $272Super Sparc 3 0.70 $1700 1.6 256 48 13% $272
Pentium 3 0.80 $1500 1.5 296 40 9% $417
EE141© Digital Integrated Circuits2nd Introduction24
Reliability―Reliability―Noise in Digital Integrated CircuitsNoise in Digital Integrated Circuits
v(t) VDDi(t)
( ) DD
Inductive coupling Capacitive coupling Power and groundnoise
EE141© Digital Integrated Circuits2nd Introduction25
DC OperationDC OperationVoltage Transfer CharacteristicVoltage Transfer CharacteristicVoltage Transfer CharacteristicVoltage Transfer Characteristic
V(y)V(y)
VOH fVOH = f(VOL)VOL f(VOH)VOH f
V(y)=V(x) VOL = f(VOH)VM = f(VM)
VMSwitching Threshold
V(x)
VOL
VV V(x)VOHVOL
Nominal Voltage Levels
EE141© Digital Integrated Circuits2nd Introduction26
Nominal Voltage Levels
Mapping between analog and digital signalsMapping between analog and digital signalspp g g g gpp g g g g
V
Slope = -1V OH
Vout
V
VOH“1”
OHVIH
UndefinedUndefinedRegion
Slope = -1
V OL“0” V
VIL
V IL V IH V in
OL0 VOL
EE141© Digital Integrated Circuits2nd Introduction27
Definition of Noise MarginsDefinition of Noise MarginsDefinition of Noise MarginsDefinition of Noise Margins
"1"
VNoise margin high
VIH
VOH NMH
Noise margin lowVIL
UndefinedRegion
VNML Noise margin lowIL
"0"
VOL
Gate Output Gate Input
EE141© Digital Integrated Circuits2nd Introduction28
N i B d tN i B d tNoise BudgetNoise Budget
Allocates gross noise margin to expected sources of noiseexpected sources of noiseSources: supply noise, cross talk, interference, offsetDifferentiate between fixed andDifferentiate between fixed and proportional noise sources
EE141© Digital Integrated Circuits2nd Introduction29
K R li bilit P tiK R li bilit P tiKey Reliability PropertiesKey Reliability PropertiesAbsolute noise margin values are deceptive
a floating node is more easily disturbed than a g ynode driven by a low impedance (in terms of voltage)
Noise immunity is the more important metric –the capability to suppress noise sourcesKey metrics: Noise transfer functions, Output impedance of the driver and input impedance of the receiver;
EE141© Digital Integrated Circuits2nd Introduction30
Regenerative PropertyRegenerative PropertyRegenerative PropertyRegenerative Property
Regenerative Non-Regenerative
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Regenerative PropertyRegenerative PropertyRegenerative PropertyRegenerative Property
v0 v1 v2 v3 v4 v5 v6
A chain of inverters
Simulated response
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FanFan--in and Fanin and Fan--outoutFanFan in and Fanin and Fan outout
MN
M
Fan-out N Fan-in M
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The Ideal GateThe Ideal Gate
V out
Ri = ∞Ro = 0o Fanout = ∞NMH = NML = VDD/2g = ∞ NMH NML VDD/2
V in
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Delay DefinitionsDelay Definitionsyy
EE141© Digital Integrated Circuits2nd Introduction35
Ring OscillatorRing OscillatorRing OscillatorRing Oscillator
T = 2 ´ tp ´ N
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p
A Fi tA Fi t O d RC N t kO d RC N t kA FirstA First--Order RC NetworkOrder RC Network
voutR
vout
vin C
tp = ln (2) τ = 0.69 RCtp ln (2) τ 0.69 RC
Important model – matches delay of inverter
EE141© Digital Integrated Circuits2nd Introduction37
Important model matches delay of inverter
P Di i tiP Di i tiPower DissipationPower Dissipation
Instantaneous power: p(t) = v(t)i(t) = V i(t)p(t) = v(t)i(t) = Vsupplyi(t)
Peak power:Peak power: Ppeak = Vsupplyipeak
Average power: V ( )∫ ∫
+ +==
Ttt
Ttt supply
supplyave dtti
TV
dttpT
P )(1
EE141© Digital Integrated Circuits2nd Introduction38
E d EE d E D lD lEnergy and EnergyEnergy and Energy--DelayDelay
Power-Delay Product (PDP) =
E = Energy per operation = Pav × tp
Energy-Delay Product (EDP) =
quality metric of gate = E × tp
EE141© Digital Integrated Circuits2nd Introduction39
A Fi tA Fi t O d RC N t kO d RC N t kA FirstA First--Order RC NetworkOrder RC Network
voutR
vin CL
T T Vdd
E0 1→ P t( )dt0
T∫ Vdd isupply t( )dt
0
T∫ Vdd CLdVout
0∫ CL Vdd• 2= = = =
Ecap Pcap t( )dt0
T∫ Vouticap t( )dt
0
T∫ CLVoutdVout
0
Vdd∫
12---C
LVdd•
2= = = =
EE141© Digital Integrated Circuits2nd Introduction40
SummarySummarySummarySummaryDigital integrated circuits have come a longDigital integrated circuits have come a long way and still have quite some potential left for the coming decadesgSome interesting challenges ahead
Getting a clear perspective on the challenges and g p p gpotential solutions is the purpose of this book
Understanding the design metrics that govern digital design is crucial
Cost, reliability, speed, power and energy di i tidissipation
EE141© Digital Integrated Circuits2nd Introduction41