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CS504 : Digital Design
Lecture Three
Gate-Level Minimization
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Circuit Optimization 2
Circuit Optimization
Goal: To otain the simplestimplementation !or a given !unction
Optimization is a more !ormal approach tosimpli!ication that is per!orme" using aspeci!ic proce"ure or algorithm
Optimization re#uires a cost criterion tomeasure the simplicit$ o! a circuit
Distinct cost criteria %e %ill use:• Literal cost &L'
• Gate input cost &G'
• Gate input cost inclu"ing inverters &G('
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Circuit Optimization 3
Literal ) a variale or it complement Literal cost ) the numer o! literal
appearances in a *oolean e+pression
correspon"ing to the logic circuit "iagram ,+ample: *oolean e+pressions !or
• . * D / * C / C D
• . * D / * C / * D / * C
• . &/*'&/D'&*/C/D'&*/C/D'
• 1hich solution is est2
Literal Cost
L . 3
L .
L . 0
irst solution is est
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Circuit Optimization 4
Gate nput Cost
Gate nput Cost: Count o! total numer o! inputs to the
gates in the logic circuit implementation
T%o gate input costs are "e!ine":
G . Count o! gate inputs %ithout counting nverters
G( . Count o! gate inputs / count o! nverters
or SO6 an" 6OS e#uations7 the gate input cost can e
!oun" !rom the *oolean e+pression $ !in"ing the sum o!:
• ll literal appearances
• (umer o! terms e+clu"ing single literal terms &a""e" to G'
• (umer o! "istinct complemente" single literals &a""e" to G('
,+ample:
• . * D / * C / C D
L . 3 G . L/8 .
G( . G/8 . 4
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Circuit Optimization 5
,+ample : . / * C /
Cost Criteria &continue"'
A
BC
F
* CL . 5
L &literal count' counts the (D inputs an" the single literal O9 input
G . L / ; . <
G &gate input count' a""s the remaining O9 gate inputs
G( . G / ; . =
G(&gate input count %ith (OTs' a""s the inverter inputs
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Circuit Optimization 6
,+ample ;: . * C /
L . > G . 3 G( .
. & / '& / C'& / *'
L . > G . = G( . ;
Same !unction an" same
literal cost
*ut !irst circuit has ettergate input count an" etter
gate input count %ith (OTs
Select !irst circuit?
Cost Criteria &continue"'
*C
ABC
F
C *
F
AB
C
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8/15/2019 digital design ch3
8/63Circuit Optimization -
*oolean unction Optimization
Minimizing the gate input &or literal' cost o! a*oolean e#uation re"uces the circuit cost
1e choose gate input cost
*oolean lgera an" graphical techni#ues are tools
to minimize cost criteria values Some important #uestions:
• 1hen "o %e stop tr$ing to re"uce the cost2
• Do %e @no% %hen %e have a minimum cost2
Treat optimum or near-optimum cost !unctions
!or t%o-level &SO6 an" 6OS' circuits !irst
ntro"uce a graphical techni#ue using Aarnaugh
maps &A-maps !or short'
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Aarnaugh Map &A-map'
A-map is a collection o! s#uares
• ,ach s#uare represents a minterm
• The collection o! s#uares is a graphical representation
o! a *oolean !unction
• "Bacent s#uares "i!!er in the value o! one variale
• lternative algeraic e+pressions !or the same !unctionare "erive" $ recognizing patterns o! s#uares
The A-map can e vie%e" as
• reorganize" version o! the truth tale
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Some ses o! A-Maps
6rovi"e a means !or:• in"ing optimum or near optimum
SO6 an" 6OS stan"ar" !orms
T%o-level (DO9 an" O9(D circuits
!or !unctions %ith small numers o! variales
• Eisualizing concepts relate" to manipulating
*oolean e+pressions7 an"• Demonstrating concepts use" $ computer-
ai"e" "esign programs to simpli!$ large circuits
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T%o-Eariale A-Map
;-variale Aarnaugh Map:• Minterm m0 an" minterm m4 are Fa"Bacent
the$ "i!!er in the value o! variale $
• Similarl$7 minterm m0 an" minterm m; area"Bacent an" "i!!er in +
• lso7 m4 an" m8 "i!!er in the + variale
•inall$7 m; an" m8 "i!!er in the $ variale
m8 . + $m; . + $+ .
m . + $m0 . + $+ . 0
$ . $ . 0+$
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Circuit Optimization /2
A-Map an" Truth Tales
The A-Map is a "i!!erent !orm o! the truth tale
Truth Tale
nputEalues
&+7$'
unctionEalue
&+7$'
0 0
0 0 0
A-Map
+ .
0+ . 0
$ . $ . 0+$
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Circuit Optimization /4
Three Eariale A-Map
1here each minterm correspon"s to the pro"uct terms:
(ote that i! the inar$ value !or an in"e+ "i!!ers in one it
position7 the minterms are a"Bacent on the A-Map
$z.00 $z.0 $z. $z.0
+.0 m0 m m8 m;
+. m4 m5 m< m>
$z.00 $z.0 $z. $z.0
+.0
+.
z$+ z$+ z$+ z$+
z$+ z$+ z$+ z$+
+$z
+$z
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Circuit Optimization /5
lternative A-Map Laeling
A-Map largel$ involves:• ,ntering values into the map7 an"
• 9ea"ing o!! pro"uct terms !rom the map
lternate laelings are use!ul:
$
z
+
0 ;
4
8
5 ><
+
$
zz
yy z
z
0 ;
4
8
5 ><
x
0
1
00 01 11 10
x
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Circuit Optimization /6
,+ample unctions
*$ convention7 %e represent the minterms o! $ a IHin the map an" leave the entries that contain I0H lan@
,+ample :
,+ample ;:
Learn the locations o! the 3
in"ices ase" on the variale
or"er sho%n
$
+
0 ;
4
8
5 ><
z
+
$0 ;
4
8
5 >
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Circuit Optimization /7
Comining S#uares
*$ comining s#uares7 %e re"uce numer o! literals ina pro"uct term7 there$ re"ucing the gate input cost
On a 8-variale A-Map:
• One s#uare represents a minterm %ith 8 variales
• T%o a"Bacent s#uares represent a term %ith ; variales
• our a"Bacent s#uares represent a term %ith variale
• ,ight a"Bacent s#uare is the !unction &no variales'
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Circuit Optimization /-
,+ample: Comining S#uares
,+ample:
ppl$ing the Minimization Theorem 8 times:
Thus the !our terms that !orm a ; K ; s#uarecorrespon" to the term I$H
$ z$$z
z$+z$+z$+z$+'z7$7+&
+
$/0 2
4
3
5 67
z
. J&;7 87 >7
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Circuit Optimization /.
Comining our S#uares
,+ample Shapes o! 4-s#uare 9ectangles:
$
0 8 ;
5 >4 <
z+
+ $ z
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Circuit Optimization 20
Comining T%o S#uares
,+ample Shapes o! ;-s#uare 9ectangles:
$
0 8 ;
5 >4 <+
z
+ $ + z
$ z
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Circuit Optimization 2/
Simpli!$ing 8-Eariale unctions
A-Maps can e use" to simpli!$ *oolean !unctions
,+ample: !in" an optimum SO6 e#uation !or
&+7 $7 z' . J &07 7 ;7 47 >7
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Circuit Optimization 22
our-Eariale A-Map
00 0 0
00 m0 . % + $ z m . % + $ z m8 . % + $ z m; . % + $ z
0 m4 . % + $ z m5 . % + $ z m . % + $ z
m; . % + $ z m8 . % + $ z m5 . % + $ z m4 . % + $ z
0 m3 . % + $ z m= . % + $ z m . % + $ z m0 . % + $ z
$z%+
1
N
1
N
N
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Circuit Optimization 23
4-Eariale A-map Terms
4-variale A-maps can have rectanglescorrespon"ing to:
• Single s#uare . 4-variale minterm
• ; comine" s#uares . 8-variale term
• 4 comine" s#uares . ;-variale term
• 3 comine" s#uares . variale term
• > &all' comine" s#uares . constant IH
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Circuit Optimization 24
Comining ,ight S#uares
,+amples o! 3-s#uare 9ectangles:
N
3 = 0
; 8 45
0 8 ;
5 >4 <
1
1
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Circuit Optimization 25
Comining our S#uares
,+amples o! 4-s#uare 9ectangles:
3 = 0
; 8 45
0 8 ;
5 >4 <
N
1
1 N N
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Circuit Optimization 26
Comining T%o S#uares
,+amples o! ;-s#uare 9ectangles:
3 = 0
; 8 45
0 8 ;
5 >4 <
N
1
1 1 N
N
1 N
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Circuit Optimization 27
Simpli!$ing 4-Eariale unctions
&17 N7 7 ' . J &07 ;7 47 57 >7
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Circuit Optimization 2-
6ro"uct-o!-Sum &6OS' Simpli!ication
&17 N7 7 ' . J &7 ;7 87 =7 07 7 87 47 5' .
&17 N7 7 ' . J &07 47 57 >7 '
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Circuit Optimization 2.
6ro"uct-o!-Sum Simpli!ication
Step /: 1ra" t,e map *or F# replacing t,e 0 o*F "it, / in F an$ vice vera
Step 2: btain a minimal Sumo*+ro$uct (S+)
e%preion *or F Step 3: e 1eorgan 8,eorem to obtain F 9 F
8,e reult i a minimal +ro$ucto*Sum (+S)
e%preion *or F
Step 4: Compare t,e cot o* t,e minimal S+ an$
+S e%preion to *in$ ",ic, one i better
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Circuit Optimization 30
ive-Eariale A-Maps or !ive variale prolems7 %e use t%o a"Bacent 4-variale
A-maps that can e visualize" to e on top o! each other
,ach s#uare in the .0 map is a"Bacent to the
correspon"ing s#uare in the . map &eg m4 an" m;0'
C
D
E
B
A = 0
0 / 3 2
4 5 7 6
/2 /3 /5 /4
- . // /0
C
E
B
A = 1D
/6 /7 /. /-
20 2/ 23 22
2- 2. 3/ 30
24 25 27 26
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Circuit Optimization 3/
,+ample o! a ive-Eariale A-map
&7 *7 C7 D7 ,' . J&07 7 37 =7 >7
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Circuit Optimization 32
Sometimes a !unction tale or A-map contains entries !or%hich it is @no%n:
• The input values !or the minterm %ill never occur7 or
• The output value !or the minterm is not use"
n these cases7 the output value nee" not e "e!ine"
nstea"7 the output value is "e!ine" as a F"ont care
*$ placing F"ont cares & an F+ entr$' in the !unction tale
or map7 the cost o! the logic circuit ma$ e lo%ere"
,+ample: logic !unction having the inar$ co"es !or the*CD "igits as its inputs Onl$ the co"es !or 0 through = are
use" The si+ co"es7 00 through never occur7 so the
output values !or these co"es are F+ . "onHt cares
Dont Cares in A-Maps
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Circuit Optimization 33
,+ample: *CD F5 or More
The map elo% gives a !unction &%7+7$7z' %hich is"e!ine" as P5 or moreP over *CD inputs 1ith the
"ont cares use" !or the > non-*CD cominations:
! the "onHt cares %ere treate" as 0Hs %e get:
. % + z / % + $ / % + $ &G . ;'
! the "onHt cares %ere Hs %e get:
; . % / + z / + $ &G . < etter'
z
w
0 / 3 2
4 5 7 6
/2 /3 /5 /4
- . // /0
/
/
//
/
0 0 0 0
0x
y
The selection o! "onHt cares
"epen"s on %hich comination
gives the simplest e+pression
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Circuit Optimization 34
6ro"uct-o!-Sums ,+ample
in" the optimum 6OS e+pression !or :&7 *7 C7 D' . J &87=77;787475' / J" &747>'
1here J" in"icates the "onHt care minterms
Solution: in" .
. * D / *
Optimum 6OS e+pression:
. &* / D' & / *'
Gate input cost &G . >'
J &07 ;7 57
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Circuit Optimization 35
S$stematic Simpli!ication
A +rime 'mplicant i a pro$uct term obtaine$ by combining t,ema%imum poible number o* a$;acent
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Circuit Optimization 36
D*
C*
*
D
,+ample o! 6rime mplicants
in" LL 6rime mplicants
C
*D
CD
*D
Onl$ ; ,ssential 6rime mplicants
D*
1 1
1 1
1 1
B
C
D
A
1 1
1 1
1
D
*
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Circuit Optimization 37
6rime mplicant 6ractice
in" all prime implicants !or&7 *7 C7 D' . J &07;78737=7077;787475'
* C
3 = 0
; 8 45
0 8 ;
5 >4 <
*
C
D
* D
8 prime implicants:
7 * C7 * D
ll 8 primeimplicants are
essential
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Circuit Optimization 3-
Optimization lgorithm
Fin$ all prime implicant 'nclu$e all essential prime implicant in t,e olution
Select a minimum cot et o* noneential prime
implicant to cover all minterm not yet covere$
+rime implicant election rule:
• inimi>e t,e overlap among prime implicant
• 'n particular# in t,e *inal olution# ma?e ure t,at eac,
prime implicant electe$ inclu$e at leat one minterm not
inclu$e$ in any ot,er prime implicant electe$
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Circuit Optimization 3.
Selection 9ule ,+ample
Simpli!$ &7 *7 C7 D' given on the A-map
*
D
C
*
D
C
,ssential
interm covere$ by eential prime implicant
Selecte"
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Circuit Optimization 40
Selection 9ule ,+ample %ith Dont Cares
Simpli*y F(A# B# C# 1) given on t,e map@
Selecte"
interm covere$ by eential prime implicant
+
+
+ +
+
*
D
C
+
+
+ +
+
*
D
C
,ssential
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Additional Gates and
t,er &ate 8ype
,y• Lo" cot implementation
• e*ul in implementing Boolean *unction
• Convenient conceptual repreentation
&ate clai*ication
• +rimitive gate a gate t,at can be $ecribe$ uing a
ingle primitive operation type (AD1 or E) plu
optional inverion()@
• Comple% gate a gate t,at re
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Additional Gates and
DAD1 &ate
8,e baic DAD1 gate ,a t,e *ollo"ing ymbol an$trut, table:
• AD1'nvert (DAD1) Symbol:
DAD1 repreent D8 AD1@ 8,e mall bubbleGcircle repreent t,e invert *unction
8,e DAD1 gate i implemente$ e**iciently in CS
tec,nology in term o* c,ip area an$ pee$
N
N Q
N ((D
00
00
0
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Additional Gates and
DAD1 &ate: 'nvertE Symbol
Applying 1eorganH La": 'nvertE 9 DAD1
8,i DAD1 ymbol i calle$ 'nvertE
• Since input are inverte$ an$ t,en Ee$ toget,er
AD1'nvert I 'nvertE bot, repreent DAD1 gate
• !aving bot, ma?e viuali>ation o* circuit *unction eaier
nli?e AD1# t,e DAD1 operation i D8 aociative
( DAD1 J) DAD1 K DAD1 (J DAD1 K)
N
N / . N Q . ((D
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Additional Gates and
DAD1 gate can implement any Boolean *unction DAD1 gate can be ue$ a inverter# or to
implement AD1 M E operation
A DAD1 gate "it, one input i an inverter
AD1 i e
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Additional Gates and
DE &ate
8,e baic DE gate ,a t,e *ollo"ing ymbol an$trut, table:
• E'nvert (DE) Symbol:
DE repreent D8 E @ 8,e mall bubbleG circlerepreent t,e invert *unction@
8,e DE gate i alo implemente$ e**iciently in
CS tec,nology in term o* c,ip area an$ pee$
N
N /
N (O9
0
0
0
0
000
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Additional Gates and
8,e DE &ate i alo niveral
DE gate can implement any Boolean *unction DE gate can be ue$ a inverter# or to implement
AD1 M E operation
A DE gate "it, one input i an inverter
E i e
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Additional Gates and
DAD1DAD1 'mplementation
Coni$er t,e Follo"ing S+ =%preion:
A 2level AD1E circuit can be converte$ eaily
to a DAD1DAD1 implementation
Z Y W XZ F +=
X
Z
W
Z
Y
F
X
Z
W
Z
Y
F
T%o successive ules
on the same line cancel
each other
X
Z
W
Z
Y
F
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Additional Gates andCircuits 50
t,er 8ype o* 2Level Circuit
t,er ue*ul type o* 2level circuit:• AD1E'DN=E8 9 AD1DE 9 DAD1AD1
• EAD1'DN=E8 9 EDAD1 9 DEE
AD1DE Function:
Similarly# EDAD1 circuit can be converte$ to DEE
Z X W XY F +=
X
Y
W
Z
X
F
X
Y
W
Z
X
F
NAND-AND
X
Y
W
Z
X
F
AND-NOR
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Additional Gates andCircuits 5/
t,er 8ype o* 2Level Circuit (2)
t,er ue*ul type o* 2level circuit:• AD1E'DN=E8 9 AD1DE 9 DAD1AD1
• EAD1'DN=E8 9 EDAD1 9 DEE
EDAD1 Function: ))(( Z X W Y X F +++=
X
Y
W
Z
X
F
X
Y
W
Z
X
F
NOR-OR
X
Y
W
Z
X
F
OR-NAND
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Circuit Optimization 52
t,er 8ype o* 2Level Circuit (3)
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Circuit Optimization 53
t,er 8ype o* 2Level Circuit (4)
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Additional Gates and
=%cluive E M =%cluive DE
8,e eNclusive-O9 &NO9' *unction i an importantBoolean *unction ue$ e%tenively in logic circuit
8,e E *unction may be:
• 'mplemente$ $irectly a an electronic circuit (true gate)
• 'mplemente$ by interconnecting ot,er gate type (E i
ue$ a a convenient repreentation)
8,e eNclusive-(O9 &N(O9' *unction i t,ecomplement o* t,e E *unction
E an$ DE gate are comple% gate
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Additional Gates and
E M DE 8able an$ Symbol
8,e DE i alo $enote$ a e#uivalence
NO9 N(O9 N N
⊕
0 0 0
0
0
0
N N⊕
0 0
0 0
0 0
NO9 S$mol N(O9 S$mol
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Additional Gates and
e *or E M DE
S+ =%preion *or EMDE:• 8,e E *unction i:
• 8,e ecluive DE (DE) *unction# ?no" alo a
e#uivalence i:
e *or t,e E an$ DE gate inclu$e:• A$$erMubtractorMmultiplier
• CounterMincrementerM$ecrementer
•+arity generatorMc,ec?er
Strictly pea?ing# E an$ DE gate $o no
e%it *or more t,at t"o input@ 'ntea$# t,ey are
replace$ by o"" an$ even *unction@
NNN
NNN
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Additional Gates and
E 'mplementation
N
N
N
N
SO6 implementation
!or NO9:
N ⊕ . N / N
((D onl$
implementation
!or NO9:
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Additional Gates and
$$ Function
8,e E *unction can be e%ten$e$ to 3 or more variable
For 3 or more variable# E i calle$ an o"" !unction
• 8,e *unction i / i* t,e total number o* / in t,e input i o""
NNNNN
N00 0 0
0
1N00 0 0
00
0
0
N ⊕ ⊕
1 ⊕ N ⊕ ⊕
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Additional Gates and
$$ an$ =ven Function
8,e / o* an o"" !unction correpon$ to input"it, an o"" numer o! s
8,e complement o* an o$$ *unction i calle$ an
even !unction
8,e / o* an even !unction correpon$ to input
"it, an even numer o! s
'mplementation o* o$$ an$ even *unction ue tree
ma$e up o* 2input E or DE gate
$$M i l i
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Additional Gates and
$$M=ven Function 'mplementation
1eign a 3input o$$ *unction "it, 2input E: 3input o$$ *unction:
F 9 ( ⊕ J) ⊕ K
1eign a 4input even *unction "it, 2input E an$
DE gate:
4input even *unction:
F 9 ( ⊕ ) ⊕ (J⊕ K)
N
1N
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+ it & t I C, ?
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+arity &enerator I C,ec?er
1eign an even parity generator an$ c,ec?er *or 3bit co$e
Solution: e 3bit o$$ *unction
to generate even parity bit
e 4bit o$$ *unction to c,ec?
*or error in even parity co$e
peration: (#J#K) 9 (0#0#/) give
(#J#K#+) 9 (0#0#/#/) an$ = 9 0
'* J c,ange *rom 0 to / bet"een
generator an$ c,ec?er t,en = 9 / in$icate an error
N
6
N
,
6
Sender Receiver
n-bit code Parity
Generator
(n+1)-bitcode
Parity
Checker Error
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