© 2011 Mentor Graphics Corp. Company Confidential www.mentor.com
Topics
About the Mechanical Analysis Division
Origins and Reasons for Thermal Design
Example Package-Level Thermal Simulation
FloTHERM’s Unique Technologies
User Interface Flexibility
Potential Die-Level Approaches
Concluding Remarks
JDP, Die-Level Design: Thermal Considerations, Oct. 2011 2
© 2011 Mentor Graphics Corp. Company Confidential www.mentor.com
Flomerics Acquires MicReD Thermal Transient Test & Measurement Tools, 2005
Our Corporate Journey…
3
Foundations in Brian Spalding’s CHAM Group & Imperial College London
Mentor Graphics acquires Flomerics for $60M, 2008
World-leading FloTHERM Product dominates
Electronics Cooling CFD with 66% of Market
First Versions of FloTHERM & FloVENT
Released, 1989-90
Mentor Graphics Mechanical Analysis Division Grows to be the 3rd largest Full-Footprint
CFD vendor in the World
Flomerics Acquires NIKA & its world-leading
MultiCAD-embedded CFD Software, 2006
FLOTHERM
FLOVENT
Flomerics founded by David Tatchell &
Harvey Rosten, 1988
General Manager Erich Buergel
© 2011 Mentor Graphics Corp. Company Confidential www.mentor.com
Mechanical Analysis Division Software & Hardware Solutions
Thermal Design of Electronics FloTHERM ™ – CFD* market leader in the electronics
vertical market Heating and Ventilation in Buildings
FloVENT ™ – optimizes airflow, temperature distribution and contamination control in and around buildings and in HVAC equipment
Data center cooling is a particular CFD focus Concurrent CFD for All Industries
FloEFD ™ – a paradigm shift in CFD: software that is fully embedded in the mechanical design environment
Test Equipment for Thermal Analysis and LEDs T3Ster ™ – thermal testing TERALED – optical testing of LEDs with
temperature control
T
t
T1 T2
∆ T
Popt(T,IF) WPE(T,IF) ΦV(T,IF)
* CFD = Computational Fluid Dynamics 4 JDP, Die-Level Design: Thermal Considerations, Oct. 2011
© 2011 Mentor Graphics Corp. Company Confidential www.mentor.com
Origins & Reasons for Thermal Design
Origins in computing: temperature affects clock speed
Legacy views of reliability (steady state temperature):
Current view, based on Physics-of-Failure approaches... Far more complex! — ΔT — ΔT/dt
But limiting TJ remains the main thermal design objective
6
(Source : US Air Force Avionics Integrity Program)
Major Causes of Electronics Failures
55% Temperature
19% Humidity
20% Vibration
6% Dust
Junction Life Statistics
(Source : GEC Research)
IBM’s Thermal Conduction Module
Solder Joint Cracking (Low-Cycle Fatigue) Die Attach Delamination
JDP, Die-Level Design: Thermal Considerations, Oct. 2011
© 2011 Mentor Graphics Corp. Company Confidential www.mentor.com
Example Package-Level Thermal Simulation Generic Modeling Approach
Build or import 3D geometry
Attach material properties
Apply or import* boundary conditions — Including heat sources
Mesh
Solve
Post-process results
*Often higher packaging levels are modelled to boundary conditions for smaller-scale models — For example, board-level to get boundary conditions for package-level modelling.
Models can be very simple in early conceptual design or very detailed in late design verification — Usually the same model is elaborated as the design evolves...
7 JDP, Die-Level Design: Thermal Considerations, Oct. 2011
© 2011 Mentor Graphics Corp. Company Confidential www.mentor.com
Example Package-Level Thermal Simulation System-Level Thermal Analysis
May start with a system level thermal analysis to explicitly calculate the boundary conditions at a package periphery
Alternatively, package boundary conditions could be prescribed
Same approach assures influence of package on die is correctly captured
Heat transfer coefficients set at each ‘cell’ face
8 JDP, Die-Level Design: Thermal Considerations, Oct. 2011
© 2011 Mentor Graphics Corp. Company Confidential www.mentor.com
Now that the boundary conditions are set, detailed package/die thermal analysis is performed — Multi-die 3D structure detailed — Power dissipation variation on each die can be imported — TSVs added, locations thermally optimized
Geometric structures on die surface not considered here
Example Package-Level Thermal Simulation Package Details
Peripheral boundary conditions
3D multi and stacked die
Many heat sources per die
9 JDP, Die-Level Design: Thermal Considerations, Oct. 2011
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Example Package-Level Thermal Simulation Power Map Import
Interface to Hyperlynx PI imports PCB-level, DC IR drop power dissipations for a +V net. – many thousands of heat sources
Same approach could be taken for power distribution on the die
Power Map CSV
10 JDP, Die-Level Design: Thermal Considerations, Oct. 2011
© 2011 Mentor Graphics Corp. Company Confidential www.mentor.com
Example Package-Level Thermal Simulation PCB Trace & Package Substrate Geometry
Have the ability to represent the distribution of metal within a PCB
Using the direct EDA interfaces, data is exported out of the EDA tool and imported into FLO/EDA, representing: — 3D board shape and
component layout information
— Stack-up definition
— A black & white image of the distribution of metal on each metallic layer
— A black & white image of the distribution of through hole vias
11 JDP, Die-Level Design: Thermal Considerations, Oct. 2011
© 2011 Mentor Graphics Corp. Company Confidential www.mentor.com
Example Package-Level Thermal Simulation PCB Trace & Package Substrate Geometry
A Layer is selected and its image ‘processed’ into a series of ‘Layer Patches’ — Rectangular regions with differing
Cu content — An orthotropic thermal conductivity
is calculated for each Layer Patch based on the distribution of Cu (black pixels) and FR4 (white pixels) in that region
Full control over the balance between accuracy vs. solution speed is available via slider bar control
Differing resolutions can be chosen for each layer depending on the application
If no processing is performed, a single % Cu value is used to create single block representing the layer
Exactly the same approach is taken for through hole vias
12 JDP, Die-Level Design: Thermal Considerations, Oct. 2011
© 2011 Mentor Graphics Corp. Company Confidential www.mentor.com
Example Package-Level Thermal Simulation Validation of Trace Image Processing Method
Thermal conductivity: Copper 400W/mK; FR4 0.4W/mK. Ratio 1000:1
13
Geometry Heat Flux Temperature
JDP, Die-Level Design: Thermal Considerations, Oct. 2011
Expl
icit
Trac
es
Smea
red
Trac
es
© 2011 Mentor Graphics Corp. Company Confidential www.mentor.com
Example Package-Level Thermal Simulation Results
Temperature Results available throughout package
I/O Layer
14 JDP, Die-Level Design: Thermal Considerations, Oct. 2011
© 2011 Mentor Graphics Corp. Company Confidential www.mentor.com
Example Package-Level Thermal Simulation Results
Temperature Results available throughout package
Processor Layer
15 JDP, Die-Level Design: Thermal Considerations, Oct. 2011
© 2011 Mentor Graphics Corp. Company Confidential www.mentor.com
Example Package-Level Thermal Simulation Results
Temperature Results available throughout package
Accelerator Layer
16 JDP, Die-Level Design: Thermal Considerations, Oct. 2011
© 2011 Mentor Graphics Corp. Company Confidential www.mentor.com
Example Package-Level Thermal Simulation *BN & SC ‘Design Change’ Tools
Largest Thermal Bottlenecks Displayed — Indicates where heat is moving and the thermal resistance is high
*Patent Pending 17 JDP, Die-Level Design: Thermal Considerations, Oct. 2011
© 2011 Mentor Graphics Corp. Company Confidential www.mentor.com
Example Package-Level Thermal Simulation *BN & SC ‘Design Change’ Tools
Potential Thermal Shortcuts Displayed — Indicates the optimal locations to create a new thermal path. In
this context, the shortcuts are TSVs
*Patent Pending 18 JDP, Die-Level Design: Thermal Considerations, Oct. 2011
© 2011 Mentor Graphics Corp. Company Confidential www.mentor.com
Example Package-Level Thermal Simulation *BN & SC ‘Design Change’ Tools - Example
Investigate where TSV should be placed from a purely thermal perspective for a selected die
Red Areas indicate best areas to create a
thermal shortcut
Design Change: Add TSVs within the best identified areas
*Patent Pending 19 JDP, Die-Level Design: Thermal Considerations, Oct. 2011
© 2011 Mentor Graphics Corp. Company Confidential www.mentor.com
Example Package-Level Thermal Simulation *BN & SC ‘Design Change’ Tools - Result
Targeted introduction of TSVs based on the Shortcut design tool results in a local thermal performance improvement
Thermal design evolves from this point by addressing further Shortcuts and Bottlenecks in other portions of the package with design changes
5
4
3
2
1
0
Thermal Improvement (%)
*Patent Pending 20 JDP, Die-Level Design: Thermal Considerations, Oct. 2011
© 2011 Mentor Graphics Corp. Company Confidential www.mentor.com
FloTHERM’s Technology Overview
FloTHERM is designed to handle: — Thousands and thousands of objects, powers, and attributes — Many millions of grid cells
Solving fundamental physics — Techniques apply at m, mm, and (sub) µm scales
Well suited to 3-D geometric complexity at package level — Same applies at die level
The example model had 12,000 objects, 14,000 power values, and 2.1 Million grid cells — A long way from pushing the limits of what’s possible: — Simulation time ~ 30 minutes on a Dell Precision M6400 laptop
Very robust — Meshing and solving can be done entirely in batch
21 JDP, Die-Level Design: Thermal Considerations, Oct. 2011
© 2011 Mentor Graphics Corp. Company Confidential www.mentor.com
FloTHERM’s Technology Meshing
Localized Grid Treatment — Our localized grid treatment,
where a region of fine mesh can be inserted into a larger, coarser mesh means that a coarse mesh can be used initially, and then refined as required based on the solution.
— There is no theoretical limit on the number of cells that can be included in the simulation
— We are quite able to handle sub-micron geometry
22 JDP, Die-Level Design: Thermal Considerations, Oct. 2011
© 2011 Mentor Graphics Corp. Company Confidential www.mentor.com
FloTHERM’s Technology Material Properties & Dynamic Heating
Temperature dependant material properties — We do have temperature dependent
thermal conductivity for silicon
Temperature-dependant dissipated power & Joule Heating — We can make heat sources a
function of temperature — Joule heating in the
interconnects, bond wires, traces — This could go some way to
capturing the effect of temperature on both leakage power
23 JDP, Die-Level Design: Thermal Considerations, Oct. 2011
© 2011 Mentor Graphics Corp. Company Confidential www.mentor.com
FloTHERM’s Technology Steady-State & Transient Simulations
Transient simulation — We handle both transient and
steady-state analysis. — If a transient simulation is
required we would need to know how the heat sources vary in time and prescribed at the start of the simulation.
Thermal mitigation — Define both time and
temperature dependent transient behaviour
— Power is controlled based on the temperature at a specified point in the model
24 JDP, Die-Level Design: Thermal Considerations, Oct. 2011
© 2011 Mentor Graphics Corp. Company Confidential www.mentor.com
User Interface Flexibility XML Import Capability
Our most recent work in interfacing has been to develop specialist bespoke links to other products using XML.
The FloTHERM XML schema supports all the necessary object and model descriptions (i.e., material, power, 3D geometry) to describe a package and IC thermal simulation, and full command line solutions are supported.
Working with both XML and Power Map CSV files are the recommended method for handling the inter-product data transfer needed for 3-D chip thermal simulations.
25 JDP, Die-Level Design: Thermal Considerations, Oct. 2011
© 2011 Mentor Graphics Corp. Company Confidential www.mentor.com
Potential Die-Level Approaches Trace Image Processing
In electrical terms, a 1000:1 conductivity ratio is approximately that between high and low doped silicon
Thermally, everything is very conductive, hence the temperature smears very quickly, even when there are a few discrete traces
Smearing is expected to be far greater in IC-like structures, where the conductors are interwoven in very closely-spaced layers:
This implies we can take exactly the same approach as we take at package level...
26 JDP, Die-Level Design: Thermal Considerations, Oct. 2011
© 2011 Mentor Graphics Corp. Company Confidential www.mentor.com
Potential Die-Level Approaches Pre-Design (Floorplanning, Power Budgeting)
27
Single cuboid for body of die
Functional regions on die surface assigned different
powers say ~100 regions
Back side of die held at constant temperature
Very quick – solves in minutes
Remainder of heat smeared over die
surface
JDP, Die-Level Design: Thermal Considerations, Oct. 2011
© 2011 Mentor Graphics Corp. Company Confidential www.mentor.com
Potential Die-Level Approaches Detailed Design (Pre-Tape Out Checks)
28
Single cuboid for body of die
~1000 x 1000 power map within the surface structure
(ALL heating sources)
Discrete cuboids capture different metallization in regions on die surface
~1,000, all same thickness
Power map ‘cells’ defined to capture geometric features
Boundary conditions on die from package-level
simulation
Monitor points can be used to check e.g. temperature
differences between key locations
Slower – solves in ~1 hour?
Temperatures along key conductors could be extracted post solution, based on results
JDP, Die-Level Design: Thermal Considerations, Oct. 2011
© 2011 Mentor Graphics Corp. Company Confidential www.mentor.com
Proposed Work Flow
Peripheral boundary conditions from pre-solved, larger scale FloTHERM Analysis
via XML format 3D FloTHERM Description of Package and multi-die
geometry via XML format
Power Maps for each die and Si interposer imported via XML or
Power Map CSV
29 JDP, Die-Level Design: Thermal Considerations, Oct. 2011
Power map exported from Apache
simulation results
Apache to XML/CSV convertor
© 2011 Mentor Graphics Corp. Company Confidential www.mentor.com
Proposed Work Flow
30 JDP, Die-Level Design: Thermal Considerations, Oct. 2011
Power Map
Package + Die Geometry Heat transfer coefficients set at each ‘cell’ face
Boundary Conditions
3D Temperature Distribution
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