Slide © 2019 Bhanushali & Davis
Development of FreePDK: An Open-Source Process Design Kit for Advanced Technology Nodes
Kirti Bhanushali, W. Rhett Davis (NCSU)
Free Silicon Conference (FSiC)March 15, 2019
NC STATE UNIVERSITY
1
Slide © 2019 Bhanushali & Davis
Motivation
Problem
» Restrictions on PDKs prevent sharing of design data, impede research & teaching
2
Slide © 2019 Bhanushali & Davis
Motivation
Problem
» Restrictions on PDKs prevent sharing of design data, impede research & teaching
Solution
» Provide a process design kit that mimics the complexity of a PDK you would get from any technology vendor.
» Free Predictive PDK, establishes a baseline for research & teaching in design, architecture, manufacturing, and automation
2
Slide © 2019 Bhanushali & Davis
Motivation
Problem
» Restrictions on PDKs prevent sharing of design data, impede research & teaching
Solution
» Provide a process design kit that mimics the complexity of a PDK you would get from any technology vendor.
» Free Predictive PDK, establishes a baseline for research & teaching in design, architecture, manufacturing, and automation
FreePDK45 accomplished this for 45nm, FreePDK15 for 15nm FinFET technology
2
Slide © 2019 Bhanushali & Davis
Licensing
FreePDK45
» Apache License 2.0
» SVRF(TM) click-through license agreement
FreePDK15 –
» 3-clause BSD license
» Click-through SVRF(TM) technology license agreement for both commercial and academic users
We jumped through multiple hoops before we were finally able to make it free for commercial use.
3
Slide © 2019 Bhanushali & Davis
Toolsets
This kit was developed in collaboration with Mentor Graphics, supports Calibre DRC, LVS, and xRC rules (Tested with Calibre2013.4_37.29)
4
Slide © 2019 Bhanushali & Davis
Toolsets
This kit was developed in collaboration with Mentor Graphics, supports Calibre DRC, LVS, and xRC rules (Tested with Calibre2013.4_37.29)
Technology library and display resources for Cadence Virtuoso
4
Slide © 2019 Bhanushali & Davis
Toolsets
This kit was developed in collaboration with Mentor Graphics, supports Calibre DRC, LVS, and xRC rules (Tested with Calibre2013.4_37.29)
Technology library and display resources for Cadence Virtuoso
HSPICE Simulation Models from the ASU 14nm PTM-MG HP model (http://ptm.asu.edu) with minor changes for compatibility with HSPICE
4
Slide © 2019 Bhanushali & Davis
Current Status/Future work
FreePDK15 – Enhancements to netlisting – Have a release for the FreePDK15 that will mainly get rid of the annoying fixHSPICEparam.py script.
FreePDK45 – Updates as it uses traditional Pcells
Any Feedback from this conference?
5
Slide © 2019 Bhanushali & Davis
Resources for using FreePDK
Tutorials that go through basic to slightly complex examples : https://www.eda.ncsu.edu/wiki/Tutorial:Contents
Kit version 1.2 is available for download
Standard cells are available from NanGate(Now Silvaco)https://www.silvaco.com/products/nangate/FreePDK15_Open_Cell_Library/index.html
6
Slide © 2019 Bhanushali & Davis
How did we develop this kit?
Use device models from ptm.asu.edu
7
Slide © 2019 Bhanushali & Davis
How did we develop this kit?
Use device models from ptm.asu.edu
Device/layout and layers dimensions from a published paper – Schuddinck et al.
7
Slide © 2019 Bhanushali & Davis
How did we develop this kit?
Use device models from ptm.asu.edu
Device/layout and layers dimensions from a published paper – Schuddinck et al.
Predict metal pitch/metal stack from ITRS roadmaps
7
Slide © 2019 Bhanushali & Davis
How did we develop this kit?
Use device models from ptm.asu.edu
Device/layout and layers dimensions from a published paper – Schuddinck et al.
Predict metal pitch/metal stack from ITRS roadmaps
Design rules - coded in SVRF language
7
Slide © 2019 Bhanushali & Davis
How did we develop this kit?
Use device models from ptm.asu.edu
Device/layout and layers dimensions from a published paper – Schuddinck et al.
Predict metal pitch/metal stack from ITRS roadmaps
Design rules - coded in SVRF language
Dielectric materials predicted from other publications
7
Slide © 2019 Bhanushali & Davis
How did we develop this kit?
Use device models from ptm.asu.edu
Device/layout and layers dimensions from a published paper – Schuddinck et al.
Predict metal pitch/metal stack from ITRS roadmaps
Design rules - coded in SVRF language
Dielectric materials predicted from other publications
LVS + Parasitic extraction rules defined
7
Slide © 2019 Bhanushali & Davis
How did we develop this kit?
Use device models from ptm.asu.edu
Device/layout and layers dimensions from a published paper – Schuddinck et al.
Predict metal pitch/metal stack from ITRS roadmaps
Design rules - coded in SVRF language
Dielectric materials predicted from other publications
LVS + Parasitic extraction rules defined
Standard cell library created by NanGate
7
Slide © 2019 Bhanushali & Davis
How did we develop this kit?
Use device models from ptm.asu.edu
Device/layout and layers dimensions from a published paper – Schuddinck et al.
Predict metal pitch/metal stack from ITRS roadmaps
Design rules - coded in SVRF language
Dielectric materials predicted from other publications
LVS + Parasitic extraction rules defined
Standard cell library created by NanGate
Design, iterate, fix issues and distribute…7
Slide © 2019 Bhanushali & Davis
Process Cross Section
What everyone should know: FinFETs & MOL layers
Thanks to Alex Toniolo (NanGate) for suggesting layers
Schuddinck, et al (IEDM 2012) suggested dimensions
Si
FinsGate
AIL1
•Active Interconnect Level-1
(AIL1)
AIL1
AIL2 AIL2
•Active Interconnect Level-2 (AIL2)
GIL
•Gate Interconnect Layer
(GIL)
•Layer Interconnect Overlap Level
Metal-1
•Level-2 Contact to Metal-1
•(Applies to AIL-2 and GIL)
•FEOL
•BEOL
8
Slide © 2019 Bhanushali & Davis
Width Quantization Of Active
Active width grows in increments of 40nm
» Weff = 2*Hfin + Wfin
» FinFETs have integer number of fins
48nm •
88nm 128nm
40nm
9
Slide © 2019 Bhanushali & Davis
Planar Device vs. FinFET
•Traditional planar
•MOSFinFET
in Layout View
FinFET
on Physical Mask
•FINS
•Fin Interconnect
10
Slide © 2019 Bhanushali & Davis
MOL Layers in Layout View
MOL Layers reduce resistance, improve density
Metal1
Interconnect
to Power rails
•Interconnect
PMOS & NMOS
Vias for connecting higher
metal layers to Gate and
Active interconnects
11
Slide © 2019 Bhanushali & Davis
Me
tal1
A
Me
tal1
B
Me
tal1
A
Me
tal1
A
•36nm •36nm•54nm
Multiple-Patterning Rules
Two colors for Gate, MOL, and 1X Metal Layers
Metal pitch for different colors is small
Metal pitch for the same color is larger
Optional uncolored layer post layout coloring (GATE only)
Also: Gate Cut Layer
12
Slide © 2019 Bhanushali & Davis
Other Restrictive RulesWidth and spacing is orientation-dependent, to account for off-axis illumination
Me
tal1
A
Metal1A•28nm
•56nm
13
Slide © 2019 Bhanushali & Davis
Other Restrictive RulesWidth and spacing is orientation-dependent, to account for off-axis illumination
AIL1, AIL2, GIL and GATE should not bend, to reduce pinching
Me
tal1
A
Metal1A•28nm
•56nm
13
Slide © 2019 Bhanushali & Davis
Other Restrictive RulesWidth and spacing is orientation-dependent, to account for off-axis illumination
AIL1, AIL2, GIL and GATE should not bend, to reduce pinching
Gate Cut rules: GATEC a negative mask. Rules identify break in connectivity if a GATEC layer is present. It allows denser layouts for four tiled inverters by breaking GATE connectivity where required
Me
tal1
A
Metal1A•28nm
•56nm
13
Slide © 2019 Bhanushali & Davis
Layout – Inverter
Dummy Gate
AIL1
AIL2
GIL
Inverter Layout
14
Slide © 2019 Bhanushali & Davis
NAND4
MINT1
M1B
GATEA
GATEB
NAND4 Layout
15
Slide © 2019 Bhanushali & Davis
Layout Density ComparisonFinFET inverter @14nm : MOS Inverter @45nm » Ideal shrink factor- 1:9
» Achieved shrink factor- 1:6
FinFET layout density is 1.3x MOSFET (Alioto, ICM 2009)
Cause» Width Quantization
» Higher Hfin for same Weff
Density Evaluation
16
Slide © 2019 Bhanushali & Davis
Complex layouts have been designed used this kit.
Standard cells are designed by NanGate/Silvaco
Students at NCSU have demonstrated complete SRAM designs using this technology
Complex Layouts
Inverter cell
NAND4 cell
17
Slide © 2019 Bhanushali & Davis
Layer propertiesWidths and pitches for metal layers derived from the Interconnect tables from ITRS 2011/Schuddinck et al. 2012
Min. width for the Metal1/MINT layer is 2x the minimum gate length.
The semi-global and global layer dimensions are derived from the ITRS-2011 tables.
Semi Global
M1x2
(130 nm thick)
Intermediate
M1x1
(60 nm thick)
M1 (60 nm thick)
Global
M1x4
(260 nm thick)
Metal 1 Pitch
18
Slide © 2019 Bhanushali & Davis
Layer PropertiesThe electrical characteristics of the layer stack chosen to follow [Schuddinck et al. 2012] and materials are chosen to provide approximate resistivity and dielectric constants predicted by ITRS.
Tetraethyl Orthosilicate (TEOS) - dielectric the metal layers
Silicon Nitride (SiN) - dielectric surrounding all the FEOL and MOL Layers,
AIL2 uses silicon dioxide SiO2
19
Slide © 2019 Bhanushali & Davis
Comparison - Fabricable PDK
FreePDK is not meant for fabrication
» It is realistic, based on assumptions and is not tied to any specific foundry
20
Slide © 2019 Bhanushali & Davis
Comparison - Fabricable PDK
FreePDK is not meant for fabrication
» It is realistic, based on assumptions and is not tied to any specific foundry
Design rules are not as extensive as a “Foundry kit”
» Most design rule types/groups are incorporated
» Foundry kit > 1000 design rules.
20
Slide © 2019 Bhanushali & Davis
Comparison - Fabricable PDK
FreePDK is not meant for fabrication
» It is realistic, based on assumptions and is not tied to any specific foundry
Design rules are not as extensive as a “Foundry kit”
» Most design rule types/groups are incorporated
» Foundry kit > 1000 design rules.
Number of device options limited
» FreePDK15 has limited MOS devices options, passive devices etc. Mostly geared towards digital design
» Gives you a good estimate on area and performance
20
Slide © 2019 Bhanushali & Davis
ConclusionFreePDK15 with DRC, LVS & PEX rules are now available since 2017, including new 15nm features and have been updated for bug fixes» FinFETs
» MOL Layers
» Multiple Patterning
How you can help» Feedback on design rules
» Other feedback through use
Future Release:» FreePDK15 – Enhancements to netllisting
» FreePDK15 – Updates as it uses traditional Pcells
21
Slide © 2019 Bhanushali & Davis
AcknowledgementPaul Franzon, NCSU
Alex Toniolo
Joseph Davis, Tarek Ramadan, Ahmed Hammed Fathy, Omar El-Sewefy , Ahmed El-Kordy, Hend Wagieh (Mentor Graphics)
P-Cells from Vikash Sharma and design rule fixes from Vidyanandgouda Patil. Thanks also to Namrata Sampat for help cleaning up the distribution.
Acknowledgements
22
Slide © 2019 Bhanushali & Davis
ReferencesP. Schuddinck, M. Badaroglu, M. Stucchi, S. Demuynck, A. Hikavyy, M. Garcia-Bardon, A. Mercha, A. Mallik, T. Chiarella, S. Kubicek, R. Athimulam, N. Collaert, N. Horiguchi, I. Debusschere, A. Thean, L. Altimime, and D. Verkest. 2012. “Standard cell level parasitics assessment in 20nm BPL and 14nmBFF,” In Electron Devices Meeting (IEDM), 2012 IEEE International. 25.3.1–25.3.4.
K. Bhanushali and W. R. Davis, "FreePDK15: An Open-Source Predictive Process Design Kit for 15nm FinFET Technology", In Proceedings of the 2015 Symposium on International Symposium on Physical Design (ISPD '15), pp. 165-170.
K. Bhanushali, "Design Rule Development for FreePDK15: An Open Source Predictive Process Design Kit for 15nm FinFET Devices," Masters Thesis, NCSU, 2014.
C. Tembe, "Layout and Parasitic Extraction for FreePDK15TM: An Open Source Predictive Process Design Kit for 15nm FinFET Devices," Masters Thesis, NCSU, 2015
J. E. Stine et al., "FreePDK: An Open-Source Variation-Aware Design Kit," 2007 IEEE International Conference on Microelectronic Systems Education (MSE'07), San Diego, CA, 2007, pp. 173-174.
23
Top Related