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Data flow & Behavioral Modeling
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Expressions,operators,operands
describes system in terms of expressions instead of primitive gates.
Expression formed using operands & operators.
Operands are data types used in ex
pression.they are :constant,parameter,net,register,bit select,part
select,memory element.
eg., c= a+ b => a, b,c operands
Operators act on operand to produce desired result.
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Logical Operators
&& p logical AND
|| p logical OR
! p logical NOT Operands evaluated to ONE bit value: 0, 1 or x
Result is ONE bit value: 0, 1 or x
A = 6; A && B p 1 && 0 p 0
B = 0; A || !B p 1 || 1 p 1
C = x; C || B p x || 0 p x but C&&B=0
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Bitwise Operators (i)
& p bitwise AND
| p bitwise OR
~
p bitwise NOT
^ p bitwise XOR
~^ or ^~ p bitwise XNOR
Operation on bit by bit basis
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Bitwise Operators (ii)
a = 4¶b1010;
b = 4¶b1100;
a = 4¶b1010;
b = 2¶b11;
c = ~a; c = a & b;
c = a ^ b;
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Reduction Operators
& p AND
| p OR
^ p XOR
~& pNAND ~| pNOR
~^ or ^~ p XNOR
One multi-bit operandp One single-bit resulta = 4¶b1001;..
c = |a; // c = 1|0|0|1 = 1
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Shift Operators
>> p shift right
<< p shift left
Result is same size as first operand, always zero
filled
a = 4¶b1010;...
d = a >> 2; // d = 0010
c = a << 1; // c = 0100
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Concatenation Operator
{op1, op2, ..} p concatenates op1, op2, .. tosingle number
Operands must be sized !!reg a;
reg [2:0] b, c;
..
a = 1b 1;
b = 3b 010;
c = 3b 101;
catx = {a, b, c}; // catx = 1_010_101
caty = {b, 2b11, a}; // caty = 010_11_1catz = {b, 1}; // WRONG !!
Replication ..
catr = {4{a}, b, 2{c}}; // catr = 1111_010_101101
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Relational Operators
> p greater than
< p less than
>= p greater or equal than
<= p less or equal than
Result is one bit value: 0, 1 or x
1 > 0 p 1
¶b1x1 <= 0 p x
10 < z p x
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Equality Operators
== p logical equality
!= p logical inequality
=== p case equality
!== p case inequality
± 4¶b 1z0x == 4¶b 1z0x p x
±
4¶b 1z0x != 4¶b 1z0xp
x ± 4¶b 1z0x === 4¶b 1z0x p 1
± 4¶b 1z0x !== 4¶b 1z0x p 0
Return 0, 1 or x
Return0
or1
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Conditional Operator
cond_expr ? true_expr : false_expr
Like a 2-to-1 mux ..
A
B
Y
sel
Y = (sel)? A : B;
0
1
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Arithmetic Operators (i)
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Arithmetic Operators (ii)
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Arithmetic Operators (iii)
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Arithmetic Operators (iv)
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Operator Precedence
Use parentheses toenforce your
priority
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Continuous Assignementsa closer look
Syntax:assign #del <id> = <expr>;
Where to write them: ± inside a module
± outside procedures
Properties:
± they all execute in parallel
± are order independent
± are continuously active
optional net type !!
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Example: Half Adder
module half_ adder(S, C, A, B);
output S, C;
input A, B;
wire S, C, A, B;
assign S = A ^ B;
assign C = A & B;
endmodule
Half
Adder
A
B
S
C
A
B
S
C
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Multiplexer
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Behavioral Model - Procedures (i)
Procedures = sections of code that weknow they execute sequentially
Procedural statements = statements inside
a procedure (they execute sequentially)
e.g. another 2-to-1 mux implem:begin
if (sel == 0)
Y = B;
else
Y = A;
end
ExecutionFlow Procedural assignments:
Y must be reg !!
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Behavioral Model - Procedures (ii)
Modules can contain any number of procedures
Procedures ex
ecute in parallel (in respect to eachother) and ..
.. can be expressed in two types of blocks:
±
initial p they execute only once ± always p they execute for ever (until simulation
finishes)
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Initial Blocks
Start execution at sim time zero and finish
when their last statement executesmodule nothing;
initial$display(³I¶m first´);
initial begin
#50;
$display(³Really?´);end
endmodule
Will be displayed
at sim time 0
Will be displayed
at sim time 50
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Always Blocks
Start execution at sim time zero andcontinue until sim finishes
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Events (i) @
always @(signal1 or signal2 or ..) begin..
end
always @(posedge clk) begin..
end
always
@(negedge c
lk)begin
..
end
execution triggers every
time any signal changes
execution triggers every
time clk changes
from 0 to 1
execution triggers every
time clk changes
from 1 to 0
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Examples
3rd half adder implemmodule half_ adder(S, C, A, B);
output S, C;
input A, B;
reg S,C;
wire A, B;
always @(A or B) begin
S = A ^ B;
C = A && B;
end
endmodule
Behavioral edge-triggered DFF
implemmodule dff(Q, D, Clk);
output Q;
input D, Clk;
reg Q;
wire D, Clk;
always @(posedge Clk)
Q = D;
endmodule
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Events (ii)
wait (expr)always begin
wait (ctrl)
#10 cnt = cnt + 1;
#10 cnt2 = cnt2 + 2;
end
e.g. Level triggered DFF ?
execution loops every
time ctrl = 1 (levelsensitive timing control)
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Example
a
b
c
Y
W
clk
resalways @(res or posedge clk) begin
if (res) begin
Y = 0;W = 0;
end
else begin
Y = a & b;
W = ~c;
endend
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Timing (i)
initial begin
#5 c = 1;#5 b = 0;
#5 d = c;end
0 5 10 15
Time
b
c
d
Each assignment isblocked by its previous one
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Timing (ii)
initial begin
fork#5 c = 1;
#5 b = 0;#5 d = c;
joinend
0 5 10 15
Time
b
c
d
Assignments are
not blocked here
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Procedural assignment
Assignment statement within an initial or analways statement .
2 kinds :i)blocking assignments (ii)non-blocking
Blocking: ³=³ operator is used.
statements executed in they order they arespecified. reg a = 2¶b 11;
reg b = reg a Non-blocking: ³<=³ operator used
allows scheduling without blocking executionof statements in sequential block.
always @ (posedge clk)
beginreg1 <= in1;
reg2 <= reg 1;//old value of reg1
end
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Timing controls Provides simulation time at which procedural
statements execute. 3 forms:1)delay based(2)event(3)level sensitive
Delay : i)regular :time between when statementis encountered and when executed.
# 3 a=2¶b11;
ii)intra-assignment :assignment to rightx = 0;z=0;
y = #10 x+z;
iii)zero delay : statement executed last
# 0 x=1;
Level sensitive: waits for certain condition to
be true before statement
wait(enable)
# 20 c=c+1;
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Contd.,
E
vent based tim
ing control: changein value on reg or net.
± Regular event: @(clk) q=d;
± Event or control:-transition on any
one ofm
ultiple signals.always @ ( rst or clk or d)
- Named event : declared by keyword
event, triggered by symbol.
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Block statements
Used to group multiple statement to acttogether.
Sequential block: begin and end ± executedsequentially.
Parallel block : fork and join ± executedconcurrently.
ordering controlled by delay.reg x,y;
reg[1:0]z,w;
initial
fork
x=1µb0; #5 y=1¶b1;# 10 z = {x,y};
# 20 w = {y,x};
join
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Procedural Statements: if
if (expr1)
true_stmt1;
else if (expr2)true_stmt2;
..
else
def_stmt;
E.g. 4-to-1 mux:module mux4_1(out, in, sel);output out;
input [3:0] in;
input [1:0] sel;
reg out;
wire [3:0] in;wire [1:0] sel;
always @(in or sel)
if (sel == 0)out = in[0];
else if (sel == 1)
out = in[1];else if (sel == 2)
out = in[2];else
out = in[3];
endmodule
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Procedural Statements: case
case (expr)
item_1, .., item_n: stmt1;
item_n+1, .., item_m: stmt2;
..
default: def_stmt;
endcase
E.g. 4-to-1 mux:module mux4_1(out, in, sel);
output out;
input [3:0] in;
input [1:0] sel;
reg out;wire [3:0] in;
wire [1:0] sel;
always @(in or sel)case (sel)0: out = in[0];
1: out = in[1];2: out = in[2];
3: out = in[3];endcase
endmodule
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Procedural Statements: forfor (init_assignment; cond;
step_assignment)
stmt;
E.g.module count(Y, start);
output [3:0] Y;
input start;
reg [3:0] Y;wire start;
integer i;
initial
Y = 0;
always @(posedge start)for (i = 0; i < 3; i = i + 1)
#10 Y = Y + 1;
endmodule
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Procedural Statements: while
while (expr) stmt;
E.g.module count(Y, start);
output [3:0] Y;
input start;
reg [3:0] Y;
wire start;
integer i;
initial
Y = 0;
always @(posedge start) begin
i = 0;
while (i < 3) begin#10 Y = Y + 1;
i = i + 1;
end
end
endmodule
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Procedural Statements: repeat
repeat (times) stmt;
E.g.module count(Y, start);
output [3:0] Y;
input start;
reg [3:0] Y;wire start;
initial
Y = 0;
always @(posedge start)
repeat (4) #10 Y = Y + 1;endmodule
Can be either an
integer or a variable
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Procedural Statements: forever
forever stmt;
Typical example:
clock generation in test modulesmodule test;
reg clk;
initial begin
clk = 0;
forever #10 clk = ~clk;end
other_ module1 o1(clk, ..);
other_ module2 o2(.., clk, ..);
endmodule
Executes until sim
finishes
Tclk = 20 time units
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Mixed Model
Code that contains various both structure and behavioral stylesmodule simple(Y, c, clk, res);
output Y;
input c, clk, res;
reg Y;
wire c, clk, res;wire n;
not(n, c); // gate-level
always @(res or posedge clk)
if (res)
Y = 0;
else
Y = n;
endmodule
c Y
clk
res
n
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