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Efficient FPGA
implementation of
convolution
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Aim
Design and efficient FPGA Implementation of
Convolution
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This project presents a direct method of reducing
convolution processing time using hardware computing
and implementations of discrete linear convolution of two
finite length sequences (!"#
The purpose of this research is to prove the feasi$ilit% of
an application specific integrated circuit (A&IC" that
performs a convolution on an acquired image in real time#
Introduction
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'an% image processing operations such as scaling and
rotation require resampling or convolution filtering for
each pi)el in the image #
Digital images can $e modified (through convolution"
$%
neigh$orhood operations* these operations go $e%ond
point wise operations+ and include smoothing+
sharpening+ and edge detection #
Convolution has man% applications which have great
significance in discrete signal processing#
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Project ,verviewIdentif% the Architecture From the literature surve%
'odel the Architecture into -T. /register transfer level0modeling
1erif% the functionalit% of 'odeled architecture in ',D2.&I'3
&%nthesis the verified design in !ilin) I&23
Generation of 4it map file for Dump into &partan 52 FPGA
Program the 4it map file into FPGA#
Post simulation in Chip&cope pro3#
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Digital image processing
-ealtime signal processing li6e
audio signal processing+
video7image processing+ or largecapacit% data
processing
Application
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Block Diagram
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Multiplexer 4*1 :
A multiple)er+ sometimes referred to as a 8multiple)or8 or
simpl% 8mu)8+ is a device that selects $etween a num$er of
input signals#
A multiple)er is a device which selects an% one of the
inputs from 9ninputs and directed to output depending on
nselect lines#
:ere each input is ;$it signed form and each output is also
a ;$it signed form
In convolution design we are using 9;
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'ultiple)ers ;
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Serial in parallel out lock!S"P#$ :
&erial in parallel out(&IP,"converts serial input intoparallel output#
:ere each serial input is ;$it signed form#
It ta6es serial input &I(? to 5" as a input and
produces four parallel outputs @?+@=+@9+@5 +each
parallel output is ;$it signed form
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&erial In Parallel ,ut -egisters>
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Binar% multiplier:
The $inar% multiplier used here is a ;$it multiplier which
ta6es two four inputs +each input is ;$it signed form and
gives an $it output#
The $inar% multiplier which is emplo%ed in convolution here
in the present project has a special characteristic that the
internal carr% will not $e forwarded to ne)t stage#
&o the num$er of outputs o$tained here is seven onl% $ecause
in $inar% multiplier the '&4 part is nothing $ut the carr%
o$tained from the second '&4 so as carr% is not forwarded
onl% seven $its will $e o$tained as output#
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Binar% Multiplier:
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'ultiple)er
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&egi'ter:
A -egister is a group of flipflops# Its
$asic function is to hold information within a digital
s%stem so as to ma6e it availa$le to the logic unitsduring the computing process# :owever+ a register
ma% also have additional capa$ilities associated with
it# It ma% have com$inational gates that perform
certain dataprocessing tas6s#
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&egi'ter:
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Advantages
The advantages of convolution $% proposed architecture has
following advantages>
-educe area
-educe Power
'ore speed
o data loss
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This implementation has the advantage of $eing optimiBed
$ased on operation+ power and area# To accuratel%
anal%Be our proposed s%stem+ we have coded our designusing the 1erilog hardware description language and have
s%nthesiBed it for FPGA products using I&2+ 'odelsim
DC compiler for other processor usage# &econd+ we
implemented an illustrative e)> ;!; convolver# &imilarl%+
the presented concept can $e e)tended on an ! case#
The functionalit% of the convolver was tested and verified
successfull% on a !I.II! &2 FPGA and design
compiler#
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'ultiple)ers>
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&erial In Parallel ,ut -egisters>
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Binar% Multiplier:
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'ultiple)er
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&egi'ter:
S t+ i & lt
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S%nt+e'i' &e'ult':&) Sc+ematic ,ie-:
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-T. Internal 1iew>
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).A/0 #2
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