COMPUTER ORGANIZATIONCSNB123
Systems and Networking 2
Expected Course Outcome# Course Outcome Coverage
1 Explain the concepts that underlie modern computer architecture, its evolution, functions and organization.
2 Identify the best organization of a computer for achieving the best performance when asked to make a selection from the current market.
3 Demonstrate the flow of an instruction cycle.
4 Differentiate types of memory components in terms of its technology and usage.
5 Convert integer and floating point numbers to its internal data representation.
6 Construct a series of computer instructions to perform low-level processor operations.
7 Explain the RISC and CISC computers, and single core and multi-core computers
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Second Generation
First Generation
Evolution
May 2014
Transistors
Scale Integration
ENIAC
Von Neumann Machine
UNIVAC IBM
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ENIAC
Von Neumann /
Turing Machine
UNIVAC IBM
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ENIAC• Electronic Numerical Integrator And Computer• Eckert and Mauchly• University of Pennsylvania• Trajectory tables for weapons • Started 1943• Finished 1946
Too late for war effort• Used until 1955
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ENIAC (2)• Decimal (not binary)• 20 accumulators of 10 digits• Programmed manually by switches• 18,000 vacuum tubes• 30 tons• 15,000 square feet• 140 kW power consumption• 5,000 additions per secondMay 2014
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ENIAC
Von Neumann /
Turing Machine
UNIVAC IBM
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Von Neumann / Turing Machine• Stored Program concept
Main memory storing programs and data ALU operating on binary data Control unit interpreting instructions from
memory and executing• Input and output equipment operated by
control unit
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Von Neumann / Turing Machine - Example
May 2014
http://www.arcadefire.com/wp/wp-content/uploads/2010/10/turing11.jpg
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Von Neumann Machine - Structure
May 2014
Main Memory (M)
I/O Equipment (I,O)
Central Processing Unit (CPU)
Arithmetic Logic Unit (CA)
Program Control Unit (CC)
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Von Neumann / Turing Machine (2)• Princeton Institute for Advanced Studies
IAS• Completed 1952
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IAS• 1000 x 40 bit words
Binary number 2 x 20 bit instructions
• Set of registers (storage in CPU) Memory Buffer Register Memory Address Register Instruction Register Instruction Buffer Register Program Counter Accumulator Multiplier Quotient
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IAS – Structure
May 2014
I/O Equipment (I,O)
Main Memory (M)
Arithmetic-logic Unit (ALU)
AC MQ
Arithmetic-logic Circuits
MBR
Program Control Unit
IBR PC
Control Circuits
IR MAR
Control Signals
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IAS Computer - Example
May 2014
http://www.comsci.us/history/images/ias.jpg
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ENIAC
Von Neumann /
Turing Machine
UNIVAC IBM
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Universal Automatic Computer (UNIVAC)
1947UNIVAC IEckert-Mauchly Computer Corporation
Late 1950UNIVAC IIPart of Sperry-Rand Corporation• Faster & more memory
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UNIVAC - Example
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http://archive.computerhistory.org/resources/still-image/UNIVAC/Univac_1.charles_collingwood.1952.102645279.lg.jpg
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ENIAC
Von Neumann /
Turing Machine
UNIVAC IBM
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IBM
1953The 701IBM 1st stored program computerScientific Calculations
1955The 702Business Applications
700/7000 series
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IBM 701
May 2014
http://www-03.ibm.com/ibm/history/exhibits/701/images/141511_Large.jpg
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IBM 702
May 2014
http://www.ed-thelen.org/comp-hist/BRL61-0396.jpg
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IBM 700/7000
May 2014
https://upload.wikimedia.org/wikipedia/commons/thumb/b/b9/NASAComputerRoom7090.NARA.jpg/280px-NASAComputerRoom7090.NARA.jpg
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Transistors• Made from Silicon (Sand)• Invented 1947 at Bell Labs• William Shockley et al.• Replaced vacuum tubes• Solid State device
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Advantages of Transistors• Smaller• Cheaper• Less heat dissipation
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Transistors Based Computers• Second generation machines• NCR & RCA produced small transistor
machines• IBM 7000• DEC - 1957
Produced PDP-1
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Microelectronics• Literally - “small electronics”• A computer is made up of gates, memory cells
and interconnections• These can be manufactured on a
semiconductor
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Overall Generations of Computer
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1946 -1957
1958 -1964
1965 1971 1971 -1977
1978 -1991
1991
Vacuum tube
Transistor Small scale integration
Medium scale integration
Large scale integration
Very large scale integration
Ultra large scale integration
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Moore’s Law
May 2014
Number of transistors on a chip will DOUBLE every
year
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Moore’s Law (2)• Gordon Moore – co-founder of Intel• Increased density of components on chip• Since 1970’s development has slowed a little
Number of transistors doubles every 18 months
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Moore’s Law (3)• Cost of a chip has remained almost unchanged• Higher packing density means shorter
electrical paths, giving higher performance• Smaller size gives increased flexibility• Reduced power and cooling requirements• Fewer interconnections increases reliability
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IBM 360 series• 1964• Replaced (& not compatible with) 7000 series• First planned “family” of computers
Similar or identical instruction sets Similar or identical O/S Increasing speed Increasing number of I/O ports (i.e. more terminals) Increased memory size Increased cost
• Multiplexed switch structureMay 2014
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DEC PDP-8• 1964• First minicomputer (after miniskirt!)• Did not need air conditioned room• Small enough to sit on a lab bench• $16,000
$100k+ for IBM 360• Embedded applications & OEM• Bus Structure
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Semiconductor Memory• 1970• Fairchild• Size of a single core
i.e. 1 bit of magnetic core storage• Holds 256 bits• Non-destructive read• Much faster than core• Capacity approximately doubles each year
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Intel
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Year Computer Name
Description
1971 4004 • First microprocessor• All CPU components on a single
chip• 4 bit
1972 8008 • 8 bit• Both designed for specific
applications1974 8080 • Intel’s first general purpose
microprocessor
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Speed Up• Pipelining• On board cache• On board L1 & L2 cache• Branch prediction• Data flow analysis• Speculative execution
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Performance Balance• Processor speed increased• Memory capacity increased• Memory speed lags behind processor speed
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Logic and Memory Performance Gap - Solutions
• Increase number of bits retrieved at one time Make DRAM “wider” rather than “deeper”
• Change DRAM interface Cache
• Reduce frequency of memory access More complex cache and cache on chip
• Increase interconnection bandwidth High speed buses Hierarchy of buses
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I/O Devices• Peripherals with intensive I/O demands• Large data throughput demands• Processors can handle this• Problem moving data
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I/O Devices - Solutions• Caching• Buffering• Higher-speed interconnection buses• More elaborate bus structures• Multiple-processor configurations
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Key is Balance• Processor components• Main memory• I/O devices• Interconnection structures
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Improvements in Chip Organization and Architecture
• Increase hardware speed of processor Fundamentally due to shrinking logic gate size• More gates, packed more tightly, increasing clock rate• Propagation time for signals reduced
• Increase size and speed of caches Dedicating part of processor chip • Cache access times drop significantly
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Improvements in Chip Organization and Architecture (2)
• Change processor organization and architecture Increase effective speed of execution Parallelism
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Problems with Clock Speed and Login Density
• Power Power density increases with density of logic and clock speed Dissipating heat
• RC delay Speed at which electrons flow limited by resistance and
capacitance of metal wires connecting them Delay increases as RC product increases Wire interconnects thinner, increasing resistance Wires closer together, increasing capacitance
• Memory latency Memory speeds lag processor speeds
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Problems with Clock Speed and Login Density - Solution
• More emphasis on organizational and architectural approaches
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Increased Cache Capacity• Typically two or three levels of cache between
processor and main memory• Chip density increased
More cache memory on chip• Faster cache access
• Pentium chip devoted about 10% of chip area to cache
• Pentium 4 devotes about 50%
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More Complex Execution Logic• Enable parallel execution of instructions• Pipeline works like assembly line
Different stages of execution of different instructions at same time along pipeline
• Superscalar allows multiple pipelines within single processor Instructions that do not depend on one another
can be executed in parallel
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Diminishing Returns• Internal organization of processors complex
Can get a great deal of parallelism Further significant increases likely to be relatively
modest• Benefits from cache are reaching limit• Increasing clock rate runs into power
dissipation problem Some fundamental physical limits are being
reached
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New Approach – Multiple Cores• Multiple processors on single chip
Large shared cache• Within a processor, increase in performance
proportional to square root of increase in complexity
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New Approach – Multiple Cores (2)• If software can use multiple processors,
doubling number of processors almost doubles performance
• So, use two simpler processors on the chip rather than one more complex processor
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New Approach – Multiple Cores (3)• With two processors, larger caches are
justified Power consumption of memory logic less than
processing logic
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x86 Evolution
May 2014
• x86 architecture dominant outside embedded systems
• Organization and technology changed dramatically• Instruction set architecture evolved with
backwards compatibility• ~1 instruction per month added• 500 instructions available• See Intel web pages for detailed information on
processors
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x86 Evolution (2)Version Description
8080 • first general purpose microprocessor• 8 bit data path• Used in first personal computer – Altair
8086 • 5MHz – 29,000 transistors• much more powerful• 16 bit • instruction cache, prefetch few instructions
8088 • (8 bit external bus) used in first IBM PC• 1Mb
80286 • 16 Mbyte memory addressable• up from 1Mb
80386 • 32 bit• Support for multitasking
80486 • sophisticated powerful cache and instruction pipelining• built in maths co-processor
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x86 - 8080
May 2014
http://www.antiquetech.com/pictures%20full-size/C8080A.jpg
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x86 Evolution (3)Version Description
Pentium • Superscalar• Multiple instructions executed in parallel
Pentium Pro
• Increased superscalar organization• Aggressive register renaming• branch prediction• data flow analysis• speculative execution
Pentium II • MMX technology• graphics, video & audio processing
Pentium III • Additional floating point instructions for 3D graphics
Pentium 4 • Note Arabic rather than Roman numerals• Further floating point and multimedia
enhancements
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x86 - Pentium
May 2014
http://www.notebookcheck.net/uploads/tx_nbc2/intel_pentium_e5700_03.jpg
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x86 Evolution (4)Version DescriptionCore • First x86 with dual coreCore 2 • 64 bit architectureCore 2 Quad • 3GHz – 820 million transistors
• Four processors on chip
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x86 – Core 2
May 2014
http://www.starbaseonline.com/hardware/Core2Duo.jpg
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Additional Reference• William Stallings, Computer Organization and
Architecture: Designing for Performance, 8th. Edition, Prentice-Hall Inc., 2010
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