Clock Generation for a SHA-less 10-bit 100Mhz Pipeline ADCVictor Lu, Pingli Huang, Yun Chiu

Illinois Center forWireless Systems

100u

A

25uA

25uA

25uA

25uA

300u

A

200u

A

AC-coupledDifferential Amplitude: 750mVFrequency: 200Mhz

÷2

100Mhz

Square Wave Generation

• Generating square wave on-chip from differential sine-wave input is believed to produce lower jitter.• Differential architecture rejects common-mode noise.• Jitter simulation performed using Spectre transient noise analysis.•The above circuit has been used previously in [2] and [3]

Sampling Clock

Input Signal

clk1d_comp

Last 4 bits ready

First 3.5 bits ready

Second 3.5 bits ready

clk1 clk2 clk1clk2

Com

para

tor

top

plat

e

Com

para

tor

botto

m p

late

S/H

top

plat

e

S/H

bot

tom

pla

te

Stage2

Stage1

Stage3

Pre

-Am

ping

and

Diff

eren

cing

Latc

h R

egen

erat

ion

Residue Amplification

Differencing RA Outputfrom Stage1 with

Sampled Reference Latc

hR

egen

erat

ion

The

rmom

eter

cod

e la

tech

ed

The

rmom

eter

code

latc

hed

Tra

ckin

g A

DC

Inp

ut

Residue Amplification

Latch RegenerationDifferencing RA Output

from Stage2 withSampled Reference

“Tracking” reference

Ref

eren

ce s

ampl

edby

bot

tom

pla

te

“Tracking” reference

Ref

eren

ce s

ampl

edby

bot

tom

pla

te

clk1_comp

clk1_SH clk1_SH

clk1_compclk3

clk1d_comp

clk3

clk2

Input Square Wave

Buffer

Buffer

Buffer

Buffer Buffer

Buffer

Buffer

clk2

clk1

clk1e

clk1e_comp

clk1_comp

clk1d_comp

clk3_comp

clk2e

Buffer

Buffer

clk1e_SHClock Phase Generation

Pipeline ADC Timing Scheme

[1] P. Huang, “A Gradient-Based Digital Algorithm for Sampling Clock Skew Calibration of SHA-less Pipeline ADCs”[2] C. Jing, “A Clock Generator and Output Buffer for 12-bit, 75-MS/s, 3.3-V CMOS ADC with SFDR 85dB,” MS Thesis, University of California at Los Angeles, 1999[3] A. M. A. Ali, et al, “A 14-bit 125 MS/s IF/RF Sampling Pipelined ADC with 100dB SFDR and 50 fs Jitter,” IEEE J. Solid-State Circuits, Vol. 41, No. 8, August 2006

Overview A clock generation and timing scheme for a SHA-less pipeline ADC is presented. Research Objectives Sampling clock jitter is known to degrade performance of sampling circuits (Fig.1), especially for input signals containing high frequency components. The problem of minimizing jitter is thus important in the design of high bandwidth ADCs. The plan is to first explore and analyze the mechanisms from which jitter may arise (thermal noise, supply bouncing) and then to devise circuit techniques to suppress these sources.

• Calibration of signal and clock skew, arising from the lack of a front-end SHA (sample and hold amplifier), is achieved by adjusting By adjusting the timing of clk1e_comp using the algorithm presented in [1].

Fig. 1: Uncertainty in sampling time results in sampling error.

Falling edge of clk1e_comp, clk1e_comp, and clk1d_comp adjusted via variable delay cell

Variable delay cell

Jitter important for these edges