8/17/2019 cad for vlsi 1.pptx
1/284
CAD for IC design
8/17/2019 cad for vlsi 1.pptx
2/284
VLSI Design Problem:
Optimization of design in several aspectsArea Minimization*Speed*Power dissipation*
Design time* Testability*
Design MethodologiesApproac followed to solve te !"SI design
problem
8/17/2019 cad for vlsi 1.pptx
3/284
To consider all parameters in one go d#ring !"SI design process we #se$
Cost function$ meas#re of !"SI design cost in terms of di%erentparameters
To design a !"SI circ#it at one go wile at te same time optimizingthe cost functions comple&ity is simply too ig
To #nderstand comple&ity Two main concepts are elpf#l to deal wit tis comple&ity
'( )ierarcy and( Abstraction
Hierarchy$ sows te str#ct#re of a design at di%erent levelsbstraction: ides te lower level details
8/17/2019 cad for vlsi 1.pptx
4/284
bstraction e!:
8/17/2019 cad for vlsi 1.pptx
5/284
"he Design Domains
"he beha#ioral domain($ Part of te design +or te wole, is seenas set of blac- bo&es
$lac% bo!$ relations between o#tp#ts and inp#ts are given wito#t areference to te implementation of tese relations(
"he structural domain$• Circ#it is seen as te composition of s#bcirc#its(• .ac of te s#bcirc#its as a description in te beavioral
domain or a description in te str#ct#ral domain itself
"he physical &or layout ' domain Te pysical domain gives information on ow te s#bparts tat
can be seen in te str#ct#ral domain/ are located on te two0dimensional plane(
8/17/2019 cad for vlsi 1.pptx
6/284
Design Methods and "echnologies
full(custom design:ma&imal freedomability to determine te sape of every mas- layer for te
prod#ction of die cip(Semicustom:• smaller searc space• limiting te freedom of te designer
• sorter design time• semic#stom design implies te #se of gate arrays/ standardcells/ parameterizable modules
designing an integrated circuit is
a se)uence of many actions most of wic can be done bycomputer tools
8/17/2019 cad for vlsi 1.pptx
7/284
*ated arrays• cips tat ave all teir transistors preplaced in reg#lar patterns(
• designer specify te wiring patterns• gate arrays as described above are mas% programmable
• Tere also e&ist so0called +eld(programmable gate arrays +1P2As,• Interconnections can be con3g#red by applying electrical signals
on some inp#ts(
Standard Cells• simple logic gates/ 4ip04ops/ etc(• Predesigned and ave been made available to te designer in a
library• characterization of the cells: determination of teir timing
beavior is done once by te library developer
Module *enerators• generators e&ist for tose designs tat ave a reg#lar str#ct#re s#c
as adders/ m#ltipliers/ and memories(• D#e to te reg#larity of te str#ct#re/ te mod#le can be described
by one or two parameters(
8/17/2019 cad for vlsi 1.pptx
8/284
!"SI design a#tomation tools$Can be categorized in$
'( Algoritmic and system design
( Str#ct#ral and logic design5( Transistor0level design6( "ayo#t design7( !eri3cation8( Design management
8/17/2019 cad for vlsi 1.pptx
9/284
lgorithmic and System Design:• mainly concerned wit te initial algorithm to be implemented in
ardware and wor-s wit a p#rely beha#ioral description(
• )ardware description lang#ages +)D"s, are #sed for te p#rpose(• A second application of formal description is te possibility ofautomatic synthesis
• syntesizer reads te description and generates an e9#ivalentdescription of te design at a m#c lower level(
• High(le#el synthesis: Te syntesis from te algoritmicbeavioral level to str#ct#ral descriptions is called ig0levelsyntesis(
• Silicon Compiler $ A silicon compiler is a software system tat ta-esa #ser:s speci3cations and a#tomatically generates an integrated
circ#it +IC,( +initial syntesizer,
• formal speci3cation does not always need to be in a te&t#al• Tools available aving capability to con#ert the graphical
information into a te!tual e9#ivalent +e&pressed in a lang#ageli-e !)D", tat can be accepted as inp#t by a syntesis tool(
8/17/2019 cad for vlsi 1.pptx
10/284
Hard,are(soft,are co(design• Design for a comple& system will consist of several cips/ some of
wic are programmable(• Part of te speci3cation is realized in ardware and some of wic in
software( +ardware0software co0design,• partitioning of te initial speci3cation re9#ired +di;c#lt to
a#tomate,• tools e&ist tat s#pport te designer• by providing information on te fre9#ency at wic eac part of
te speci3cation is e&ec#ted(• te parts wit te igest fre9#encies are te most li-ely to berealized in ardware(
• Te result of co(design$• is a pair of descriptions$
• one of te ardware +e(g( in !)D", tat will contain programmableparts/ and• te oter of te software +e(g( in C,(
8/17/2019 cad for vlsi 1.pptx
11/284
Code generation $Mapping te ig0level descriptions of te software to te low0level
instr#ctions of te programmable ardware $ CAD problem(
Hard,are(soft,are co(simulation$!eri3cation of te correctness of te res#lt of co0design #singsim#lation(
8/17/2019 cad for vlsi 1.pptx
12/284
• Structural and Logic Design• Sometimes te tools migt not be able to cope wit te desired
beavio#r$ ine;cient syntesis• Designer provides lower level description $Str#ct#ral and "ogic
Design• designer can #se a schematic editor program$ CAD tool• It allows te interacti#e speci+cation of te bloc-s composing
a circ#it and teir interconnections by means of a grapicalinterface(
• scematics constr#cted in tis way are hierarchical
• -ole of simulation$ Once te circ#it scematics ave beencapt#red by an editor/ it is a common practice to verify te circ#it bymeans of sim#lation
• fault simulation$ cec-s weter a set of test vectors or testpatterns +inp#t signals #sed for testing, will be able to detect fa#ltsca#sed by imperfections of te fabrication process
• automatic test(pattern generation$• te comp#ter searc for te best set of test vectors by #sing a
tool $ ATP2(
8/17/2019 cad for vlsi 1.pptx
13/284
Logic synthesis:2eneration and optimization of a circ#it at te level of logic gates(tree di%erent types of problems$
./ Synthesis of t,o(le#el combinational logic$•
8/17/2019 cad for vlsi 1.pptx
14/284
"iming constraints:• designer so#ld be informed abo#t te ma!imum delay paths• sorter tese delays/ te faster te operation of te circ#it
• One possibility of 3nding o#t abo#t tese delays is by means ofsimulation• Or by timing analysis tool: comp#te delays tro#g te circ#it
wito#t performing any sim#lation
8/17/2019 cad for vlsi 1.pptx
15/284
"ransistor(le#el Design "ogic gates are composed of transistorsDepending on te acc#racy re9#ired/ transistors can be sim#lated atdi0erent le#els
At te s,itch le#el / transistors are modeled as idealbidirectional switces and te signals are essentially digital
At te timing le#el / analog signals are considered/ b#t tetransistors ave simple models +e(g( piecewise linear f#nctions,
At te circuit le#el / more acc#rate models of te transistors are#sed wic ofteninvolve nonlinear di%erential e9#ations for te c#rrents and
voltages
more accurate te model/ te more comp#ter time is necessary forsim#lation
8/17/2019 cad for vlsi 1.pptx
16/284
Process +f#ll0c#stom Transistor0level design,$
'( it is te c#stom to e&tract te circ#it from te layo#t data of
transistor(( Constr#ct te networ- of transistors/ resistors and
capacitances(5( Te e&tracted circ#it can ten be sim#lated at te circ#it or
switc level(
8/17/2019 cad for vlsi 1.pptx
17/284
Layout DesignDesign actions related to layo#t are very di#erse terefore/di0erent layout tools/ If one as te layo#t of te s#bbloc-s of a design available/ togeterwit te list of interconnections ten
'( 1irst/ a position in te plane is assigned to eac s#bbloc-/trying to minimize te area to be occ#pied byinterconnections &placement problem'(
( Te ne&t step is to generate te wiring patterns tat realizete correct interconnections +routing problem,(
goal of placement and ro#ting is to generate te minimal chiparea&.'/
"iming constraint &1'$ As te lengt of a wire a%ects tepropagation time of a signal along te wire/ it is important to -eepspeci3c wires sort in order to g#arantee an overall e&ec#tion speedof te circ#it( +timing(dri#en layout'
8/17/2019 cad for vlsi 1.pptx
18/284
Partitioning problem: gro#ping of te s#b0bloc-s
• S#bbloc-s tat are tigtly connected are p#t in te same group
wile te n#mber of connections from one gro#p to te oter is-ept low• Partitioning helps to solve te placement problem
2loorplanning$
• Te simultaneous de#elopment of structure and layout iscalled 4oorplanning(
• wen ma-ing a transition of a beavioral description to astr#ct#re/ one can also 3&es te relative positions of te s#bbloc-s
• It gives early feedbac% on e(g( long wires in te layo#t
• Detailed layo#t information is available in placement wereas4oorplanning as mainly to deal wit estimations( &di0erence'
8/17/2019 cad for vlsi 1.pptx
19/284
• microcells($ comple&ity of aro#nd '> transistors• A cell compiler generates te layo#t for a networ- of transistors(
• Module$ A bloc-/ layo#t of wic can be composed by anarrangement of cells(• Module generation$ 2iven some parameters +e(g( te n#mber of
bits for an adder or te word lengt and n#mber of words in amemory,/
• te mod#le generator p#ts te rigt cells at te rigt place and
composes a mod#le in tis way(
• Layout editor +In f#ll0c#stom design,$ provides te possibility tomodify te layo#t at te level of mas- patterns(
• In a correct design/ te mas- patterns so#ld obey some r#lescalled design rules/
• Tools tat analyze a layo#t to detect violations of tese r#les arecalled design(rule chec%ers/
8/17/2019 cad for vlsi 1.pptx
20/284
Circuit e!tractor$ ta-es te mas- patterns as its inp#t andconstr#cts a circ#it of transistors/ resistors and capacitances tat canbe sim#lated
disad#antage of full(custom design is tat te layo#t as to beredesigned wen te tecnology canges( symbolic layo#t as beenproposed as a solution(
Symbolic representation represents positions of te patternsrelative to eac oter(
Compactor$ ta-es te symbolic description/ assigns widts to allpatterns and spaces te patterns s#c tat all design r#les are
satis3ed(
8/17/2019 cad for vlsi 1.pptx
21/284
Veri+cation Methods$ Tere are tree ways of cec-ing tecorrectness of an integrated circ#it wito#t act#ally fabricating it
'( Prototyping( Sim#lation5( 1ormal veri3cation
./ Prototyping$ b#ilding te system to be designed from discretecomponents rater tan one or a few integrated circ#its e&(
8/17/2019 cad for vlsi 1.pptx
22/284
( Simulation: modelling a comp#ter model of all relevant aspects ofte circ#it/ e&ec#ting te model for a set of inp#t signals/ andobserving te o#tp#t signals(
it is impossible to ave an e&a#stive test of a circ#it of reasonablesize/ as te set of all possible inp#t signals and internal states growstoo large(
5( 2ormal #eri+cation$ #se of matematical metods to prove tat a
circ#it is correct(
8/17/2019 cad for vlsi 1.pptx
23/284
Design Management "ools$• CAD tools cons#me and prod#ce design data• 9#antity of data for a !"SI cip can be enormo#s and
• appropriate data management tecni9#es ave to be #sed to storeand retrieve tem e;ciently(
• anoter aspect of design management is to maintain a consistentdescription of te design wile m#ltiple designers wor- on di%erentparts of te design(
• famo#s standard format for storing data is 3DI2 +.lectronic DesignIntercange 1ormat,
• 2rame,or% is an #niversal interface #sed by tools to e&tract .DI1data from database(
8/17/2019 cad for vlsi 1.pptx
24/284
4/ lgorithmic *raph "heory and Computational Comple!ity:
lgorithmic graph theory: design of algoritms tat operate ongraps
*raph: A grap is a matematical str#ct#re tat describes a set ofob@ects and te connections between tem(
2raps are used in te 3eld of design a#tomation for integratedcirc#its
'( wen dealing wit entities tat nat#rally loo- li-e a networ- +e(g( acirc#it of transistors,
( in more abstract cases +e(g( precedence relations in tecomp#tations of some algoritm(
Computational comple!ity$ time and memory re9#ired by a certainalgoritm as f#nction of te size of te algoritm:s inp#tB(
8/17/2019 cad for vlsi 1.pptx
25/284
Terminology$A grap 2+!/ ., is caracterized by two sets$'( a verte& set ! +node, and( an edge set . +branc,
Te two vertices tat are @oined by an edge are called te edge:sendpoints/ notation +#/ v, is #sed(
Te vertices # and v s#c tat +#/ v, ./ are called ad5acent vertices(
8/17/2019 cad for vlsi 1.pptx
26/284
Subgraph: en one removes vertices and edges from a givengrap 2/ one gets a s#bgrap of 2(-ule$ removing a verte& implies te removal of all edges connectedto it(
Complete graph : a complete graph is a simple#ndirected graph in wic every pair of distinct vertices isconnected by a #ni9#e edge(
Digraph: a directed graph +or digraph, is a grap/ or set of
nodes connected by edges/ were te edges ave a directionassociated wit tem(
Complete digraph$ A complete digrap is a directed graph inwic every pair of distinct vertices is connected by a pair of #ni9#eedges +one in eac direction,(
8/17/2019 cad for vlsi 1.pptx
27/284
Cli)ue$ a cli9#e in an #ndirected grap is a s#bset of its vertices s#ctat every two vertices in te s#bset are connected by an edge(A s#bgrap tat is complete
tree cli9#es identi3ed by te verte& sets E!' / !/ !5F/ E!5/ !6F andE!7/ !8F
8/17/2019 cad for vlsi 1.pptx
28/284
Ma!imal cli)ue: A ma&imal cli9#e is a cli9#e tat cannot be e&tendedby incl#ding one more ad@acent verte&/it is not a s#bset of a larger cli9#e(
degree of a #erte!$ Te degree of a verte& is e9#al to te n#mber ofedges incident wit it
Sel7oop: An edge +#/ #,/ i(e( one starting and 3nising at te same
verte&/ is called a sel4oop(
8/17/2019 cad for vlsi 1.pptx
29/284
Parallel edges$ Two edges of te form e'G +v' / v, and e G +v' /v,/ i(e( aving te same endpoints/ are called parallel edges(
Simple graph: A grap wito#t sel4oops or parallel edges is called a
simple grap
8/17/2019 cad for vlsi 1.pptx
30/284
A grap wito#t sel4oops b#t wit parallel edges is called amultigraph(
bigraph $ a bipartite grap +or bigrap, is a grap wose vertices can
be divided into two dis@oint sets H and ! +tat is/ H and ! are eacindependent sets, s#c tat every edge connects a verte& in H to one in!(
8/17/2019 cad for vlsi 1.pptx
31/284
Planar(graph: A grap tat can be drawn on a two0dimensionalplane wito#t any of its edges intersecting is called planar(
Path$ A se9#ence of alternating vertices and edges/ starting and
3nising wit a verte&/ s#c tat an edge e G +#/ v, is preceded by #and followed by v in te se9#ence +or vice versa,/ is called a pat( .&
Te length of a path e9#als te n#mber of edges it contains
A pat/ of wic te 3rst and last vertices are te same and te
lengt is larger tan zero/ is called a cycle +sometimes also$ loop orcirc#it,(
A pat or a cycle not containing two or more occ#rrences of tesame verte& is a simple path or cycle(
8/17/2019 cad for vlsi 1.pptx
32/284
Connected graph: If all pairs of vertices in a grap are connected/ tegrap is called a connected graph
Connected component$ a connected component is a s#bgrap
ind#ced by a ma&imal s#bset of te verte& set/ s#c tat all pairs in teset are connected
In(degree$ Te in0degree of a verte& is e9#al to te n#mber of edgesincident to it
out(degree$ o#t0degree of an edge is e9#al to te n#mber of edgesincident from it(
strongly connected #ertices$ Two vertices # and v in a directedgrap are called strongly connected if tere is bot a directed patfrom # to v and a directed pat from # to #(
strongly connected components$ In te matematical teory ofdirected graps/ a grap is said to be strongly connected if everyverte& is reacable from every oter verte&(
8/17/2019 cad for vlsi 1.pptx
33/284
A ,eighted graph is a grap in wic eac branc is given an#merical weigt(
a special type of labeled grap in wic te labels are n#mbers
+wic are #s#ally ta-en to be positive,(
8/17/2019 cad for vlsi 1.pptx
34/284
To implement grap algoritms s#itable data str#ct#res are re9#iredDi%erent algoritms re9#ire di%erent data0str#ct#res(
ad5acency matri!: If te grap 2+!/ ., as n vertices/ an n&n matri&A is #sed(
Te ad@acency matrices of #ndirected graps are symmetric(
8/17/2019 cad for vlsi 1.pptx
35/284
1inding all vertices connected to a given verte& re9#ires inspectionof a complete row and a complete col#mn of te matri& +not verye;cient,
ad5acency list representation: It consists of an array tat as asmany elements as te n#mber of vertices in te grap(• Array element identi3ed by an inde& i corresponds wit te verte&
#(• .ac array element points to a lin%ed list tat contains te
indices of all vertices to wic te verte& corresponding to teelement is connected(
8/17/2019 cad for vlsi 1.pptx
36/284
8/17/2019 cad for vlsi 1.pptx
37/284
Te comple!ity beavio#r of an algoritm is caracterized bymatematical f#nctions of te algoritm:s ?inp#t sizeJ(
Te input size or problem size of an algoritm is related to te n#mber
of symbolsnecessary to describe te inp#t(
.&$ a sorting algoritm as to sort a list of n words/ eac consisting of atmost '> lettersinp#t size G'>n
#sing te ASCII code tat #ses K bits for eac letterinp#t size GK>n
Two types of computational comple!ity are disting#ised$'( time comple&ity/ wic is a meas#re for te time necessary to
accomplis a comp#tation/
( space comple&ity wic is a meas#re for te amo#nt of memoryre9#ired for a comp#tation(
Space comple&ity is given less importance tan time comple&ity
8/17/2019 cad for vlsi 1.pptx
38/284
8rder of a function$
8/17/2019 cad for vlsi 1.pptx
39/284
algoritm:s time comple&ities$
8/17/2019 cad for vlsi 1.pptx
40/284
3!amples of *raph lgorithms: Depth(+rst Search: • To traverse te grap• to visit all vertices only once
• A new member mar-B in te verte&str#ct#re
• initialized wit te val#e ' and givente val#e > wen te verte& is visited(
8/17/2019 cad for vlsi 1.pptx
41/284
8/17/2019 cad for vlsi 1.pptx
42/284
eac verte& is visited e&actly once/ all edges are also visited e&actlyonce(
Ass#ming tat te generic verte& and edge actions ave a constanttime comple&ity/ tis leads to a time comple&ity of
dept03rst searc co#ld be #sed to 3nd all vertices connected to aspeci3c verte& #
8/17/2019 cad for vlsi 1.pptx
43/284
8/17/2019 cad for vlsi 1.pptx
44/284
Stat#s of 9#e#e
8/17/2019 cad for vlsi 1.pptx
45/284
dept03rst searc co#ld be #sed to 3nd all vertices connected to aspeci3c verte& #
vertices are visited in te order of teir sortest pat from vs
Te sortest0pat problem becomes more comple&/ if te lengt ofte pat between two vertices is not simply te n#mber of edges inte pat( +weigted graps,
8/17/2019 cad for vlsi 1.pptx
46/284
• Di@-stra:s Sortest0patAlgoritm
• a weigted directedgrap 2+!/ ., is given
• edge weigts w+e,/ w+e, >
• !isited vertices of te set! are transferred one byone to a set T
• Ordering of vertices isdone #sing verte&attrib#te distanceB(
• te distance attrib#te of averte& v is e9#al to teedge weigt w++vs/ v,,
8/17/2019 cad for vlsi 1.pptx
47/284
vt G !5 is reaced after 7 iterations
contin#ing for one iteration more comp#tes te lengts of tesortest pats for all vertices in te grap Time comple&ity of wile loop G O+n, time/ were n G N!Noverall time comple&ity G O+n,as all edges are visited e&actly once/ viz( after te verte& from wictey are incident is added to set T( Tis gives a contrib#tion of >+.,
to te overall time comple&ity(worst0case time comple&ity G O+n . ,
8/17/2019 cad for vlsi 1.pptx
48/284
Prims lgorithm for Minimum Spanning "reesIn te matematical 3eld of grap teory/ a spanning tree T of an#ndirected grap 2 is a s#bgrap tat incl#des all of te vertices of 2tat is a tree(
One gets a spanning tree by removing edges from . #ntil all cycles inte grap avedisappeared wile all vertices remain connected(a grap as several spanning trees/ all of wic ave te same n#mberof edges +n#mber of vertices min#s one,In te case of edge0weigted #ndirected graps/ spanning tree is to befo#nd wit te least total edge weigt/ also called te tree lengt(+minim#m spanning tree problem,
8/17/2019 cad for vlsi 1.pptx
49/284
starts wit an arbitrary verte& wic is considered te initial tree
8/17/2019 cad for vlsi 1.pptx
50/284
8/17/2019 cad for vlsi 1.pptx
51/284
"ractable Intractable problems:
A problem tat can be solved in polynomial time is called tractable(A problem tat can not be solved in polynomial time is/ calledintractable(
8/17/2019 cad for vlsi 1.pptx
52/284
Combinatorial 8ptimization ProblemsProblem $ problem refers to a general class/ e(g( te ?sortest0patproblemJInstance$ Te term instance refers to a speci3c case of a problem/
e(g( ?te sortest0pat problem between verte& vs and verte& vt(
Instances of optimization problems can be caracterized by a 3nite setof variables(
If te variables range over real n#mbers/ te problem is called a
contin#o#s optimization problem(If te variables are discrete/ i(e( tey only can ass#me a 3nite n#mberof distinct val#es/ te problem is called a combinatorial optimizationproblem(
An e&le of a simple combinatorial optimization problem is te
satis3ability
problem$ to assign
8/17/2019 cad for vlsi 1.pptx
53/284
Anoter e&le$Di@-stra:s algoritm$wit given so#rce and target vertices vt vs/ de3nes an instance of teproblem
One co#ld associate
8/17/2019 cad for vlsi 1.pptx
54/284
• "he tra#eling salesman problem &"SP':
• 2iven a list of cities and te distances between eac pair of cities/wat is te sortest possible ro#te tat visits eac city e&actly once
and ret#rns to te origin cityR• TSP can be modelled as an #ndirected weigted grap/ s#c tat
cities are te grap:s vertices(• pats are te grap:s edges/ and a pat:s distance is te edge:s
lengt(• It is a minimization problem starting and 3nising at a speci3ed
verte& after aving visited eac oter verte& e&actly once(• Often/ te model is a complete grap
8/17/2019 cad for vlsi 1.pptx
55/284
any perm#tation of te cities de3nes a feasible sol#tion and tecost of te feasible sol#tion is te lengt of te cycle represented
by te sol#tion
cities c'/ c/ ( (( CIf te coordinates of a city ci are given by +&i / yi,/ te distance
between two cities ci and c@ is simply given by
nonoptimal sol#tion optimal sol#tion
8/17/2019 cad for vlsi 1.pptx
56/284
Decision Problems +part of optimization problem,$te optimization #ersion of te sortest0pat problem in grapsre9#ires tat te edges forming te sortest pat are identi3ed/wereas
te e#aluation #ersion merely as-s for te lengt of te sortestpat(decision problems$decision #ersion $ Tese are problems tat only ave two possibleanswers$ ?yes? or ?no(
If optimization version can be solved in polynomial time/ ten tedecision version can also be solved in polynomial time(
In oter words$ if tere is an algoritm tat is able to decide inpolynomial time weter tere is a sol#tion wit cost less tan or e9#al
to -/ it is not always obvio#s ow to get te sol#tion itself in polynomialtime(
Terefore/ te comp#tational comple&ity of te decision version of aproblem gives a lower bo#nd for te comp#tational comple&ity of teoptimization version(
8/17/2019 cad for vlsi 1.pptx
57/284
review Te decision #ersion of a combinatorial problem can be de3nedas te set of its instances +1/ c/ -,(
Uote tat eac instance is now caracterized by an e&tra parameter -V- is te parameter in te 9#estion ?Is tere a sol#tion wit cost lesstan or e9#al to -R:(
An interesting s#bset of instances is formed by tose instances for
wic te answer to te 9#estion is ?yes?(
Tis set is called
tas- associated wit a decision problem is sol#tion cec-ing(It is te problem of verifying weter c+f, W-(
Comple!ity Classes:
8/17/2019 cad for vlsi 1.pptx
58/284
Comple!ity Classes: it is #sef#l to gro#p problems wit te same degree in one comple&ityclass(
Te class of decision problems for wic an algoritm is -nown tatoperates in polynomial time is called P +wic is an abbreviation of?polynomial?,(
Deterministic and nondeterministic computer/
1or a common +deterministic, comp#ter it always is clear ow acomp#tation contin#es at a certain point in te comp#tation( Tis is alsore4ected in te programming lang#ages #sed for tem(
A nondeterministic comp#ter allows for te speci3cation of m#ltiple
comp#tations at a certain point in a program$ te comp#ter will ma-e anondeterministic coices on/ wic of tem to be performed(
Tis is not @#st a random coice/ b#t a coice tat will lead to te desiredanswer(
Te macine splits itself into as many copies as tere are coices/
eval#ates all coices in parallel/ and ten merges bac- to one macine(
Comple!ity class ;P$ Te comple&ity class UP +an abbreviation of
8/17/2019 cad for vlsi 1.pptx
59/284
Comple!ity class ;P$ Te comple&ity class UP +an abbreviation of?nondeterministic polynomial?, consists of tose problems tat can besolved in polynomial time on a nondeterministic comp#ter(
Any decision problem for wic sol#tion cec-ing can be done in
polynomial time is in UP(
class P is a s#bset of te class UP
Halting problem &undecidable class'$ problem is to 3nd an algoritmtat accepts a comp#ter program as its inp#t and as to decide weteror not tis program will stop after a 3nite comp#tation time(
;P l t
8/17/2019 cad for vlsi 1.pptx
60/284
;P(completeness :all decision problems contain in it are polynomially red#cible to eacoter(An instance of any UP0complete problem can be e&pressed as an
instance of any oterUP0complete problem #sing transformations tat ave a polynomial timecomple&ity(
3!: HMIL"8;I;C
8/17/2019 cad for vlsi 1.pptx
61/284
o de e s c co p# e g + a e a ca ode ,
a comp#ter wit a se9#entially accessible memory +a ?tape?, and a verysimple instr#ction set(
Te set only incl#des instr#ctions for writing a symbol +from a 3nite set,to te memory location pointed at by te memory pointer and move tepointer one position #p or down(
A 3nite n#mber of ?internal states? so#ld also be provided for a speci3c T#ring macine(
A ?program? ten consists of a set of conditional statements tat map acombination of a symbol at te c#rrent memory location and an internalstate to a new symbol to be written/ a new internal state and a pointermovement(
Te inp#t to te algoritm to be e&ec#ted on a T#ring macine is teinitial state of te memory(
Te macine stops wen it enters one of te special internal stateslabeled by ?yes? and ?no? +corresponding to te answers to a decision
problem,(
*eneral(purpose Methods for Combinatorial 8ptimization$
8/17/2019 cad for vlsi 1.pptx
62/284
*eneral(purpose Methods for Combinatorial 8ptimization$
algoritm designer as tree possibilities wen confronted wit anintractable problem(
'( try to solve te problem e&actly if te problem size is s#;cientlysmall #sing an algoritm tat as an e&ponential +or even a igerorder, time comple&ity in te worst case('( Te simplest way to loo- for an e&act sol#tion is e&a#stive
searc$ it simply visits all points in te searc space in someorder and retains te best sol#tion visited(
( Oter metods only visit part of te searc space/ albeit ten#mber of points visited may grow e&ponentially +or worse,wit te problem size(
( Appro&imation algoritms5( )e#ristics algoritms
"he =nit(size Placement Problem$Problem$ ow te cells so#ld be interconnected
8/17/2019 cad for vlsi 1.pptx
63/284
Problem$ ow te cells so#ld be interconnected(A net can be seen as a set of cells tat sare te same electrical signal
Te interconnections to be made are speci3ed by netsPlacement is to assign a location to eac cell s#c tat te total cip
area occ#pied is minimized(As te n#mber of cells is not modi3ed by placement/ minimizing tearea amo#nts to avoiding empty space and -eeping te wires tatwill realize te interconnections as sort as possible(
cells in te circ#it are s#pposed to ave a layo#t wit dimensions'&'+meas#red in some abstract lengt #nit,
it can be ass#med tat te only positions on wic a cell can be p#t onte cip are te grid points of a grid created by orizontal and verticallines wit #nit0lengt separation(
A nice property of #nit0size placement is tat te assignment of distinctcoordinate pairs to eac cell g#arantees tat te layo#ts of te cells willnot overlap(
Te possible way to eval#ate te 9#ality of a sol#tion for #nit0size
8/17/2019 cad for vlsi 1.pptx
64/284
Te possible way to eval#ate te 9#ality of a sol#tion for #nit sizeplacement is to ro#te all nets and meas#re die e&tra area necessaryfor wiring(
A bad placement will ave longer connections wic normally will lead to
more ro#ting trac-s between te cells and terefore to a larger cip area(
8/17/2019 cad for vlsi 1.pptx
65/284
Solving te ro#ting problem is an e&pensive way to eval#ate te9#ality of a placement(
Tis is especially te case if many tentative placements ave to be
eval#ated in an algoritm tat tries to 3nd a good one(
An alternative #sed in most placement algoritms is to only estimatete wiring area(
$ac%trac%ing and $ranch(and(bound:
8/17/2019 cad for vlsi 1.pptx
66/284
$ac%trac%ing and $ranch and bound:an instance I of a combinatorial optimization problem was de3ned by apair +1 / c,/ wit1 te ?set of feasible sol#tions? +also called te ?searc spaceJ or?sol#tion space?, andc a cost f#nction assigning a real n#mber to eac element in 1(
S#ppose tat eac feasible sol#tion can be caracterized by an n0dimensional vector f G Xf'/f ( ( ( fn, andeac 3+' W i W n, can ass#me a 3nite n#mber of val#es/ called te
e!plicit constraints (
te val#es assigned to te di%erent components of f may sometimes notbe cosen independently( In s#c a case one spea-s of implicitconstraints(
Consider a combinatorial optimization problem related to some grap2+!/ ., in wic a pat wit some properties is loo-ed for(One can ten associate a variable 3 wit eac edge/ wose val#e iseiter ' to indicate tat te corresponding edge is part of te pat or >to indicate te opposite(
Te e!plicit constraints ten state tat 3E>/ 'F for all i(
$ac%trac%ing$
8/17/2019 cad for vlsi 1.pptx
67/284
$ac%trac%ing$ Te principle of #sing bac-trac-ing for an e&a#stive searc of tesol#tion space is to
start wit an initial partial sol#tion in wic as many variables aspossible are left #nspeci3ed/ and
ten to systematically assign val#es to te #nspeci3ed variables#ntil eiter a single point in te searc space is identi3ed or an implicitconstraint ma-es it impossible to process more #nspeci3ed variables(
Te cost of te feasible sol#tion fo#nd can be comp#ted if all variables
are fo#nd(
Te algoritm contin#es by going bac% to a partial sol#tion generatedearlier and ten assigning a ne&t val#e to an #nspeci3ed variable+ence te name ?bac%trac%ing?,
It is ass#med tat all variables 3 ave type sol#tion0element
8/17/2019 cad for vlsi 1.pptx
68/284
It is ass#med tat all variables 3 ave type sol#tion element( Te partial sol#tions are generated in s#c a way tat te variables 3are speci3ed for' W i W - and are #nspeci3ed for i -(
Partial sol#tions aving tis str#ct#re will be denoted by fY+-,(fY+n,corresponds to a f#lly0speci3ed sol#tion +a member of te set offeasible sol#tions,(
Te global array val corresponds to te vector f+-,( Te val#e of f- isstored in valX- Z '[( So/ te val#es of array elements wit inde&
greater tan or e9#al to - are meaningless and so#ld not beinspected( Te proced#re cost+val, is s#pposed to comp#te te cost of a feasiblesol#tion #sing te cost f#nction c( It is only called wen - G n
8/17/2019 cad for vlsi 1.pptx
69/284
proced#re allowed+val/ -, ret#rns aset of val#es allowed by te e&plicitand implicit constraints for tevariable f-I given fY+\,
8/17/2019 cad for vlsi 1.pptx
70/284
8/17/2019 cad for vlsi 1.pptx
71/284
• Information abo#t a certain partial sol#tion f+-, ' W - Wn/ at a certainlevel can indicate tat any f#lly0speci3ed sol#tion f+n, D +f+-,, derivedfrom it can never be te optimal sol#tion(
• 1#nction tat estimates tis cost lower bo#nd will be denoted by (
• If inspection of can g#arantee tat all of te sol#tions belonging tof+-, ave a iger cost tan some sol#tion already fo#nd earlier
d#ring te bac-trac-ing/ none of te cildren of need any f#rterinvestigation(
• One says tat te node in te tree corresponding to can be -illed(
• -illing partial sol#tions is called branc0and0bo#nd
8/17/2019 cad for vlsi 1.pptx
72/284
8/17/2019 cad for vlsi 1.pptx
73/284
Proced#re "owerLbo#ndLcostis called to get a lower bo#nd of te partialsol#tion based on te f#nction
8/17/2019 cad for vlsi 1.pptx
74/284
Dynamic Programming$
8/17/2019 cad for vlsi 1.pptx
75/284
Dynamic programming is a tecni9#e tat systematically constr#cts teoptimal sol#tion of some problem instance by de3ning te optimalsol#tion in terms of optimal sol#tions of smaller size instances(
Dynamic programming can be applied to s#c a problem if tere is a r#leto constr#ct te optimal sol#tion for p G - +complete sol#tion, from teoptimal sol#tions of instances for wic p W - +set of partial sol#tions,(
Te fact tat an optimal sol#tion for a speci3c comple&ity can beconstr#cted from te optimal lower comple&ity problems only/ is essentialfor dynamic programming(
Tis idea is called the principle of optimality(
l i bl i 3 d f
8/17/2019 cad for vlsi 1.pptx
76/284
Te goal in te sortest0pat problem is to 3nd te sortest pat from aso#rce verte&vs to a destination verte& vt in a directed grap 2+!/ ., were tedistance between two vertices #/ v is given by te edge weigt w++#/ v,,(
If p G -/ te optimization goal becomes$ 3nd te sortest pat from vs toall oter vertices in te grap considering pats tat only pass tro#gte 3rst - closest vertices to vs(
Te optimal sol#tion for te instance wit p G ' is fo#nd in a trivial wayby assigning te edge weigt w++vs/ #,, to te distance attrib#te of allvertices #(
S#ppose tat te optimal sol#tion for p G - is -nown and tat te -closest vertices to vs ave been identi3ed and transferred from ! to T(
Ten/ solving te problem for p G -' is simple$ transfer te verte& #in ! aving te lowest val#e for its distance attrib#te from ! to T and#pdate te val#e of te distance attrib#tes for tose vertices remainingin !(
additional parameters may be necessary to disting#is m#ltiple instances
of te problem for te same val#e of p(
Integer Linear Programming:
8/17/2019 cad for vlsi 1.pptx
77/284
Integer Linear Programming:• Integer linear programming +I"P, is a speci3c way of casting a
combinatorial optimization problem in a matematical format(• Tis does not elp from te point of view of comp#tational comple&ity
as I"P is UP complete itself (• I"P form#lations for problems from te 3eld of !"SI design a#tomation
are often enco#ntered d#e to te e&istence of ?ILP sol#ersJ(• I"P solvers are software pac-ages tat accept any instance of I"P as
teir inp#t and generate an e!act solution for te instance(
• ,hy ILP is useful in CD for VLSI• Te inp#t sizes of te problems involved may be small eno#g for an
I"P solver to 3nd a sol#tion in reasonable time(• One ten as an easy way of obtaining e&act sol#tions/ compared to
techni)ues s#c as branc0and0bo#nd(
8/17/2019 cad for vlsi 1.pptx
78/284
8/17/2019 cad for vlsi 1.pptx
79/284
all variables are apparently restricted to be positive
Qi / tat may ass#me negative val#es/ can be replaced by tedi%erence Qi Z Q- of two new variables Qi and Q- tat are botrestricted to be positive(
standard form
b' is slac- variableIt is possible to solve "P problems by a polynomial0time algoritmcalled te ellipsoid algoritm
Integer "inear Programming$ I"P is a variant of "P in wic te variablesare restricted to be integers
8/17/2019 cad for vlsi 1.pptx
80/284
are restricted to be integers Te tecni9#es #sed for 3nding sol#tions of "P are in general not s#itablefor I"POter tecni9#es tat more e&plicitly deal wit te integer val#es of te
variables so#ld be #sed(If integer variables are restricted f#rter to ass#me eiter of te val#eszero or one( Tis variant of I"P is called zero(one integer linearprogramming/
zero(one ILP formulation for the "SP:
Consider a grap 2+!/ ., were te edge set . contains - edges$ . G Ee'/e/ ( ( ( / e-F(
Te I"P form#lation re9#ires a variable &i/ for eac edge ei Te variable &i can eiter ave te val#e '/ wic means tat tecorresponding edgeei as been selected as part of te sol#tion/
or te val#e > meaning tat ei/ is not part of te sol#tion(
Cost f#nctionG
In te optimal sol#tion/ only tose &i tat correspond to edges in te
8/17/2019 cad for vlsi 1.pptx
81/284
Sol#tion set wo#ld also incl#desol#tions tat consists of m#ltipledis@oint to#rsAdditional constraint$ A to#r tat
visits all vertices in te grap so#ldpass tro#g at least two of teedges tat connect a verte& in !'wit a verte& ! +were ! G ! ] !',
8/17/2019 cad for vlsi 1.pptx
82/284
size of te problem instance$te n#mber of variables is e9#al to te n#mber of edges
Te n#mber of constraints of te type presented is e9#al to te n#mberof vertices
Te n#mber of constraints of te type given in owever/ can grow
e&ponentially as te n#mber of s#bsets of ! e9#als y(
"ocal Searc$• "ocal searc is a general p#rpose optimization metod tat wor-s wit
8/17/2019 cad for vlsi 1.pptx
83/284
• "ocal searc is a general0p#rpose optimization metod tat wor-s witf#lly speci3ed sol#tions f of a problem instance +1/ c,
• It ma-es #se of te notion of a neigbo#rood U+f, of a feasiblesol#tion f(
• or-s wit s#bset of 1 tat is ?close? to f in some sense(• a neigbo#rood is a f#nction tat assigns a n#mber of feasible
sol#tions to eac feasible sol#tion$ U $ 1 1(• 1 denotes te power set of 1(• Any g U+f, is called a neigbo#r of f(
• Te principle of local searc is to s#bse9#ently visit a n#mber of
8/17/2019 cad for vlsi 1.pptx
84/284
• Te principle of local searc is to s#bse9#ently visit a n#mber offeasible sol#tions in te searc space(
• transition from one sol#tion to te ne&t in te neigbo#rood iscalled a move or a local transformation
• Multiple minima problem• If te f#nction as a single minim#m/ it will be fo#nd(• 1#nctions wit many minima/ most of wic are local• local searc as te property tat it can get st#c- in a local
minim#m(• te larger te neigbo#roods considered/ te larger is te part of
te searc space e&plored and te iger is te cance of 3nding asol#tion wit good 9#ality(
• One more possibility is to repeat te searc a n#mber of times witdi%erent initial sol#tions
• one so#ld be able to move to a sol#tion wit a iger cost/ bymeans of so0called uphill mo#es(
Sim#lated Annealing$• a material is 3rst eated #p to a temperat#re tat allows all its
8/17/2019 cad for vlsi 1.pptx
85/284
• a material is 3rst eated #p to a temperat#re tat allows all itsmolec#les to move freely aro#nd +te material becomes li9#id,/ andis ten cooled down very slowly(
• At te end of te process/ te total energy of te material is minimal(
• Te energy corresponds to te cost f#nction(• Te movement of te molec#les corresponds to a se9#ence of moves
in te set of feasible sol#tions(• Te temperat#re corresponds to a control parameter T wic
controls te acceptance probability for a move from
8/17/2019 cad for vlsi 1.pptx
86/284
Te f#nction random +-,generates a real0val#ed randomn#mber between > and - wit a
#niform distrib#tion
Te combination of tef#nctions termal e9#ilibri#m/new temperat#re and stoprealizes a strategy for
sim#lated annealing/ wic iscalled tecooling sced#le(
Sim#lated annealing allowsmany #pill moves at tebeginning of te searcand grad#ally decreases teirfre9#ency(
Tab# Searc
8/17/2019 cad for vlsi 1.pptx
87/284
2iven a neigbo#rood s#bset 2 U+f, of a feasible sol#tion f/ teprinciple of tab# searc is to move to te ceapest element g 2 evenwen c+g, c+f,(
Te tab# searc metod/ does not directly restrict #pill movestro#go#t te searc processIn order to avoid a circ#lar searc pattern/ a so0called tab# listcontaining te - last visited feasible sol#tions is maintained
Tis only elps/ of co#rse/ to avoid cycles of lengt W -
8/17/2019 cad for vlsi 1.pptx
88/284
Genetic Algorithms$instead of repetitively transforming a single c#rrent sol#tion into a ne&t
8/17/2019 cad for vlsi 1.pptx
89/284
instead of repetitively transforming a single c#rrent sol#tion into a ne&tone by teapplication of a move/te algoritm sim#ltaneo#sly -eeps trac- of a set P of feasible
sol#tions/ called te population(
In an iterative searc process/ te c#rrent pop#lation is replaced by tene&t one#sing a proced#reIn order to generate a feasible sol#tion two feasible sol#tions called teparents of te cild are 3rst selected from
is generated in s#c a way tat it inerits parts of its ?properties? fromoneparent and te oter part from te second parent by te application ofan operationcalled crossover (
1irst of all/ tis operation ass#mes tat all feasible sol#tions can beencoded by a 3&ed lengt vector f G Xf'/f (( ( fn[T G f as was te casefor te bac-trac-ing algoritm
$it strings are to represent feasible sol#tions(
U#mber of vector elements n is 3&ed/ b#t tat te n#mber of bits to
Consider an instance of te #nit0size placement problem wit '>> cellsand a '>& '> grid(
8/17/2019 cad for vlsi 1.pptx
90/284
As 6 bits are necessary to represent one coordinate val#e +eac val#e isan integer between 'and '>, and
>> coordinates +'>> coordinate pairs, specify a feasible sol#tion/ tecromosomes of tis problem instance ave a lengt of K>> bits(
A feasible sol#tion G the phenotype .ncoding of cromosome G the genotype
2iven two cromosomes/ a crossover operator will #se some of te bitsof te 3rstparents and some of te second parent to create a new bit stringrepresenting teCild(
A simple crossover operator wor-s as follows$
2enerate a random n#mber r between ' and te lengt I of te bit stringsfor teproblem instance(
Copy te bits 'tro#g r Z ' from te 3rst parent and te bits r tro#g
S#ppose tat te bit strings of te e&le represent te coordinates ofte placement
8/17/2019 cad for vlsi 1.pptx
91/284
te placementproblem on a '> & '> grid/ now wit only a single cell to place +anarti3cial problem,(
Te bit string for a feasible sol#tion is ten obtained by concatenatingte two 60bit val#es of te coordinates of te cell(
So/ f+-, is a placement on position +7/ , and g+-, one on position +K/ 8,( Te cildren generated by crossover represent placements atrespectively +7/ '6, and +K/ ',(
Clearly/ a placement at +7/ '6, is illegal$ it does not represent a feasiblesol#tion as coordinate val#es cannot e&ceed '>(
Te combination of te cromosome representation and te crossovert f ti f ibl l ti l d t
8/17/2019 cad for vlsi 1.pptx
92/284
operator for generating new feasible sol#tions/ may leads to morecomplications(
Consider e(g( te traveling salesman problem for wic eac of tefeasible sol#tions can be represented by a perm#tation of te cities(
Two e&le cromosomes for a si& city problem instance wit cities c'tro#g c8 co#ld ten loo- li-e?C'C5C8C7CC6J and ?C6CC'C7C5C8?(
In s#c a sit#ation/ te application of te crossover operator asdescribed for binary strings is very li-ely to prod#ce sol#tions tat arenot feasible(
illegal sol#tion ?C'C5C'C7C5C8 +or ?C6CC8C7CC6?,
Order crossover$ for cromosomes tat represent perm#tationsTis operator copies te elements of te 3rst parent cromosome #ntil
8/17/2019 cad for vlsi 1.pptx
93/284
Tis operator copies te elements of te 3rst parent cromosome #ntilte point of te c#t into te cild cromosome(
Te remaining part of te cild is composed of te elements missing inte perm#tation in te order in wic tey appear in te second parent
cromosome(
Consider again te cromosomes ?C'C5C8C7CC6J and?C6CC'C7C5C8? c#t after te second city(
Ten te application of order crossover wo#ld lead to te cild?C'C5C6CC7C8?
8/17/2019 cad for vlsi 1.pptx
94/284
Te f#nction select isresponsible for te selection offeasible sol#tions from tec#rrent pop#lation favo#ringtose tat ave a better cost
Te f#nction stop decideswen to terminate te searc/e(g( wen tere as been noimprovement on te bestsol#tion in te pop#lationd#ring te last m iterations/
were m is a parameter of te
8/17/2019 cad for vlsi 1.pptx
95/284
stronger preference given to parents wit a lower cost wen selectingpairs of parents to be s#bmitted to te crossover operator
Mutation: M#tation elps to avoid getting st#c- in a local minim#m
One can wor- wit more sopisticated crossover operators/ e(g(operators tatma-e m#ltiple c#ts in a cromosome(
One can copy some members of te pop#lation entirely to te newgenerationinstead of generating new cildren from tem(
Instead of disting#ising between te pop#lations p- and p+-', oneco#ld
directly add a new cild to te pop#lation and sim#ltaneo#sly removesome?wea-? member of te pop#lation(
Longest(path lgorithm for D*s
8/17/2019 cad for vlsi 1.pptx
96/284
• A variable pi is associated wit eac verte& vi to -eep co#nt of teedges incident to vi tat ave already been processed(
•
8/17/2019 cad for vlsi 1.pptx
97/284
8/17/2019 cad for vlsi 1.pptx
98/284
Layout Compaction$At te lowest level/ te level of te mas- patterns for te fabrication of
8/17/2019 cad for vlsi 1.pptx
99/284
At te lowest level/ te level of te mas- patterns for te fabrication ofte circ#it/ a 3nal optimization can be applied to remove red#ndantspace(
Tis optimization is called layo#t compaction
"ayo#t compaction can be applied in four situations/
'( Converting symbolic layo#t to geometric layo#t(
( =emoving red#ndant area from geometric layo#t(
5( Adapting geometric layo#t to a new tecnology(
6( Correcting small design r#le errors
A ne, technology means tat te design r#les ave cangedVas long as te new and old tecnologies are compatible +e(g( bot areCMOS tecnologies,/ tis adaptation can be done a#tomatically/ +e(g( bymeans of so0called mas%(to(symbolic e!traction(,
"he Layout design problem:
8/17/2019 cad for vlsi 1.pptx
100/284
A layo#t is considered to consist of rectangles(te rectangles can be classi3ed into t,o groups$
'( rigid rectangles and( stretcable rectangles(
'( -igid rectangles correspond to transistors and contact cutswose lengt and widt are 3&ed(
en tey are moved d#ring a compaction process/ teir lengts
and widts do not cange(
( Stretchable rectangles correspond to ,ires(In principle te widt of a wire cannot be modi3ed( Te lengt of a
wire/ can be canged by compaction(
Compaction tools:
8/17/2019 cad for vlsi 1.pptx
101/284
• "ayo#t is essentially two0dimensional and layo#t elements can inprinciple be moved bot orizontally and vertically for te p#rpose
of compaction(
• en one dimensional compaction tools are #sed/ te layo#telements are only moved along one direction +eiter vertically ororizontally,( Tis means tat te tool as to be applied at least twice$ once for
orizontal and once for vertical compaction(
• ",o dimensional compaction tools move layo#t elements inbot directions sim#ltaneo#sly(
• Teoretically/ only two0dimensional compaction can acieve an
optimal res#lt( Tis type of compaction is ;P(complete( On teoter and/ one dimensional compaction can be solvedoptimally in polynomial time
8/17/2019 cad for vlsi 1.pptx
102/284
In one0dimensional/ say orizontal/ compaction a rigid rectangle can berepresented by one &0coordinate +of its centre/ for e&le, and astretcable one by two +one for eac of te endpoints,
A minim#m0distance design r#le between two rectangle edges can nowbe e&pressed as an ine)uality
te minim#m widt for te layer concerned is a and te minim#mseparation is b
A grap following all tese ine9#alities is called constraint graph(
8/17/2019 cad for vlsi 1.pptx
103/284
Tere is a so#rce verte& no( locatedat & G >
Directed acyclic graph
8/17/2019 cad for vlsi 1.pptx
104/284
Directed acyclic graphA constraint grap derived from only minim#m0distance constraints asno cycles
Te lengt of te longest pat from te so#rce verte& v> to a speci3cverte& vi in a te constraint grap 2+!/ ., gives te minimal &0coordinate &i/ associated to tat verte&(
"he Longest Path in *raphs ,ith Cycles Two cases can be disting#ised$'( Te grap only contains negative cycles/ i(e( te s#m of te edge
weigts along any cycle is negative(( Te grap contains positive cycles$ Te problem for graps wit
positive cycles is UP0ardA constraint grap wit positive cycles corresponds to a layo#t wit
con7icting constraints S#c a layo#t is called o#er(constrained layout and is impossibleto realize
partitions te edge set . of te constraint grap 2+! ., into two sets .f
8/17/2019 cad for vlsi 1.pptx
105/284
partitions te edge set . of te constraint grap 2+!/ ., into two sets .fand .b
Te edges in .f ave been obtained from te minim#m0distanceine9#alities and are called 1orward edges( Te edges in .b correspond to ma&im#m0distance ine9#alities and arecalled bac-ward edges
at te -t iteration of te do loop/ teval#es of te &i represent te longest0
8/17/2019 cad for vlsi 1.pptx
106/284
pats goingtro#g all forward edges andpossibly - bac-ward edges(
As te DA2 longest0pat algoritm as a time comple&ity of >+N.f N, andis called
8/17/2019 cad for vlsi 1.pptx
107/284
is calledat most .b times/
So te "iao0ong algoritm as a time comple&ity of >+N.bN & N.f N,(
Tis ma-es te algoritm interesting in cases wen te n#mber ofbac-ward edgesis relatively small(
Te
8/17/2019 cad for vlsi 1.pptx
108/284
edges(
S' contains te c#rrent wave
front andS is te one for te ne&t iteration
n is te n#mber of vertices
after - iterations/ te algoritm
as comp#ted te longest0patval#es for pats going tro#g -Z ' intermediate vertices
Te time comple&ity of te
8/17/2019 cad for vlsi 1.pptx
109/284
Te time comple&ity of te
8/17/2019 cad for vlsi 1.pptx
110/284
e c 9#e co e p ob e +a so so e es ca ed pa o o c 9#es,is te problem of determining weter te vertices of a grap can bepartitioned into - cli9#es(
)ig0level syntesis is often divided into a n#mber of s#btas-s(
Considering tem as independent tas-s ma-es it easier to de3neoptimization problems and to design algoritms to solve tem(
Scheduling is te tas- of determining te instants at wic tee&ec#tion of teoperations in te D12 will start(
Assignment(also called binding) maps eac operation in te D12to a speci3c f#nctional #nit on wic te operation will be e&ec#ted(
Assignment is also concerned wit mapping storage val#es tospeci3c memory elements and of data transfers to interconnectedstr#ct#res(
Allocation (or "resource allocation“ or module selection) simplyreserves te ardware reso#rces tat will be necessary to realize te
algoritm(
Assignment(also called binding) problem is called tas-0to0agentassignment were
8/17/2019 cad for vlsi 1.pptx
111/284
assignment/ werea tas% can be an operation or a val#e and an agent can be an 1H or aregister(
Tas-s are called compatible if tey can be e&ec#ted on te same agent(
In case of val#es/ compatibility means wen teir life times do notoverlap(
Te set of tas-s can be #sed as te verte& set of a so0calledcompatibility grap 2C+!C/ .c,(
Te grap as edges +vi/!@, .cif and only if te tas-s vi and v@ arecompatible(
one can say tat two tas-s are in con4ict if tey cannot be e&ec#ted onte same agent(
Te set of tas-s is ten #sed as te verte& set of a con4ict grap tatas edges for tose verte& pairs tat are in con4ict(
Te con4ict grap is te complement grap of te compatibility grap(
Te goal of te assignment problem is to minimize te n#mber of agentsfor te given set of tas-s
8/17/2019 cad for vlsi 1.pptx
112/284
for te given set of tas-s(
Te vertices of any complete s#bgrap of a compatibility grap
correspond to a set of tas-s tat can be assigned to te same agent(
Te goal of te assignment problem is ten to partition te compatibilitygrap in s#c a way tat eac s#bset in te partition forms a completegrap and te n#mber of s#bsets in te partition is minimal(
Te s#bsets are pairwise dis@oint and te #nion of te s#bsets forms teoriginal set by de3nition of a partition(
In te literat#re s#c a partitioning is called a cli9#e partitioning
combining vertices in te compatibility grap res#lts a s#perverte&(
Te inde& I of a s#perverte& represents te set of indices of te verticesfrom wic te s#perverte& was formed(1or e&le/ combining vertices '/5 and _gives a s#perverte&!'/5/_(
A s#perverte&vnis a common neigbor of te s#pervertices!i/v@!-/ if botedges +viB vn, and +v@/ vn, are incl#ded in set .-(
8/17/2019 cad for vlsi 1.pptx
113/284
Placement and Partitioning
8/17/2019 cad for vlsi 1.pptx
114/284
Te inp#t to te placement problem is te structural description of acirc#it( it is te o#tp#t of ig0level syntesis(
S#c a description consists of a list of design s#bentities +ardwares#bparts wit teir layo#t designs, and teir interconnection patternstat togeter specify te complete circ#it(
Te goal of placement is to determine te location of tese layo#ts onte cip s#c tat te total res#lting cip area is minimal/ and s#;cientspace is left for wiring(
Te wiring so#ld realize e&actly te interconnections speci3ed in testr#ct#ral description +routing problem)
8/17/2019 cad for vlsi 1.pptx
115/284
Te partitioning problem deals wit splitting a networ- into two or morepartsby c#tting connections(
Partitioning problem is treated ere togeter wit placement beca#sesol#tion metods for te partitioning problem can be #sed as as#bro#tine for some type of placement algoritms(
!ata model of an electric circ#it$ te organization of te data str#ct#res
tat represent electric circ#it(
Te data model consists of te tree str#ct#res cell/ port and net(
A ll i t b i b ildi bl - f i it A UAUD t i l
8/17/2019 cad for vlsi 1.pptx
116/284
A cell is te basic b#ilding bloc- of a circ#it( A UAUD gate is an e&leof a cell(
Te point at wic a connection between a wire and a cell is establisedis called a port(
Te wire tat electrically connects two or more ports is a net(
A set of ports is associated wit eac net(
A port can only be part of a single net(
8/17/2019 cad for vlsi 1.pptx
117/284
te information stored in masters originates from a library
8/17/2019 cad for vlsi 1.pptx
118/284
n input cell has a single port tro#g wic it sends a signal to tecirc#it and an output cell has a single port tro#g wic it receivesa signal from te circ#it(
Ports are indicated bysmall s9#aresDased lines sow tecell bo#ndaries
Te grap will ave tree distinct sets of vertices$'( a cell set/
8/17/2019 cad for vlsi 1.pptx
119/284
( a port set and5( a net set(
Tere will be two edge sets$6( one for edges connecting cells wit ports and7( one for edges connecting nets wit ports
edges never connect vertices of te same type
8/17/2019 cad for vlsi 1.pptx
120/284
A hypergraph consists of verticesand yperedges/
yperedges connect two or morevertices
te vertices represent te cells and
te nets
by omitting te e&plicitrepresentationof nets$ cli)ue model Hsed for cli9#e partitioning
9ire(length 3stimation
total wire lengt is #sed to eval#ate te 9#ality of placement
8/17/2019 cad for vlsi 1.pptx
121/284
total wire lengt is #sed to eval#ate te 9#ality of placement
3stimation$
A wire0lengt metric is applied to eac net/ res#lting in a lengtestimate per net(
Te total wire lengt estimation is ten obtained by s#mming teindivid#al estimates(
Te total wiring area can ten be derived from tis lengt by ass#minga certain wire widt and a wire separation distance(
All metrics refer to a cell:s coordinates(common metrics are
Half perimeter$ Tis metric comp#tes te smallest rectangle tatencloses all terminals of a net and ta-es te s#m of te widt andeigt of te rectangle as an estimation of te wire lengt(
Te estimation is e&act for t,o( and three terminal nets and gives a
lower bo#nd for te wire lengt of nets wit fo#r or more terminals(
8/17/2019 cad for vlsi 1.pptx
122/284
Minim#m rectilinear spanning>Steiner tree$ Te minim#m Steiner tree always as a lengt sorter tan or e9#al tote spanning treeCan be #tilized to estimate total wire lengt re9#ired(
S)uared 3uclidean distance$ Tis metod is meant for te cli9#e0
model representation of an electric circ#it(As nets are not e&plicitly present in tis model/ te total cost isobtained by s#mming over te cells rater tan over te nets(
Te cost of a placement is ten de3ned as$ `i@ is zero if tere is no edge betweente vertices !i/ and !@
Types of Placement Problemstandard0cell placement $ standard cells are predesigned small circ#its+ i l l i t 4i 4 t ,
8/17/2019 cad for vlsi 1.pptx
123/284
+e(g( simple logic gates/ 4ip04ops/ etc(,
ules #or placement $'( Connections tat are sared by all or most cells/ li-e e(g( power andcloc- connections/ cross te cells from left to rigt at 3&ed locations(+called te logistic signals,
( Signals related to te speci3c IO of te cell ave to leave te celleiter at te top or te bottom(
5( cells are collected into rows separated by wiring or ro#ting cannels(tey are connected by horizontal abutment( +standard0cell layo#t,
8/17/2019 cad for vlsi 1.pptx
124/284
y y y
6( In f#ll0c#stom design were designers ave te freedom to givearbitrary sapes to teir cells / te cells need wiring space all aro#nd(+b#ilding0bloc- layo#t,
Apart from te standard0cell and b#ilding0bloc- layo#t styles/ a
combination of
Te placement problem for standard cells or b#ilding bloc-s is morecomple& tan te #nit0size placement problem(
8/17/2019 cad for vlsi 1.pptx
125/284
One obvio#s di%erence is tat moves tat e&cange two cells asenco#ntered in many general p#rpose algoritms are not always
possible d#e to te size di%erence
Placement lgorithms:Placement algoritms can be gro#ped into two categories$
8/17/2019 cad for vlsi 1.pptx
126/284
Constructi#e placement$ te algoritm is s#c tat once tecoordinates of a cell ave been 3&ed tey are not modi3ed anymoreV
Iterati#e placement$ all cells ave already some coordinates andcells are moved aro#nd/ teir positions are intercanged/ etc( in orderto get a new +opef#lly better, con3g#ration(
An initial placement is obtained in a constr#ctive way and attempts aremade to increase te 9#ality of te placement by iterativeimprovement(
Constructive Placement $
Partitioning methods wic divide te circ#it in two or more
8/17/2019 cad for vlsi 1.pptx
127/284
gs#bcirc#its of a given size wile minimizing te n#mber of connectionsbetween te s#bcirc#its$
'( min0c#t partitioning and( Cl#stering
./ min(cut partitioning
Te basic idea of min(cut placement is to split te circ#it into two
s#bcirc#its of more or less e9#al size wile minimizing te n#mber ofnets tat are connected to bot s#bcirc#its
Te two s#bcirc#its obtained will eac be placed in separate alves of telayo#t
Te n#mber of long wires crossing from one alf of te cip to te oterwill be minimized
bipartitioning is rec#rsively applied
8/17/2019 cad for vlsi 1.pptx
128/284
Te second tas- can be based on di%erent e#ristics(One s#c e#ristic is to loo- at te parts of te circ#it tat already avea 3&ed position +eiter beca#se te placement of tese parts is already3&ed or beca#se tey are connected to te inp#ts or o#tp#ts of te cip
tat are located at te cip:s peripery,
Min0c#t placement is a top0down metod
8/17/2019 cad for vlsi 1.pptx
129/284
Pert#rbation of a feasible sol#tion for standard cell or b#ilding0bloc-placement is more comple& d#e to te ine9#ality of te cell sizes(Di%erent approaces are possible$
8/17/2019 cad for vlsi 1.pptx
130/284
Di%erent approaces are possible$
'( One can allow tat cells in a feasible sol#tion overlap and ma-e te
overlap part of te cost f#nction to be minimized(
Tis will direct a placement algoritm towards sol#tions $ith little or nooverlap(
Any overlap tat remains can be eliminated by pulling apart te cells inte 3nal layo#t +at te e&pense of a larger overall cip area,(
( One can eliminate overlaps directly after eac move by sifting anappropriate part of te cells in te layo#t(
In general/ tis is a comp#tation0intensive operation as te coordinates ofmany cells in te layo#t ave to be recomp#ted as well
1orce0directed placement$
It ass#mes tat cells tat sare nets/ feel an attractive ?force? from eac
8/17/2019 cad for vlsi 1.pptx
131/284
It ass#mes tat cells tat sare nets/ feel an attractive force from eacoter(
Te goal is to red#ce te total force in te networ-(
one can comp#te te ?center of gravity? of a cell/ te position were tecell feels a force zero
center of gravity +&ig / yig, of a cell i is de3ned as
pert#rbation is ten tomove a cell to a legal position close to its center of gravity andif tere is anoter cell at tat position to move tat cell to some emptylocation or to its own center of gravity
Partitioning
en a large circ#it as to be implemented wit m#ltiple cips and ten#mber of pins on te IC pac-ages necessary for intercip
8/17/2019 cad for vlsi 1.pptx
132/284
n#mber of pins on te IC pac-ages necessary for intercipcomm#nication so#ld be minimized(
\ernigan0"in Partitioning Algoritm Tere is an edge0weigted #ndirected grap 2+!/ .,
Te grap as n vertices +N!N G n,V an edge +a/ b, .as a weigt if +a/b, ./ >(
Te problem is to 3nd two sets A and /and NAN G N and wic/ in general/ will not ave aminimal c#t cost
8/17/2019 cad for vlsi 1.pptx
133/284
minimal c#t cost(
In an iterative process/ s#bsets of bot sets are isolated and
intercanged(
In iteration n#mber m/ te set isolated from Am0' will be denoted byQm and te set isolated from
8/17/2019 cad for vlsi 1.pptx
134/284
Te e&ternal cost .a of a Am0' is de3ned as follows
te e&ternal cost for verte& a Am0' is a meas#re for te p#ll tat teverte& e&periences from te vertices in
8/17/2019 cad for vlsi 1.pptx
135/284
Te di%erence between internal and e&ternal costs gives an indicationabo#t tedesirability to move te verte&$
a positive val#e sows tat te verte& so#ld be better moved to teopposite set/ a negative val#e sows a preference to -eep te verte& inits c#rrent set(
Te di%erences for te vertices in bot sets are given by te variablesDa and Db
te gain in te c#t cost/ A/ res#lting from te intercange of two vertices
can
It is important to realize tat te best c#t cost improvement leading tote selectionof a pair +ai bi, may be negative
8/17/2019 cad for vlsi 1.pptx
136/284
of a pair +ai /bi, may be negative(
Once all vertices ave been loc-ed/ te pairs are investigated in teorder of selection$ te act#al s#bsets to be intercanged correspond tote se9#ence of pairs +starting wit iG', giving te best improvement(
Pairs in te se9#ence may ave negative cost improvements as long aste pairs following
tem compensate for it(
S#c a sit#ation wo#ld occ#r wen te e&cange of two cl#sters oftigtly connected vertices res#lts in an improvement/ wile tee&cange of individ#al vertices from eac cl#ster does not improve tec#t cost(
\" algoritm
8/17/2019 cad for vlsi 1.pptx
137/284
8/17/2019 cad for vlsi 1.pptx
138/284
%loorplanning$4oorplan0based design metodology$ Tis top0down designmetodology advocates tat layout aspects should be taken into
8/17/2019 cad for vlsi 1.pptx
139/284
metodology advocates tat layout aspects should be taken intoaccount in all design stages(
At iger levels of abstraction/ d#e to te lac- of detailed information/only te relative positions of the subblocks in te str#ct#ral descriptioncan be 3&ed(
Ta-ing layo#t into acco#nt in all design stages also gives earlyfeedbac-$ str#ct#ral syntesis decisions can immediately be eval#atedfor teir layo#t conse9#ences and corrected if necessary(
Te presence of +appro&imate, layo#t information allows for anestimation of wire lengts( 1rom tese lengts/ one can derive performance properties of te design s#c as timing and power
cons#mption(
8/17/2019 cad for vlsi 1.pptx
140/284
tree registers/ two m#ltiple&ers anda controller and an A"H
At te moment tat tis type of str#ct#ral information is not f#llyavailable/
one can estimate te area to be occ#pied by te vario#s s#bbloc-s
8/17/2019 cad for vlsi 1.pptx
141/284
one can estimate te area to be occ#pied by te vario#s s#bbloc-sand/ togeter wit a precise or estimated interconnection pattern/
try to allocate distinct regions of te integrated circ#it to te speci3c
s#bbloc-s
Terminology and 1loorplan =epresentation$
4oorplan can be represented hierarchically$ cells are b#ilt from oter
8/17/2019 cad for vlsi 1.pptx
142/284
p p ycells/ e&cept for tose cells tat are at te lowest level of te ierarcy
Tese lowest0level cells are called leaf cells
Cells tat are made from leaf cells are called composite cells
Composite cells can contain oter composite cells as well/ Te directs#bcells of a composite cell are called its children
every cell/ e&cept for te one representing te complete circ#it/ as aparent cell
bot leaf cells and composite cells are ass#med to ave a rectang#larsape(
If te cildren of all composite cells can be obtained by bisecting te cellorizontally or vertically/ te 4oorplan is called a slicing4oorplan(
So/ in a slicing 4oorplan a composite cell is made by combining itscildren orizontally or vertically
8/17/2019 cad for vlsi 1.pptx
143/284
A nat#ral way to represent a slicing 4oorplan is by means of a slicingtree(
Te leaves of tis tree correspond to te leaf cells(Oter nodes correspond wit orizontal and vertical composition of tecildren nodes(
8/17/2019 cad for vlsi 1.pptx
144/284
A representation mecanism tat can deal wit any 4oorplan is tepolar grap wic act#ally consists of two directed graps$te orizontal polar grap and
8/17/2019 cad for vlsi 1.pptx
145/284
p g pte vertical one(
Tese graps can be constr#cted by identifying te longest possibleline segments tat separate te cells in te 4oorplans(
Te orizontal segments are #sed as vertices in te orizontal polargrap and tevertical segments as te vertices in te vertical polar grap
.ac cell is represented by an edge in te polar grap
In te orizontal one/ tere will be an edge directed from te linesegment tat is te cell:s top bo#ndary to te line segment tat is itsbottom bo#ndary
In te vertical one/ a similar idea is #sed were te edge direction isfrom te left bo#ndary to te rigt one
8/17/2019 cad for vlsi 1.pptx
146/284
but : en two cells tat need to be electrically connected ave teirterminals in te rigt order and separated correctly/ te cells can simplybe p#t against eac oter wito#t te necessity for a ro#ting cannel in
8/17/2019 cad for vlsi 1.pptx
147/284
between tem( S#c cells are said to but/
Ideally/ all composite cells are created by ab#tment and no ro#tingcannels are #sed in a 4oorplan$ Tis re9#ires te e&istence of 7e!iblecells
4e&ible cells so#ld be able to accommodate feedtro#g wires(
4oorplan0based design does not e&cl#de te e!istence of routingchannels( Te cannels can be ta-en care of by incorporating tem inte area estimations for te cells(
Optimization Problems in 1loorplanning$
./ Mapping of a structural description to a 7oorplan +e(g( a slicingt ,
8/17/2019 cad for vlsi 1.pptx
148/284
tree,(In a tr#e top0down design metodology/ 4oorplanning will probably be
performed man#ally or interactively as te n#mber of cildren cells inwic a parent cell is s#bdivided is relatively small andgood decisions can be made based on designer e&perience(
tecni9#es -nown from placement li-e min0c#t partitioning can also be#sed in 4oorplanning
problem related to global ro#ting is called abstract routing(
1/ 2loorplan sizing$ Te availability of 4e&ible cells implies tepossibility of avingdi%erent sapes(
It is terefore possible to coose a s#itable sape for eac leaf cell s#ctat te res#lting 4oorplan is optimal in some sense(
4/ *eneration of 7e!ible cells: Tis tas- ta-es as inp#t a cell sape/ data on desired positions ofterminals and a netlist of te circ#it to be syntesized at some
8/17/2019 cad for vlsi 1.pptx
149/284
abstraction level/ and #ses a cell compiler to generate te layo#t tatcomplies wit te inp#t(
Te problem is especially comple& wen te layo#t as to be composedof individ#al transistors beca#se of te many degrees of freedom and te#ge searc space tat is associated wit it(
As tis style of design amo#nts to f#ll0c#stom design/ 9#ite some e&trae%ort as to be spent in te caracterization of te generated cells(
Characterization is te process of determining all -ind of electricalproperties of a cell/ s#c as parasitic capacitances and propagation delay/
Caracterization is necessary for an acc#rate simulation of te circ#itcontaining te generated cell(
1le&ibility in a cell:s sape can be acieved #sing primitives belonging toa level iger tan te transistor level(An e&le is a register 3le of 86 registers tat can be laid o#t in many
di%erent ways/ s#c as K & K/ '8 & 6/ 6 & '8 or ' & 86(
Shape 2unctions and 2loorplan Sizing$
en te cell is 4e&ible/ one co#ld say tat te realization needs an areaA
8/17/2019 cad for vlsi 1.pptx
150/284
A(
icever sape te cell will ave/ its eigt and its widt w ave toobey te constraint w A(
Te minimal eigt given as a f#nction of te widt is called te sape1#nction of te cell(
D#e to design r#les neiter te eigt nor te widt will asymptoticallyapproac zero(
Inset or rigid cell$ An inset cell/ a predesigned cell residing in a library/as te possibility of rotations +only in m#ltiples of >, and mirroringsas te only 4e&ibility to be 3t in a 4oorplan(
8/17/2019 cad for vlsi 1.pptx
151/284
Te sape f#nction of a composite cell in a slicing 4oorplan can be
comp#ted fromte sape f#nction of its cildren cells
If te sape f#nction of c' is indicated by '+w, and te one of C by+w,/ ten te sape f#nction 5+w, of te composite cell c5 can bee&pressed as$
a small e&le were bot c' and c are inset cells wit respectivesizes of 6 & and 7&5( Clearly/ tere are fo#r ways to stac- te two cellsvertically
8/17/2019 cad for vlsi 1.pptx
152/284
y
In te case of orizontal composition/ te sape f#nction of a compositecell as to be comp#ted #sing a deto#r via te inverses of te cildren:ssape f#nctions
8/17/2019 cad for vlsi 1.pptx
153/284
Te inverse of te composite cell:s sape f#nction is te s#m of te
inverses of itscildren cell:s sape f#nctions
cildren sapes can be easily derived from te cosen parent sape forbot types of composition
sizing algorithm for slicing 4oorplans
'( Constr#ct te sape f#nction of te top0level composite cell in abottom0#p fasion starting wit te lowest level and combining sapef#nctions wile moving #pwards(
( Coose te optimal sape of te top0level cell(
5( Propagate te conse9#ences of te coice for te optimal sape downte slicing tree #ntil te sapes of all leaf cells are 3&ed(
-outing Te speci3cation of a ro#ting problem will consist of te'( position of te terminals/ te netlist tat indicates wic terminals so#ld be interconnected
8/17/2019 cad for vlsi 1.pptx
154/284
( te netlist tat indicates wic terminals so#ld be interconnectedand
5( te area available for ro#ting in eac layer(
=o#ting is normally performed in two stages(6( Te 3rst stage/ global or loose routing$ determines tro#g wic
wiring cannels a connection will r#n(
7( Te second stage local or detailed routing$ 3&es te precise patstat a wire will
ta-e +its position inside a cannel and its layer,(
Types of "ocal =o#ting Problems are de3ned #sing followingparameters$'( Te n#mber of wiring layersTe n#mber of layers available depends on te tecnology and te
8/17/2019 cad for vlsi 1.pptx
155/284
Te n#mber of layers available depends on te tecnology and tedesign style
contact cut tat realizes a connection between two layers is oftencalled a #ia in te conte&t of ro#ting(
( Te orientation of wire segments in a given layer$=eserved0layer models of ro#ting #se eiter orizontal or verticalsegments in one layer
Sometimes it is also allowed to #se segments wit an orientation tat isa m#ltiple of 67
5( *ridded or gridless routing/ In gridded ro#ting/ all wire segmentsr#n along lines of an ortogonal grid wit #niform spacing between telines(
In gridless ro#ting/ wires of di%erent widts as well as contacts aree&plicitly represented(
6( Te presence or absence of obstacles( Sometimes te completero#ting area isavailable for ro#ting/ sometimes part of te area in one or more layers
is bloc-ed
8/ "erminals ,ith a +!ed or 7oating position( In some problems teposition of teterminals is 3&ed/ b#t in oter problems te ro#ter can move te terminalinside a
8/17/2019 cad for vlsi 1.pptx
156/284
inside arestricted area(
_( Permutability of terminals( Sometimes te ro#ter is allowed tointercange terminals beca#se tey are f#nctionally e9#ivalent(
K( 3lectrically e)ui#alent terminals$ In some sit#ations/ a gro#p ofterminals belonging to te same net may already be connected to eac
oter/ ro#ter so#ld connect te rest of te net to only one of teterminals in tis gro#p/ wicever is te most s#itable(
rea -outing +single wiring layer/ a grid/ te presence of obstacles/ and3&ed terminals in all te ro#ting area,(
=o#ting problems in wic terminals are allowed anywere in te area
8/17/2019 cad for vlsi 1.pptx
157/284
g p yavailable for ro#ting are normally classi3ed as area ro#ting problems
path connection? or ?maze routing? algorithm Te basic algoritm is meant to realize a connection between two points+?so#rce? terminal/ te ?target? terminal, in a plane/ in an environmenttat may contain obstacles(
If a pat e&ists/ te algoritm always 3nds te sortest connection/going aro#nd obstacles(
Obstacles are grid points tro#g wic no wire segments can pass(
Te distance between two orizontally or vertically neigboring grid
points corresponds to te sortest possible wire segment( Te algoritm consists oftree steps$wave propagation/bac-tracing/ andclean#p
8/17/2019 cad for vlsi 1.pptx
158/284
8/17/2019 cad for vlsi 1.pptx
159/284
in tis bac-tracing step/ sometimes te neighbor ,ith label i is notuni)ue$ a e#ristic so#ld be #sed to ma-e a coice(
anoter e#ristic can be #sed not to cange te orientation of te
8/17/2019 cad for vlsi 1.pptx
160/284
anoter e#ristic can be #sed not to cange te orientation of tepat #nnecessarily/
Once a pat as been fo#nd/ it will act as an obstacle for te ne&tconnections to be made
Te worst0case time comple!ity of "ee:s algoritm operating on an n& n grid is >+n,( Its space comple&ity is also >En,(
In te case tat tere are multiple layers/ te algoritm operates ona tree0dimensional grid/ were te size of te tird dimension e9#alste n#mber of layers available
en a net as three or more terminals 3rst a pat between twoterminals so#ldbe fo#nd and ten a generalization of te algoritm as to be #sedwere a pat caneiter act as a so#rce or a target for te wave propagation(
nets ave to be ro#ted se)uentially is te wea- point of "ee:salgoritm
=o#ting te nets in a di%erent order strongly in4#ences te 3nal res#lt
8/17/2019 cad for vlsi 1.pptx
161/284
=o#ting te nets in a di%erent order strongly in4#ences te 3nal res#lt
8/17/2019 cad for vlsi 1.pptx
162/284
te grid distance is e9#al to te orizontal separation between teterminals(
Te nets ave 3&ed terminals at te top and bottom of te cannel and4oating terminals at te ?openJ sides/ at te left and rigt(
8/17/2019 cad for vlsi 1.pptx
163/284
A 7oating terminal is -nown to enter te cannel on te left or on terigt side/ b#t it is #p to te ro#ter to determine te e&act positionnets 'and 5 ave 4oating terminals at te left side and te nets 6 and 7 atte rigt
Te main goal of cannel ro#ting is te minimization of te eigt/ wile
a secondary goal is te minimization of te total wire lengt and ten#mber of via(
In oter words$ Te ob@ective is to minimize te area of te cannel:srectang#lar bo#nding bo&00or e9#ivalently/ to minimize te n#mber ofdi%erent orizontal trac-s needed(
s,itchbo! routingA ro#ting problem tat as some similarity wit cannel ro#ting isswitcbo& ro#ting
8/17/2019 cad for vlsi 1.pptx
164/284
3&ed terminals can be fo#nd on all fo#r sides of te rectang#lar ro#tingarea(
te minimization of te area is not an optimization goal(
Switcbo& ro#ting is a decision problem(
te goal is to 3nd o#t weter a sol#tion e&ists( en a sol#tion can befo#nd/ asecondary goal is to minimize te total wire lengt and te n#mber ofvias
8/17/2019 cad for vlsi 1.pptx
165/284
*ridless routing model
=o#ters ave been designed for wor-ing wito#t a grid(
8/17/2019 cad for vlsi 1.pptx
166/284
allows tat eac wire as a speci3c widt(
reser#ed(layer model: eac layer as only wires in one direction(or-s for small searc space(nonreser#ed layer model wor-s for a larger sol#tion space
"he Vertical Constraint *raphConsider a pair of terminals located in te same col#mn and entering tecannel inte same layer
8/17/2019 cad for vlsi 1.pptx
167/284
yIt is obvio#s tat in any sol#tion of te problem/
te endpoint of te segment coming from te top as to 3nis at aposition iger or lowertan te endpoint of te bottom segment +oterwise/ tere wo#ld be asortcirc#it,
Tis restriction is called a vertical constraint(
.ac col#mn aving two terminals in te same layer gives rise to avertical constraint( Te constraints are often represented in a vertical
In tis directed grap/ te vertices represent te endpoints of teterminal segments and te directed edges represent te relation?should be located abo#e
8/17/2019 cad for vlsi 1.pptx
168/284
it consists of pairs of vertices/ one pair for eac col#mn tat as two
terminals in te same layer/ eac pair connected by a single directededge from one verte& to te oter/ and #nconnected vertices for teoter col#mnsCycles are not allowed(
f#lly merged !C2f#lly separated !C2
Te main problem wit te f#lly merged form is te possible e&istence ofcycles/ in wic case te corresponding layo#t cannot be realized$ asegment cannot be at te same time above and below anoter one(
8/17/2019 cad for vlsi 1.pptx
169/284
In te absence of cycles in te !C2/ a sol#tion wit a single orizontal
segment per net wo#ld amo#nt to 3nding te longest pat in te grap(
Horizontal Constraints and the Left(edge lgorithm
If/ in te classical model for cannel ro#ting/ orizontal segmentsbelonging to di%erent nets are p#t on te same row +implying tat tey
8/17/2019 cad for vlsi 1.pptx
170/284
will be in te same layer too,/ te segments so#ld not overlap
+oterwise tere wo#ld be a sortcirc#it,(
Tis restriction is called a orizontal constraint(
A net I in a cannel ro#ting problem wito#t vertical constraints can becaracterized by an interval XQimin/ Qima&[/ corresponding to te left0
most and rigt0most terminal positions of te net(
Te goal of cannel ro#ting is ten red#ced to assign a row position inte cannel to eac interval
An optimal sol#tion combines tose nonoverlapping intervals on te
same row tatwill lead to a minimal n#mber of rows
Te n#mber of intervals tat contain a speci3c &0coordinate is calledte localdensity at col#mn position & and will be denoted by d+&,
8/17/2019 cad for vlsi 1.pptx
171/284
Te ma&im#m local density in te range of all col#mn positions is called
te cannel:s density and is denoted by dma&
Obvio#sly/ te density is a lower bo#nd on te n#mber of necessaryrows$ all intervalstat contain te same &0coordinate m#st be p#t on distinct rows
Te left0edge algoritm always 3nds a sol#tion wit a n#mber of rowse9#al to telower bo#nd(
Str#ct#res for te representation of intervals and lin-ed lists of intervals/
called intervaland list of interval respectively
standard ?list processing? function calls$3rst+l, gives te 3rst element of a list lVrest+l, gives te list tat remains wen te 3rst element is removed
list iLlist tat contains te intervals in order of increasing left coordinate(
8/17/2019 cad for vlsi 1.pptx
172/284
Te time comple&ity of te algoritm can easily be e&pressed in terms ofte n#mber of intervals n andte density of te problem d +te n#mber of rows in te sol#tion,(
8/17/2019 cad for vlsi 1.pptx
173/284
Sorting te set of intervals by teir left coordinate can be done in >+nlogn,(
Te o#ter loop will be e&ec#ted d times and at most n intervals from tesorted list will be inspected in te inner loop(
Tis leads to a total worst0case time comple&am
Top Related