8/20/2019 Basic Block Diagram
1/3
Basic Block Diagram
The basic Block Diagram of 8051 Architecture is shown below. The 8-Bit ALU block is linke with the register A! B!
"#$s! $egister Bank an the %&' (orts )ia 8-Bit Data Bus. The 1*-Bit Aress Bus is use to link the +,! D+T$!
$' an two %&' (ort/igher Aress Bte Lower Aress Bte.
The aresses of the "#$s of the8051 Architecture.
Register Function Address
A Accumulator 0x0E0
B Arithmetic 0x0F0
DPH Addressing External Memory 0x83
DPL Addressing External Memory 0x8
!E !nterru"t Ena#le $ontrol 0x0A8
!P !nterru"t Priority 0x0B8
P0 Port%0 0x80
P& Port%& 0x'0
P Port% 0xA0
P3 Port%3 0xB0
P$() Po*er $ontrol 0x8+
P,- Program ,tatus -ord 0x0D0
,$() ,erial Port $ontrol 0x'8
http://embeddedsystemdesignhub.blogspot.com/2010/08/basic-block-diagram.htmlhttp://embeddedsystemdesignhub.blogspot.com/2010/08/basic-block-diagram.html
8/20/2019 Basic Block Diagram
2/3
,B.F ,erial Port Data Bu//er 0x''
,P ,tac Pointer 0x8&
1M(D 1imer2$ounter Mode $ontrol 0x8'
1$() 1imer2$ounter 0x88
1L0 1imer%0 Lo* Byte 0x8A
1H0 1imer%0 High Byte 0x8$
1L& 1imer%& Lo* Byte 0x8B
1L0 1imer%0 High Byte 0x8D
The 2eneral +ur(ose $egisters are i)ie into four bank Bank-0! Bank-1! Bank-3! an Bank-4. ach bank
contains eight numbers of 8-bit registers. The aress starts from 0600 of first register of Bank-0 to 061# aress
of last register of Bank-4. The 1*-Bte of area of emor is utili7e for are bit aressing .The aress location
starts from the register with aress 0630.
Bank-4
R+ R R4 R5 R3 R R& R0
&F &E &D &$ &B3 &A &' &8
Bank-3
R+ R R4 R5 R3 R R& R0
&+ & &4 &5 &3 & && &0
Bank-1
R+ R R4 R5 R3 R R& R0
0F 0E 0D 0$ 0B 0A 0' 08
Bank-0
R+ R R4 R5 R3 R R& R0
0+ 0 04 05 03 0 0& 00
Bit Aressable $egister
Register Address 1o Bit Address From Bit Address
F +F +8
E ++ +0
D F 8
$ + 0
B 4F 48
A 4+ 40
' 5F 58
8 5+ 50
+ 3F 38
3+ 30
4 F 8
5 + 0
8/20/2019 Basic Block Diagram
3/3
3 &F &8
&+ &0
& 0F 08
0 0+ 00
Top Related