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William Stallings
Computer Organizationand Architecture8th Edition
Chapter 5Internal Memory
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Semiconductor Memory Types
Memory Type Category Erasure Write Mechanism Volatility
Random-access
memory (RAM) Read-write memory Electrically, byte-level Electrically VolatileRead-only
memory (ROM)Read-only memory
Not possible
Masks
NonvolatileProgrammable
ROM (PROM)
ElectricallyErasable PROM
(EPROM)Read-mostly memory
UV light, chip-levelElectrically ErasablePROM (EEPROM) Electrically, byte-levelFlash memory Electrically, block-level
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Semiconductor Memory
RAMMisnamed as all semiconductor memory is
random access
Read/WriteVolatileTemporary storageStatic or dynamic
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Memory Cell Operation
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Dynamic RAM
Bits stored as charge in capacitors Charges leak
Need refreshing even when powered Simpler construction Smaller per bit Less expensive Need refresh circuits Slower Main memory Essentially analogue
Level of charge determines value
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Dynamic RAM Structure
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DRAM Operation
Address line active when bit read or writtenTransistor switch closed (current flows)
WriteVoltage to bit line
High for 1 low for 0Then signal address line
Transfers charge to capacitor Read
Address line selected transistor turns on
Charge from capacitor fed via bit line to sense amplifier Compares with reference value to determine 0 or 1
Capacitor charge must be restored
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Static RAM
Bits stored as on/off switches No charges to leak No refreshing needed when powered More complex construction Larger per bit More expensive Does not need refresh circuits Faster Cache Digital
Uses flip-flops
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Stating RAM Structure
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Static RAM Operation
Transistor arrangement gives stable logicstate
State 1C1 high, C2 lowT1 T4 off, T2 T3 on
State 0C2 high, C1 lowT2 T3 off, T1 T4 on
Address line transistors T5 T6 is switch
Write apply value to B & compliment toB
Read value is on line B
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SRAM v DRAM
Both volatilePower needed to preserve data
Dynamic cellSimpler to build, smallerMore denseLess expensiveNeeds refreshLarger memory units
StaticFasterCache
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Read Only Memory (ROM)
Permanent storageNonvolatile
Microprogramming (see later) Library subroutines Systems programs (BIOS) Function tables
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Types of ROM
Written during manufactureVery expensive for small runs
Programmable (once)PROMNeeds special equipment to program
Read mostlyErasable Programmable (EPROM)
Erased by UVElectrically Erasable (EEPROM)
Takes much longer to write than readFlash memory
Erase whole memory electrically
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Organisation in detail
A 16Mbit chip can be organised as 1M of16 bit words
A bit per chip system has 16 lots of 1Mbitchip with bit 1 of each word in chip 1 andso on
A 16Mbit chip can be organised as a 2048x 2048 x 4bit array
Reduces number of address pinsMultiplex row address and column address11 pins to address (211=2048)Adding one more pin doubles range of values so x4
capacity
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Refreshing
Refresh circuit included on chip Disable chip Count through rows Read & Write back Takes time Slows down apparent performance
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Typical 16 Mb DRAM (4M x 4)
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Packaging
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256kByte Module
Organisation
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1MByte Module Organisation
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Interleaved Memory
Collection of DRAM chips Grouped into memory bank Banks independently service read or write
requests
K banks can service k requestssimultaneously
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Error Correction
Hard FailurePermanent defect
Soft ErrorRandom, non-destructiveNo permanent damage to memory
Detected using Hamming error correctingcode
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Error Correcting Code Function
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Advanced DRAM Organization
Basic DRAM same since first RAM chips Enhanced DRAM
Contains small SRAM as wellSRAM holds last line read (c.f. Cache!)
Cache DRAMLarger SRAM componentUse as cache or serial buffer
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Synchronous DRAM (SDRAM)
Access is synchronized with an external clock Address is presented to RAM RAM finds data (CPU waits in conventional DRAM) Since SDRAM moves data in time with system
clock, CPU knows when data will be ready
CPU does not have to wait, it can do somethingelse Burst mode allows SDRAM to set up stream of
data and fire it out in block
DDR-SDRAM sends data twice per clock cycle(leading & trailing edge)
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SDRAM
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SDRAM Read Timing
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RAMBUS
Adopted by Intel for Pentium & Itanium Main competitor to SDRAM Vertical package all pins on one side Data exchange over 28 wires < cm long Bus addresses up to 320 RDRAM chips at1.6Gbps Asynchronous block protocol
480ns access time
Then 1.6 Gbps
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RAMBUS Diagram
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DDR SDRAM
SDRAM can only send data once per clock Double-data-rate SDRAM can send data
twice per clock cycle
Rising edge and falling edge
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DDR SDRAMRead Timing
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Simplified DRAM Read Timing
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Cache DRAM
Mitsubishi Integrates small SRAM cache (16 kb) onto
generic DRAM chip
Used as true cache64-bit linesEffective for ordinary random access
To support serial access of block of dataE.g. refresh bit-mapped screen
CDRAM can prefetch data from DRAM into SRAMbuffer
Subsequent accesses solely to SRAM
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Reading
The RAM Guide RDRAM
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