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ASIC
DESIGNM.E.[EC] SEMESTER-I
Subject Code :- 710403
(GTU)
Prepared by:Mr. Amish J. Tankariya
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INTRODUCTION:
AnASIC (a-sick) is an application-specificintegrated circuit
History of integration:
Small-scale integration (SSI, ~10 gates per chip, 60s) Medium-scale integration (MSI, ~1001000 gates per chip,
70s)
Large-scale integration (LSI, ~100010,000 gates per chip,80s)
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Very large-scale integration (VLSI, ~10,000100,000 gatesper chip, 90s)
Ultra-large scale integration (ULSI, ~1M10M gates perchip)
History of technology:
Bipolar technology and transistortransistor logic (TTL)preceded ...
Metal-oxide-silicon (MOS) (nmos or NMOS)
The introduction of complementary MOS (CMOS) greatlyreduced power 2
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CONTINUE....
Generally, Size of IC is measured by no of logic gates (Transistors). Aunit of measure is gate equivalent is a NAND gate F = (A B),or four transistors
Example: 100k gate IC => 1,00,000 two input NAND gates
The another measure of the IC feature size is the smallest shapeyou can make on a chip and is measured in or lambda.
(since lambda is equal to half of the smallest transistor length,=
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. . .
Origin of ASICs:
Standard parts - initially used to design microelectronic systems
Gradually replaced with a combination ofglue logic (remaining logic
functions), custom ICs, dynamic random-access memory (DRAM)and static RAM (SRAM)
History of ASICs: The IEEE Custom Integrated CircuitsConference (CICC) and IEEE Inter-national ASIC Conference
document the development of ASICs
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CLASSIFICATION OF VLSI DESIGN AT
DIFFERENT LEVEL:
Front End (Coding) (Results)
Back End (Schematics of RTL)(No parasitic Extraction)
Physical End (Layouts)
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(Parasitic Extraction)
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Y- CHART
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ASIC DESIGN FLOW
S-1 Design Entry: Schematic entry
or HDL description
S-2: Logic Synthesis: UsingVerilog HDL or VHDL and Synthesistool, produce a netlist-logic cells
and their interconnect detail
S-3 System Partitioning: Divide alarge system into ASIC sized pieces
S-4 Pre-Layout Simulation: Check
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S-5 Floorplanning: Arrange netlistblocks on the chip.
S-6 Placement: Decide thelocations in a block
S-7 Routing: Make the cell and
block interconnections
S-8 Extraction: Measure theinterconnect R/C cost
S-9 Post-Layout Simulation :Check to see the design still works
with the added load of theinterconnect.
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CLASSIFICATION
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ASICASICVSVS SSTANDARDTANDARD ICIC
o Standard ICs ICs sold as Standard Parts SSI/LSI/ MSI IC
such as MUX, Encoder, Memory Chips, or Microprocessor IC
(NOT ASIC)
o Application Specific Integrated Circuits (ASIC) A Chip for
Toy Bear, Auto-Mobile Control Chip, Different Communication
Chips [ICs not Found in Data Book]
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o oncep ar e n s
oAn IC Customized to a Particular System or Application
Custom ICs
o Digital Designs Became a Matter of Placing of Fewer CICs or
ICs plus Some Glue Logic
o Reduced Cost and Improved Reliability
o Application Specific Standard Parts (ASSP) Controller
Chip for PC or a Modem9
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SSTANDARDTANDARD IC:IC:
oOlder generation IC technology such as TTL ICs could often
require to interconnect 5 to 15 ICs.
oThe wiring would often be very complex and messy.
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Example of system Design using standard ICsExample of system Design using standard ICs
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PROGRAMMABLE
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OGIC
DEVICES
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WHY PROGRAMMABLE LOGIC?
Facts:
It is most economical to produce an IC in large
volumes
Many designs required only small volumes of ICs
Need an IC that can be:
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Produced in large volumes Handle many designs required in small volumes
A programmable logic part can be:
Made in large volumes Programmed to implement large numbers of
different low-volume designs12
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Many programmable logic devices are field-
programmable, i. e., can be programmed outside of
the manufacturing environment Most programmable logic devices are erasable and
reprogrammable.
PROGRAMMABLE LOGIC - ADDITIONALADVANTAGES
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ows up at ng a ev ce or correct on o errors Allows reuse the device for a different design - the
ultimate in re-usability!
Ideal for course laboratories
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WHAT IS PROGRAMMABLE LOGIC?In the world of digital electronic systems, there are threebasic kinds of devices:
Memory: store random information such as the contentsof a spreadsheet or database.
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icroprocessors : execute so tware instructions toperform a wide variety of tasks such as running a wordprocessing program or video game.
Logic : Logic devices provide specific functions, includingdevice-to-device interfacing, data communication, signalprocessing, data display, timing and control operations,and almost every other function.
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FIXED LOGIC V/S PROGRAMMABLE LOGIC
Logic devices can be classified into two broad categories.
Fixed : the circuits in a fixed logic device are permanent,they perform one function or set of functions - oncemanufactured, they cannot be changed.
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Programmable : programmable logic devices (PLDs) arestandard, off-the-shelf parts that offer customers a widerange of logic capacity, features, speed, and voltagecharacteristics - and these devices can be changed at anytime to perform any number of functions.
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FIXED LOGIC
The time required to go from design, to prototypes, to afinal manufacturing run can take from several months tomore than a year, depending on the complexity of the
device. If the device does not work properly, or if the requirements
change, a new design must be developed.
-
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devices involves substantial "non-recurring engineering"costs, or NRE.
NRE represents all the costs customers incur before thefinal fixed logic device emerges from a silicon foundry,
including engineering resources, expensive software designtools, expensive photolithography mask sets formanufacturing the various metal layers of the chip, and thecost of initial prototype devices.
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PROGRAMMABLE LOGIC DEVICE
With PLDs designers use inexpensive software tools to quicklydevelop, simulate, and test their designs.
Design can be quickly programmed into a device, andimmediately tested in a live circuit.
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faster than that of a custom, fixed logic device.
During the design phase customers can change the circuitry asoften as they want until the design operates to their satisfaction.
Once the design is final, customers can go into immediateproduction by simply programming as many PLDs as theyneed with the final software design file. 17
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PLD ADVANTAGES PLDs offer customers much more flexibility during the design cycle because design
iterations are simply a matter of changing the programming file, and the results of design
changes can be seen immediately in working parts.
Low development cost
Less space requirement
Fast Design Time
Less power requirement
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g re a ty
Easy circuit testing
Easy design modification
Less design time
PLDs do not require long lead times for prototypes or production parts PLDs do not require customers to pay for large NRE costs and purchase expensive mask
sets
PLDs can be reprogrammed even after a piece of equipment is shipped to a customer.
In fact, thanks to programmable logic devices, a number of equipment manufacturersnow have the ability to add new features or upgrade products that already are in the field.
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WHO MAKES PLDS ?
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SOME DEFINITIONS
Programmable Logic - a logic element whose
function is not restricted to a particular function. Itmay be programmed at different points of the life
cycle. It is programmed by the semiconductor vendor,
b the desi ner rior to assembl or b the user in
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circuit.
Gate Array - Transistors or gates are fabricated in a
2 dimensional array on a die to form the standardbase of an application specific integrated circuit. The
devices is programmed by custom metal layers
interconnecting nodes in the array. 20
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SOME DEFINITIONS
Standard Cell - This device differs from the gate
array since each cell may be different andoptimized for each "standard" function. There are
no standard layers to the device and each layer of
the chi is a uni ue desi n.
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Programmable Read Only Memory (PROM) -
This device has a fixed, fully decoded AND plane
and a programmable OR plane. The programmableelement for these devices include EPROM,
EEPROM, fuses and antifuses.21
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SOME DEFINITIONS
Programmable Array Logic (PAL) - This devicehas a programmable AND plane and a fixed OR
plane. Device uses an amorphous silicon antifuse asthe programmable element. These are oftenreferred to as Simple Programmable Logic
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.
Programmable Logic Array (PLA) - This devicehas both programmable AND and OR planes. PLA
structures may also appear as part of some CPLDs.
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PROGRAMMABLE LOGIC DEVICES
(WITH DIFFERENT VIEWPOINT)
Programmable Arrays
OR Array
AND Array
Classifications of Simple Programmable Logic Devices (SPLD)
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-
Programmable Array Logic (PAL)
Programmable Logic Array (PLA)
Generic Array Logic (GAL)
More complex
FPGA (field programmable gate arrays)
CPLD (Complex Programmable Logic Devices) 23
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OR ARRAY
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M A i h J T k i
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AND ARRAY
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READ
ONLY
EMORY:(ROM)
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READ ONLYMEMORY:
Consists of an array of semiconductor devices interconnected tostore an array of binary data.
Cant be changed once burned in. Conceptually, consist of a decoder and a memory array.
ROM Types
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Mask programmable ROM fuses programmed during manufacture
Programmable ROM (PROM) 0s programmed by blowing fuses or burning
Erasable PROM (EPROM) programming erased by UV light
Electrically erasable PROM (EEPROM) programming erased via control signals
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Example: A 8 X 4 ROM ( 2NxM ROM)(N = 3 input lines, M= 4 output lines)
In general, a 2NxM ROM will have
an internal Nx 2N decoder andM OR gates, each with 2N input.
The fixed "AND" array is a
READ ONLYMEMORYEXAMPLE
D7D6
D5D4D3
X XX
XX
X
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outputs implementing minterms. The programmable "OR
array uses a single line torepresent all inputs to anOR gate.
An x in the array corresponds
to attaching the minterm to the OR
Read Example: For input (A2, A1, A0)= 001, output is (F3,F2,F1,F0 ) = 0011.
D2D1D0
A1A0
F0F1F2F3
X
XX
X
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PROGRAMMABLE READ-ONLY MEMORY(PROM)
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PROMS
Input: kAddress lines (A)
Output: d Data lines (D)
Function:
Each possible value of A [0..(2^k)-1] has a unique set of d bitsthat are output on D when the corresponding address is
provided on A
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DecoderA1A2
Ak-1
D0 D1 Dd-1
fuses
1
2
(2^k)-1
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What are functions F3, F2 , F1 and F0 in terms of (A2, A1, A0)?
PROM EXAMPLE:
D7D6
D5D4D3A2A
X XX
XX
X
y
F3 = D7 + D5 + D2 = A2A0 + A2A1A0 F2 = D7 + D0 = A2A1A0 + A2A1A0
F1 = D4 + D1 = A2A1A0 + A2A1A0
F0 = D7 + D5 + D1 = A2A0 + A1A0
D2
D1D0
A1A0
BC
F0F1F2F3
XX X
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EXAMPLE:Problem: Tabulate the truth for an 8 X 4 ROM that implements the
following four Boolean functions: A(X,Y,Z) = m(3,6,7);
B(X,Y,Z) = m(0,1,4,5,6)
C(X,Y,Z) = m(2,3,4);
D(X,Y,Z) = m(2,3,4,7)
Solution:
y
Inputs Outputs
X Y Z A B C D
0 0 0 0 1 0 0
0 0 1 0 1 0 0
0 1 0 0 0 1 1
0 1 1 1 0 1 1
1 0 0 0 1 1 1
1 0 1 0 1 0 0
1 1 0 1 1 0 0
1 1 1 1 0 0 1
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IMPLEMENTATION USING 8X4 ROM.
0
1
X
X
33
3
A B C D
Z
Y
X
- -
Decoder 4
5
6
7
XX
X
X
XX
X
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IMPLEMENTING LOGIC IN PROMS
A B F1 F2 F3
F1=A+B
F2=AB
F1=AB+AB
0011
0101
1101
0010
0110
F1=D0+D1+D3
F2=D2
F1=D1+D234
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D3
IMPLEMENTING LOGIC IN PROMS
X
F1=D0+D1+D3
F2=D2
F1=D1+D2
4 X 3 ROM ( 22x3 ROM)
2-to-4
Decoder
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D2
D1
D0
B
F0
F1F2
X
XXX
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EXAMPLE: 2: USING 8X6 ROM, IMPLEMENT DESIGN THAT
GENERATES SQUARE OF INPUT,AT THE OUTPUT.
Design a square lookup table for F(X) = XF(X) = X22 using ROM
Inputs Outputs
X2 X1 X0 SQ F5 F4 F3 F2 F1 F0
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0 0 1 1 0 0 0 0 0 1
0 1 0 4 0 0 0 1 0 0
0 1 1 9 0 0 1 0 0 1
1 0 0 16 0 1 0 0 0 0
1 0 1 25 0 1 1 0 0 1
1 1 0 36 1 0 0 1 0 0
1 1 1 49 1 1 0 0 0 1
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0
1
F5=D6+D7F4=D4+D5+D7
F3=D3+D5F2=D2+D6F1=0F0=D1+D3+D5+D7
3
F5 F4 F3 F2 F1 F0
X2
X1
X0
- -
Decoder 4
5
6
7
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01
2
3
X2
X1
3-to-8
Lets think something more ahead........
Ready??
= X0= X0EffectivelyEffectively
NotNot UsedUsed
F5 F4 F3 F2 F1 F0
X0
eco er 4
5
6
7
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01
2
3
X2 3-to-8
F5 F4 F3 F2 F0
X0
Decoder 4
5
6
7
F1
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Using 8x2 ROM, Implement Full
adder logic Design.
in x2 M Im l m n Full
EXERCISE:
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Subtraction logic Design.
Using ROM, Implement the logicdesign that generates gray code for
given 4 bit binary input.
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PROGRAMMABLEARRAY
LOGIC(PAL)
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PROGRAMMABLEARRAY LOGIC (PAL)
The PAL is the opposite of the ROM, having a programmableset of ANDs combined with fixed ORs.
Disadvantage
NxM ROM guaranteed to implement any M functions of Ninputs. PAL may have too few inputs to the OR gates.
Advantages or g ven n erna comp ex y, a can ave arger an
Some PALs have outputs that can be complemented, addingPOS functions
No multilevel circuit implementations in ROM (without externalconnections from output to input).PAL has outputs from OR
terms as internal inputs to all AND terms, makingimplementation of multi-level circuits easier.
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PROGRAMMABLEARRAY LOGIC: (PAL)
Basic PAL configuration is the same as a PLA
The number of AND gates fed to each OR gate is fixedAND terms are not shared by OR gates
Special case of PLA
AND is programmable
OR is fixed
Less expensive than PLA
Easier to program
Less flexibility
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PROGRAMMABLE ARRAY LOGIC (PAL)
It was developed to overcome certain disadvantages of PLA, such as longer
delays due to the additional fusible links that result from using twoprogrammable arrays and more difficult complexity.
The PAL is most common one-time programmable (OTP) logic device and is
implemented with bipolar technology (TTL or ECL) 44
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PROGRAMMABLEARRAYLOGIC
Basic structure of PAL
PAL implementation of SOP form
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PAL:
Each PAL input must drive many AND gates
Buffers must be used
An unprogrammed segment
Notation:
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PAL REPRESENTATION
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PAL REPRESENTATION
Standard PAL representation
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PAL I
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PAL IMPLEMENTATION:
Example of Any Random Design:???????????(Dont waste your time in analyzing the design type)
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PAL I
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PAL IMPLEMENTATION:
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SOLVE THE EXAMPLE:
Illustrate the simultaneous PAL Implementation of
below 3 function:A) fa (A,B,C,D)= m(0,2,7,10) + d(12,13)
B) fb (A,B,C,D)= m(2,4,5) + d(6,7,8,10)
c , , , = m 2,7,8 + 0,13
A)
B)
C)
Ans: F1= ABC+BCD+ABCF2= ACD+BCD+ABD+ABC
F3= ACD+ABC+ABCD
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S
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SOLUTION:
Result of the above 3 functionIs as below
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PAL DEVICE
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PAL DEVICE
A
IO1
IO1 IO1B BA A IO1 IO2
ProgrammableAND Plane
B
IO2
FixedOR Plane
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PAL DEVICE DESIGN EXAMPLE
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PAL DEVICE DESIGN EXAMPLE
A
IO1
IO1 IO1B BA A D DC C
Notprogrammed
B
IO2
DCBADCAIO1IO2
DCBADCADCBACABIO2
DCBACABIO1
++=
+++=
+=
Reused
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PROGRAMMABLEARRAYLOGIC
E
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EXAMPLE
4-input, 4-output PAL
with fixed, 3-input
OR terms What are the
equations for F1roug 3
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FIG SHOW THE TYPICAL PAL
STRUCTURE. WITH 16 INPUTS
AND 8 OUTPUT.
PAL:P16H8
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PROGRAMMABLE
LOGIC
ARRAY(PLA)
PROGRAMMABLE LOGIC ARRAY (PLA)
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PROGRAMMABLE LOGIC ARRAY (PLA)
PLA Programmable Logic Array (PLA) is a relatively small FPD
that contains two levels of logic, an AND-plane and an
OR-plane, where both levels are programmable
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UNPROGRAMMED PLA
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UNPROGRAMMED PLA
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PLA STRUCTURE:
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Programmable AND Plane
Programmable Node
Programmable OR Plane
-
X Y O1 O2 O3 O4
Connect
Disconnect
X X Y Y
X
YXY XY
XY
XY
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PLA PROGRAMMING:
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Programmable AND Plane Programmable OR Plane
YZ
XZ
X Y Z XY+YZ ? ?
XZ+XYZ
XYZ
XY
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PROGRAMMABLE LOGICARRAY:
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Consider a PLA with
3 inputs
4 outputsAnd implement the following function using it.
EXAMPLE
F0= AB + AC F1= AC + B
F2= AB + BC
F3= B + AC
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STEP:1
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STEP:1
F0= AB + AC
F1= AC + B
F2= AB + BC F3= B + AC
List the Product Terms (5 unique product terms)
AB
AC
B
BC
AC
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STEP:2
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STEP:2
PLA TABLE IMPLEMENTATION:
F0= AB + AC
F1= AC + B F2= AB + BC
F3= B + AC
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PLA
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EXAMPLE:
F1 = AB+ C
F2 = AC + BC
F3 = AB + AC
F4 = AC + BC + ABC
Product (Specified) Outputs
Term A B C F1 F2 F3 F4
AB' 1 0 - 1 0 1 0
C - - 1 1 0 0 0
A'C' 0 - 0 0 1 1 1
BC - 1 1 0 1 0 1
AB'C 1 0 1 0 0 0 1
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PLA R
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PLA REPRESENTATIONInputs
AB'
C
CBA
Outputs
A'C'
BC
AB'C
F1 F2 F3 F4
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INTERNAL PLA STRUCTURE
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INTERNAL PLA STRUCTURE
+ V
A B C
A' B' C' AB'
C
Inputs
+ V
+ V
+ V
F1 F2 F3 F4
A'C'
BC
AB'C
Outputs 67
INTERNAL PLA STRUCTURE
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+ V
A B C
A' B' C' AB'
C
INTERNAL PLA STRUCTUREInputs
+ V
+ V
+ V
F1
F2
F3
F4
A'C'
BC
AB'C
Outputs
The AND plane lines get pulled up to +V
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Internal PLA Structure
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+ V
A B C
A' B' C' AB'
C
0
Inputs
+ V
+ V
+ V
F1
F2
F3
F4
A'C'
BC
AB'C
The AND plane lines stay at +V unless oneof the connected inputs pulls it low.
Outputs 69
Internal PLA Structure
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+ V
A B C
A' B' C' AB'
C
1
Inputs
+ V
+ V
+ V
F1
F2
F3
F4
A'C'
BC
AB'C
The AND plane lines stay at +V unless oneof the connected inputs pulls it low.
Outputs 70
Internal PLA Structure
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+ V
A B C
A' B' C' AB'
C
Inputs
+ V
+ V
+ V
F1
F2
F3
F4
A'C'
BC
AB'C
The OR plane lines get pulled down to Ground
Outputs 71
Internal PLA Structure
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+ V
A B C
A' B' C' AB'
C
Inputs
+ V
+ V
+ V
F1
F2
F3
F4
A'C'
BC
AB'C
The OR plane lines get pulled down to Ground
Outputs 72
Internal PLA Structure
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+ V
A B C
A' B' C' AB'
C
Inputs
+ V
+ V
+ V
F1
F2
F3
F4
A'C'
BC
AB'C
The OR plane lines stay at GND unless oneof the AND plane lines pulls it high.
Outputs 73
Internal PLA Structure
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+ V
A B C
A' B' C' AB'
C
Inputs
+ V
+ V
+ V
F1
F2
F3
F4
A'C'
BC
AB'C
The OR plane lines stay at GND unless oneof the AND plane lines pulls it high.
Outputs 74
Internal PLA Structure
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+ V
A B C
A' B' C' AB'
C
Inputs
+ V
+ V
+ V
F1
F2
F3
F4
A'C'
BC
AB'C
The OR plane lines stay at GND unless oneof the AND plane lines pulls it high.
Outputs 75
Internal PLA Structure
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+ V
A B C
A' B' C' AB'
C
Inputs
+ V
+ V
+ V
F1
F2
F3
F4
A'C'
BC
AB'C
The OR plane lines stay at GND unless oneof the AND plane lines pulls it high.
Outputs 76
ANOTHER PLA EXAMPLE:
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Implement these equations:
X = ABC + BD + ABD + CD
Y = BC + D
Z = CD + BD + ABC
in this PLA: CBA D
8 terms
1 2 3 4
5 6
7 2 8
X Y Z
4 input, 6 AND Plane,
3 OR plan lines
How can we implement 8 product terms with 6 AND plane lines? 77
PLA EXAMPLE
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Implement these equations:
X = ABC + BD + ABD + CD
Y = BC + D
Z = CD + BD + ABC
X
Y
Z
C D00 01 11 10
C D00 01 11 10
C D00 01 11 10
00 00 00
01 01 01
11 11 11
10 10 10
78
PLA EXAMPLE
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Implement these equations:
X = ABC + BD + ABD + CD
Y = BC + D
Z = CD + BD + ABC
X
Y
Z
C D00 01 11 10
C D00 01 11 10
C D00 01 11 10
00 1 1 1 1 00 00
01 1 01 01
11 1 1 11 11
10
1 1 110 10
79
PLA EXAMPLE
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Implement these equations:
X = ABC + BD + ABD + CD
Y = BC + D
Z = CD + BD + ABC
X
Y
Z
C D00 01 11 10
C D00 01 11 10
C D00 01 11 10
00 1 1 1 1 00 1 1 1 1 00
01 1 01 01
11 1 1 11 1 1 11
10
1 1 110
1 1 1 110
80
PLA EXAMPLE
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Implement these equations:
X = ABC + BD + ABD + CD
Y = BC + D
Z = CD + BD + ABC
X
Y
Z
C D00 01 11 10
C D00 01 11 10
C D00 01 11 10
00 1 1 1 1 00 1 1 1 1 00 1 1
01 1 01 01
11 1 1 11 1 1 11 1 1 1 1
10
1 1 110
1 1 1 110
1 1 1
81
PLA Example
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X
Y
Z
CD is in X and Y and looks useful
C D00 01 11 10
C D00 01 11 10
C D00 01 11 10
00 1 1 1 1 00 1 1 1 1 00 1 1
01 1 01 01
11 1 1 11 1 1 11 1 1 1 1
10
1 1 110
1 1 1 110
1 1 1
82
PLA EXAMPLE
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BD is in all three functions
CD is in X and Y and looks useful
X
Y
Z
C D00 01 11 10
C D00 01 11 10
C D00 01 11 10
00 1 1 1 1 00 1 1 1 1 00 1 1
01 1 01 01
11 1 1 11 1 1 11 1 1 1 1
10 1 1 1 10 1 1 1 1 10 1 1 1
83
PLA EXAMPLE
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CD is in X and Y and looks useful
BD is in all three functions
ABC and ABC cover a lot of minterms
X
Y
Z
C D00 01 11 10
C D00 01 11 10
C D00 01 11 10
00 1 1 1 1 00 1 1 1 1 00 1 1
01 1 01 01
11 1 1 11 1 1 11 1 1 1 1
10 1 1 1 10 1 1 1 1 10 1 1 1
84
PLA Example
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BD is in all three functions
CD is in X and Y and looks useful
ABC and ABC cover a lot of minterms
X
Y
Z
The only ones left are AB and CD
C D00 01 11 10
C D00 01 11 10
C D00 01 11 10
00 1 1 1 1 00 1 1 1 1 00 1 1
01 1 01 01
11 1 1 11 1 1 11 1 1 1 1
10 1 1 1 10 1 1 1 1 10 1 1 1
85
PLA EXAMPLE
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X = CD + BD + AB + ABC
Y = CD + BD + ABC + ABC
Z = BD + CD + ABC
X
Y
Z
All of the functions are covered using only 6 product terms
C D00 01 11 10
C D00 01 11 10
C D00 01 11 10
00 1 1 1 1 00 1 1 1 1 00 1 1
01 1 01 01
11 1 1 11 1 1 11 1 1 1 1
10 1 1 1 10 1 1 1 1 10 1 1 1
How is this possible?86
PLA EXAMPLE
X CD BD AB ABC
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X = CD + BD + AB + ABC
Y = CD + BD + ABC + ABC
Z = BD + CD + ABC
Product Input Output
Term A B C D X Y Z
C'D'
B'D'
AB'
ABC
A'BC
CD
87
PLA EXAMPLE
X CD BD AB ABC
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X = CD + BD + AB + ABC
Y = CD + BD + ABC + ABC
Z = BD + CD + ABC
Product Input Output
Term A B C D X Y Z
C'D' - - 0 0
B'D' - 0 - 0
AB' 1 0 - -
ABC 1 1 1 -
A'BC 0 1 1 -
CD - - 1 1
88
PLA EXAMPLE
X CD BD AB ABC
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X = CD + BD + AB + ABC
Y = CD + BD + ABC + ABC
Z = BD + CD + ABC
Product Input Output
Term A B C D X Y Z
C'D' - - 0 0 1 1 0
B'D' - 0 - 0 1 1 1
AB' 1 0 - - 1 0 0
ABC 1 1 1 - 1 1 0
A'BC 0 1 1 - 0 1 1
CD - - 1 1 0 0 1
89
PLA EXAMPLE
X CD + BD + AB + ABC Product Input Output
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X = CD + BD + AB + ABCY = CD + BD + ABC + ABC
Z = BD + CD + ABC
Product Input OutputTerm A B C D X Y Z
C'D' - - 0 0 1 1 0
B'D' - 0 - 0 1 1 1
AB' 1 0 - - 1 0 0
ABC 1 1 1 - 1 1 0
A'BC 0 1 1 - 0 1 1
CD - - 1 1 0 0 1
CBA D
X Y Z 90
PROGRAMMABLE LOGICARRAY:
EXAMPLE
F AB BC ACA
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product
T
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F1 = AB +BC + AC
F2 = AB + AB
= (AB + AB)
X
A
B
C
1X XX A B
Terms
????
Term A B C F1 F2
AB 1 1 -- 1 1
BC -- 1 1 1 --
AC 1 -- 1 1 --
3-input, 2-output PLAwith 4 product terms
1
F1
F2
C C B B A A 0
2
3
4X
XX
X X
X
X
X
X
X
X
A C
B C
A B Here X-OR isworking as
controlledinverter
AB 0 1 -- -- 1
91
EXAMPLE FOR PRACTICE:
Realize the following functions using PLA
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Realize the following functions using PLA
A) F1= m(0,1,4,6)
F2= m(2,3,4,6,7)
F3= m(0,1,2,6)F4= m(2,3,5,6,7)
B) F1= m(1,2,4,6)F2= m(2,6)
F3= m(0,1,6,7)
F4= m(1,2,3,5,7)
C) Write a Program Table to implement BCA to XS-3 Code Conversion using PLA. 92
Features of PLAs:
PLA i i i
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PLAs come in various sizes
Typical size is 16 inputs, 32 product terms, 8
outputs
Each AND gate has large fan-in this limits thenumber of inputs that can be provided in a PLA
16 =
32 permitted (since 32 AND gates) in a typical PLA
32 AND terms permitted large fan-in for OR gates
as well
This makes PLAs slower and slightly more
expensive than some alternatives
8 outputs could have shared minterms, but not
required93
PROGRAMMABLE LOGICARRAY(PLA) Compared to a ROM and a PAL a PLA is the most flexible
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Compared to a ROM and a PAL, a PLA is the most flexiblehaving a programmable set of ANDs combined with aprogrammable set of ORs.
Advantages
A PLA can have implementation of large equations thanthat of the same size ROM or PAL.
A PLA has all of its product terms connectable to all outputs,
ORs
Some PLAs have outputs that can be complemented, adds POSfunctions implementation.
Disadvantage
Expensive to manufacture
Often, the product term count limits the application of a PLA.
Offer somewhat poor speed-performance, due to the two levels of
configurable logic,94
PLA fl ibl th PAL i b th AND &
PAL VS PAL
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PLAs are more flexible than PALs since both AND &
OR planes are programmable in PLAs.
Because both AND & OR planes are programmable,
PLAs expensive to fabricate and have large
ro a ation dela than PAL.
95
By using fix OR gates, PALs are cheaper and fasterthan PLAs.
PALs usually contain D flip-flops connected to the
outputs of OR gates to implement sequential circuits. PLAs and PALs are usually referred to as SPLD.
GENERIC ARRAY LOGIC (GAL)
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of the PAL and was invented by Lattice Semiconductor.
The GAL was an improvement on the PAL because one device was ableto take the place of many PAL devices or could even have functionality not
covered by the original range.
Its primary benefit was that it was erasable and re-programmable making
design changes easier for engineers.
The differences between GAL and PAL device is that the GAL isreprogrammable
The GAL is programmable again and again because it uses E2CMOS
(electrically erasable CMOS) technology instead of bipolar technology and
fusible links.
96
ROM, PAL AND PLA CONFIGURATIONS
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(a) Programmable read-only memory (PROM)
InputsFixed
AND array(decoder)
ProgrammableOR array Outputs
Programmable
Connections
(b) Programmable array logic (PAL) device
Inputs Programma leAND array
xeOR array
Outputsrogramma e
Connections
(c) Programmable logic array (PLA) device
Inputs ProgrammableOR array
OutputsProgrammableConnections
ProgrammableConnections
ProgrammableAND array
97
SUMMARY:
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98
COMPARISON BETWEEN PROM, PAL, PLA
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99
PLD PROGRAMMING DEVICES
A DEVICE PROGRAMMER is used tot f th B l l i tt i t
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transfer the Boolean logic pattern intothe programmable device.
In the early days of programmable logic,every PLD manufacturer also produced aspecialized device programmer for itsfamily of logic devices.
Later universal device ro rammerscame onto the market that supported
several logic device families fromdifferent manufacturers.
Today's device programmers usually canprogram common PLDs (mostlyPAL/GAL equivalents) from all existing
manufacturers. Common file formats used to store the
Boolean logic pattern (fuses) are JEDEC,Altera POF (Programmable Object File),or Xilinx BITstream.
100
PLD LANGUAGES
Many PLD programming devices accept input in a
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y p g g p pstandard file format, commonly referred to as 'JEDECfiles. They are analogous to software compilers.
The languages used as source code for logic compilers
are called hardware description languages, or HDLs.
- CUPL Universal Compiler for Programmable Logic
ABEL Advanced Boolean Expression Language Palasm Sorry No Acronym Here
HDL frequently used for higher-level -complexity
devices: Verilog
VHDL 101
DESIGN FLOWCHART OF PLD
DEFINATION CODEWRITING
CODEIMPLEMENTATION
CODE
SIMULATION
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WRITING
BINARY/HEX FILEGENERATION
INTERFACING
IMLEMENTATION IN DEVICE
102
CONCLUSION:
The value of programmable logic has always
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e va ue o p og a ab e og c as a waysbeen its ability to shorten developmentcycles for electronic equipment
manufacturers.And help them to get their product to
.
Integrate more functions inside theirdevices,
Reduce costs.
Time-saving.Programmable logic is certain to expand
its popularity with digital designers. 103
QUESTIONS
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Q
104
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