Download - ADC and TDC Implemented Using FPGA Jinyuan Wu, S. Hansen and Z. Shi Fermi National Accelerator Laboratory, Batavia, IL 60510, USA Single Slope ADC != Wilkinson.

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Page 1: ADC and TDC Implemented Using FPGA Jinyuan Wu, S. Hansen and Z. Shi Fermi National Accelerator Laboratory, Batavia, IL 60510, USA Single Slope ADC != Wilkinson.

ADC and TDC Implemented Using FPGA

Jinyuan Wu, S. Hansen and Z. Shi

Fermi National Accelerator Laboratory, Batavia, IL 60510, USA

Single Slope ADC != Wilkinson ADC

FPGA Direct Analog Signal Digitization

Single Slope ADC: Ramping-Comparing

Internal Layout Inside FPGA

FPGA ADC and TDC

Intrinsically, FPGA is a digital device. However, with suitable use of the FPGA resources, it is possible to use FPGA to digitize multi-channel analog waveforms. The digitized waveforms can be directly processes in the FPGA. There are several possible schemes of digitizing analog signals. One of the schemes we used in our FPGA ADC study is based on the ramping-comparing approach.

In today’s FPGA devices, differential input buffers are good comparators within a sufficiently large range of input voltage levels, since they are designed to be compatible with various differential signaling standards. Comparator-based ADC schemes can be implemented with FPGA.

In our tests, the analog inputs are directly connected to the FPGA input pins. A passive RC network is connected to the FPGA output pins so that a periodic reference voltage ramp can be generated. The differential input buffers are used as comparators to generate logic transitions inside the FPGA when the reference voltage ramps across the input voltage levels. The transition times are digitized by the TDC block implemented in the FPGA. Since the period, the RC network parameters and the starting time of the ramps are known the input voltage levels can be derived from the transition times. (In some references, the single-slope scheme is mistakenly referred as Wilkinson ADC that is based on dual-slope principle.)

A key functional block, Time-to-Digit-Converter (TDC) is needed in FPGA. The TDC we used in this work is multi-sampling scheme with quad clock. In our TDC design, the four samples are transferred into a bit pattern in a single clock domain immediately and only one set of edge detect, pulse filter and count latch circuit is used. The meta-stability is limited at the sampling stage only and in fact, the meta-stability in sampling stage does no harm but carrying the input signal arrival time information. The decoding becomes very simple in our design. The detail is described in the paper.

The TDC in FPGA alone is already very useful. The TDC card designed for Fermilab MIPP upgrade project is documented in this paper.

The multi-sampling structure can have other applications. A deserializer circuit known as “Digital Phase Follower” (DPF) is also documented. Using DPF, any FPGA input can be used to receive serial data without needing dedicated deserializer that is only available in high-end FPGA families. The DPF can compensate input data phase drift not only due to cable temperature variation, but also due to crystal oscillator frequency difference between transmitter and receiver.

AMP &Shaper

AMP &Shaper

AMP &Shaper

AMP &Shaper

ADC

ADC

ADC

ADC

FPGA AMP &Shaper

AMP &Shaper

AMP &Shaper

AMP &Shaper

FPGA

TDC

TDC

TDC

TDC

R1 R1

C

R2

VREF

T1

V1

T2

V2

T3

V3

T4

V4

4Ch

Enc

ode

c0

c90

c180

c270

c0Data In

Q0

Q1

Q2

Q3QF

QE

QD

c90

DV

T0T1

TS

FPGA

TDC

TDC

50 50

1000pF

100

VREF

Input Waveform

0

8

16

24

32

40

48

56

64

0 32 64 96 128 160 192 224 256

Leading Ramp Trailing RampRaw Data

Input Waveform & Reference VoltageOverlap Trigger

1

1.5

2

2.5

2500 3000 3500 4000 4500 5000 5500

t(ns)

V

Leading Ramp Trailing Ramp

Converted

FPGA

TDC

TDC

50 50

150pF

100

VREF

= 7.5 ns Reference Voltage

Input Waveform

1

1.5

2

2.5

0 32 64 96 128 160 192 224 256

V

Leading Ramp Trailing Ramp

Converted

The data measured by trailing ramp is much more smoother than the leading ramp for small pulses.

0

8

16

24

32

40

48

56

64

0 32 64 96 128 160 192 224 256

Leading Ramp Trailing RampRaw Data

Small pulses are emphasized by the trailing ramp measurement.

Test Result: BD3_19, Quasi-Linear VREF

Test Result: BD4_22, Exponential VREF

= 59 ns, Reference Voltage

Micro-processor address line driven by 45 MHz clock.32 TDC bin = 1 clock cycle (0.69ns LSB)

Micro-processor data line.Data out from different sources.

0

200

400

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1600

0 32 64 96 128 160 192 224 256

0

1000

2000

3000

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5000

6000

7000

8000

9000

0 32 64 96 128 160 192 224 256

eZ80

RAMFlashRAM

FPGA

TDC

eZ80

RAMFlashRAM

FPGA

TDC

45MHz

45MHz

Data Concentration

FPGA

48CH TDC FPGA

48CH TDC FPGA

Multi-Sampling Based TDC

TDC Bench Test Results

The 96-Channel TDC Module

TABLE I MIPP TDC CARD PARAMETERS

Main Input Clock: RF 53.102MHz, 18.8ns

Internal Clock: CK212 212.4MHz, 4.708ns

TDC Resolution: LSB 1.18ns

Hit Rate Limiter Setting 4hits/256CK212

Double Hit Min. Separation 4xCK106, 37.7ns

Event Window 2 x 1.2s

Absolute Maximum Hits/event/48ch 123hits+5header/trailers

Event Maximum Size/96ch 256 x 2Bytes

SDRAM port data rate 53MHz x 2Bytes

Number of events/spill <32K

Absolute Maximum data/spill/FE card 8M words

Absolute Maximum data/spill/8 FE 128MB, 1280Mbits

Readout Chain Data Rate 26.5Mbits/s

Absolute Maximum Spill Readout Time 48.3sec

Digital Phase Follower (DPF): A TDC-Like Deserializer

c0

c90

c180

c270

c0In

MultipleSampling

ClockDomain

Changing

b0

b1

FrameDetection

DataOut

Tri-speedShift

Register

Shift2

Shift0

was3is0

SEL

was0is3

Trans.Detection

Q0

Q1

Q2

Q3QF

QE

QD

FPGA FPGA

X1 X2

•It is used for serial communication between low-cost FPGA devices.•No dedicated clock-data-recovery (CDR) circuitry is needed.•It tolerates multi-crystal operations.

b0

SEL

Q0

Q1

Q2

Q3

QF

QE

QD

Newer Samples

Older Samples

SelectedSample

SelectedSample

SelectedSample

SelectedSample

SEL=0 SEL=1 SEL=2 SEL=3

b0

SEL

Q0

Q1

Q2

Q3

QF

QE

QD

Newer Samples

Older Samples

SelectedSample

SelectedSample

SelectedSample

SelectedSample

SEL=0 SEL=1 SEL=2 SEL=3

Q0

Q1

Q2

Q3

QF

QE

QD

OldSelection

NewSelection

SEL was 0 SEL is 3

b0

b1

Tri-speedShift

Register

Shift2

Shift0

SEL

was0is3

Q0

Q1

Q2

Q3

Newer Samples

Older Samples

Q0

Q1

Q2

Q3

QF

QE

QD

OldSelection

NewSelection

SEL was 0 SEL is 3

b0

b1

Tri-speedShift

Register

Shift2

Shift0

SEL

was0is3

Q0

Q1

Q2

Q3

Newer Samples

Older Samples

Q0

Q1

Q2

Q3

QF

QE

QD

NewSelection

OldSelection

SEL was 3 SEL is 0

b0

b1

Tri-speedShift

Register

Shift2

Shift0

was3is0

SEL

Q0

Q1

Q2

Q3

Newer Samples

Older Samples

Q0

Q1

Q2

Q3

QF

QE

QD

NewSelection

OldSelection

SEL was 3 SEL is 0

b0

b1

Tri-speedShift

Register

Shift2

Shift0

was3is0

SEL

Q0

Q1

Q2

Q3

Newer Samples

Older Samples