Download - 8 Cmos Capacitance

1Dr. Bassel Soudan – University of SharjahVLSI Design

CMOS Capacitance Estimation


MOS Transistor Capacitance

• Any two conductors separated by an insulator have capacitance

• Gate to channel capacitor is very important– Creates channel charge necessary for operation

• Source and drain have capacitance to body– Across reverse-biased diodes

– Called diffusion capacitance because it is associated with source/drain diffusion


MOS Transistor CapacitanceGate

DrainSource

CGB

CDBCSB

CGS CGD

Gate

DrainSource

CGB

CDBCSB

CGS CGD

VDD


Gate Capacitance

• Define Cpermicron = CoxL– Typically about 2 fF/µm

• Therefore, CGB = Cpermicron X W

• Realistically, there are additional capacitances.However, the aboverelationship is a good approximationof the gatecapacitance.

n+ n+

p-type body

W

L

tox

SiO2 gate oxide(good insulator, εox = 3.9ε0)

polysilicongate

WLCt

WLC OX

OX

OXGB ==

ε


Diffusion Capacitance

• CSB, CDB

• Undesirable, called parasitic capacitance

• Capacitance depends on area and perimeter– Comparable to CG for

contacted diffusion

– ½ CG for uncontacted

– Varies with process


MOSFET Resistance

• The resistance of a MOSFET transistor must be determined from the Shockley I-V relationships.– However, Ids(Vds, Vgs).

– Therefore, R – the resistance to current moving from the drain to the source is:

• However,– Shockley models for MOSFET transistor are not

accurate enough for modern transistors

– Too complicated for hand analysis

1−

⎟⎟⎠

⎞⎜⎜⎝

⎛∂∂

=ds

ds

V

IR


Effective Resistance

• Simplification: treat transistor as resistor– Replace with effective resistance R

• Ids = Vds/R

– R averaged across switching range of digital gate• Simulate the transistor driving a known capacitance and

measure the time constant.

• Too inaccurate to predict current at any given time– But good enough to predict RC delay


RC Delay Model

• Use equivalent circuits for MOS transistors– Ideal switch + capacitances and ON resistance

– Unit nMOS has resistance R, capacitance C

– Unit pMOS has resistance 2R, capacitance C• The PMOS resistance should actually be (k’n/k’p)R

• Capacitance proportional to width

• Resistance inversely proportional to width

kg

s

d

g

s

d

kCkC

kCR/k

kg

d

s

g

s

d

kC

kC

kC

2R/k


RC Values

• Capacitance– C = Cg = Cs = Cd = 2 fF/µm of gate width

– Values similar across many processes

• Resistance– R ≈ 6 KΩ*µm in 0.6um process

– Improves with shorter channel lengths

• Unit transistors– May refer to minimum contacted device (4/2 λ)

– Or maybe 1 µm wide device

– Doesn’t matter as long as you are consistent


Input Capacitance of the CMOS Inverter

• The input capacitance of the CMOS inverter can be written as:– Cin = CGN + CGP = (WN + WP) Cpermicron

– Cpermicron = COX X L:• COX – the oxide capacitance which depends on the type

of oxide used and is inversely dependent on the thickness of the oxide layer.

– COX is typically in the range of ~700aF/µm2

» a stands for atto – 10-18.

• L – the length of the channel.


Example

• Calculate the input capacitance for a CMOS inverter with the following characteristics:

– COX = 690 aF/µm2

– WN / LN = 4µm / 2µm– WP / LP = 8µm / 2µm

Using the expressions from above:Cin = (WN + WP) Cpermicron

Cpermicron = L COX

Cpermicron = 2µm X 690 aF/µm2 = 1.38 fF/µmCin = (4µm + 8µm) X 1.38 fF/µmCin = 16.56 fF


Inverter Delay Estimate

• Estimate the delay of a fanout-of-1 inverter

2

1A

Y 2

1




C

CR

2C

2C

R

2

1A

Y

C

2C

Y2

1




C

CR

2C

2C

R

2

1A

Y

C

2C

C

2C

C

2C

RY

2

1




d = 6RC

C

CR

2C

2C

R

2

1A

Y

C

2C

C

2C

C

2C

RY

2

1


Delay Components

• Delay has two parts– Parasitic delay – due to capacitances of the

driving gate itself.• 3 RC in the inverter example above.

• Independent of load.

– Effort delay – due to capacitances of the load gates.

• The other 3 RC in the inverter example above.

• Depends on the number and type of driven gates.


Example: 3-input NAND

• Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).



• Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).


Ex.: Capacitances of a 3-input NAND

• Determine the parasitic capacitances of a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).

3

3

222

3


3-input NAND Caps

• Annotate the 3-input NAND gate with gate and diffusion capacitance.

2 2 2

3

3

3


3-input NAND Caps


2 2 2

3

3

33C

3C

3C

3C

2C

2C

2C

2C

2C

2C

3C

3C

3C

2C 2C 2C


Combining Capacitances

• Capacitors on source diffusions of transistors connected to VDD or GND will be shorted out.

• The DC voltage on the second terminal of a capacitor is irrelevant to delay calculation.– Therefore, all capacitors will be estimated as

terminating to GND.

• Combine parallel and series capacitances in the normal manner.


3-input NAND Caps


9C

3C

3C3

3

3

222

5C

5C

5C


Elmore Delay

• ON transistors look like resistors

• Pullup or pulldown network modeled as RC ladder

• Elmore delay of RC ladder

( ) ( )nodes

1 1 1 2 2 1 2... ...

pd i to source ii

N N

t R C

R C R R C R R R C

− −≈

= + + + + + + +

∑

R1 R2 R3 RN

C1 C2 C3 CN



• Estimate worst-case rising and falling delay of 2-input NAND driving h identical gates.

h copies

2

2

22

B

Ax

Y



• Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.

h copies6C

2C2

2

22

4hC

B

Ax

Y




h copies6C

2C2

2

22

4hC

B

Ax

Y

R

(6+4h)CY ( )6 4pdrt h RC= +




h copies6C

2C2

2

22

4hC

B

Ax

Y




h copies6C

2C2

2

22

4hC

B

Ax

Y

( ) ( ) ( ) ( )( )

2 2 22 6 4

7 4

R R Rpdft C h C

h RC

= + + +⎡ ⎤⎣ ⎦= +

(6+4h)C2CR/2

R/2x Y


7C

3C

3C3

3

3

222

3C

2C2C

3C3C

IsolatedContactedDiffusionMerged

UncontactedDiffusion

SharedContactedDiffusion

Diffusion Capacitance

• we assumed contacted diffusion on every s / d.

• Good layout minimizes diffusion area

• Ex: NAND3 layout shares one diffusion contact– Reduces output capacitance by 2C

– Merged uncontacted diffusion might help too


Layout Comparison

• Which layout is better?

AVDD

GND

B

Y

AVDD

GND

B

Y


Determining the Total Delay for a Circuit

• In order to determine the total delay for a circuit, one has to determine the delay of each stageand then calculate the total delay for all stages combined.– Two delays: rising and falling.

• Example, using Elmore Delay Model, determine the total delay of the following circuit:

IN

OUT

12 C


Determine Transistor Sizes

IN

OUT

12 C

P: 2N: 1 P: 2

N: 2P: 2N: 1 P: 4

N: 1

P: 2N: 3

P: 2N: 1


Assume Logic Transition

IN

OUT

12 C

10PDN

PUN

PDN

PUNP: 2N: 1 P: 2

N: 2P: 2N: 1 P: 4

N: 1

P: 2N: 3

P: 2N: 1


Determine Individual Stage Delays

IN

OUT

12 C

10PDN

PUN

PDN

PUNP: 2N: 1 P: 2

N: 2P: 2N: 1 P: 4

N: 1

P: 2N: 3

P: 2N: 1

R 3C 4(4C)

d = 19RC



IN

OUT

12 C

10PDN

PUN

PDN

PUNP: 2N: 1 P: 2

N: 2P: 2N: 1 P: 4

N: 1

P: 2N: 3

P: 2N: 1

R 6C 3C

d = 9RC



IN

OUT

12 C

10PDN

PUN

PDN

PUNP: 2N: 1 P: 2

N: 2P: 2N: 1 P: 4

N: 1

P: 2N: 3

P: 2N: 1

R 3C 5C + 5C + 3C = 13C

d = 16RC



IN

OUT

12 C

10PDN

PUN

PDN

PUNP: 2N: 1 P: 2

N: 2P: 2N: 1 P: 4

N: 1

P: 2N: 3

P: 2N: 1

R/2 4C 6C

R/2

12C

d = (R/2)4C + (R/2 + R/2) (6C + 12C) = 20RC


Total Rising Output Delay

IN

OUT

12 C

10PDN

PUN

PDN

PUNP: 2N: 1 P: 2

N: 2P: 2N: 1 P: 4

N: 1

P: 2N: 3

P: 2N: 1

Tpdr = 19RC + 9RC + 16RC + 20RC = 64RC


Other Logic Transition

IN

OUT

12 C

10PUN

PDN

PUN

PDNP: 2N: 1 P: 2

N: 2P: 2N: 1 P: 4

N: 1

P: 2N: 3

P: 2N: 1


IN

OUT

12 C


10PUN

PDN

PUN

PDNP: 2N: 1 P: 2

N: 2P: 2N: 1 P: 4

N: 1

P: 2N: 3

P: 2N: 1

R 3C 4(4C)

d = 19RC


IN

OUT

12 C


10PUN

PDN

PUN

PDNP: 2N: 1 P: 2

N: 2P: 2N: 1 P: 4

N: 1

P: 2N: 3

P: 2N: 1

R/2 2C 6C

R/2

3C

d = (R/2)2C + (R/2 + R/2) (6C + 3C) = 10RC


IN

OUT

12 C


10PUN

PDN

PUN

PDNP: 2N: 1 P: 2

N: 2P: 2N: 1 P: 4

N: 1

P: 2N: 3

P: 2N: 1

R 3C 5C + 5C + 3C = 13C

d = 16RC


IN

OUT

12 C


10PUN

PDN

PUN

PDNP: 2N: 1 P: 2

N: 2P: 2N: 1 P: 4

N: 1

P: 2N: 3

P: 2N: 1

d = 18RC

R 6C 12C


Total Falling Output Delay

IN

OUT

12 C

10PUN

PDN

PUN

PDNP: 2N: 1 P: 2

N: 2P: 2N: 1 P: 4

N: 1

P: 2N: 3

P: 2N: 1

Tpdf = 19RC + 10RC + 16RC + 18RC = 63RC