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Registers
CPE 49
RMUTI
KOTAT
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Shift Registers
Capability to shift bits In one or both directions
Why?
Part of standard CPUinstruction set
Cheap multiplication
Serial communications
Just a chain of flip-flops
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Simple 4-Bit Shift Register
Clocked in common
Just serial in and serial out
Not quite a FIFO
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Serial In - Serial Out Shift Registers
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Serial In - Parallel Out Shift Registers
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Parallel In - Serial Out Shift Registers
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Parallel In - Parallel Out Shift Registers
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Bidirectional Shift Registers
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Shift Register Counters
Ring Counters
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Shift Register Counters
Johnson Counters
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Applications
To p roduce time delayThe ser ial in -ser ial ou t sh if t register can be us ed as a t ime delay
device. The amoun t of delay can be contro l led by:
- the num ber of stages in the register
- the clock frequ ency
To simpl i fy com binat ional logicThe ring counter techniq ue can be effect ively ut i l ized to implement
sync hrono us sequent ial c i rcu i ts . A major problem in the real ization of
sequent ial c i rcu i ts is the assignment of binary cod es to the internal
states of the circu i t in o rder to reduce the comp lexi ty of c i rcu i ts
required. By assig nin g one f l ip-f lop to one internal state, i t is po ssib le
to sim pl i fy the com binat ional logic required to realize the complete
sequent ial circuit . When the circu it is in a part icular state, the f l ip-f lop
co rrespon din g to th at state is set to HIGH and al l oth er f lip- f lops
remain LOW.
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Applications
To convert serial data to paral lel dataA com puter or m icroprocessor-based system
commonly requi res incom ing data to be in
paral lel form at. Bu t frequently, these systems
must commun icate w ith external devices that
send or receive serial data. So, serial-to -
paral lel conversion is requ ired. As shown inthe previous sections , a serial in - paral lel ou t
register can ach ieve this.
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Symbol
we could gate the clock
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Parallel Load
Can provide parallel outputs fromflip-flops
And also parallel inputs
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Schematic
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Why is this useful?
Basis for serial communications
Keyboard
Serial port Initially to connect to terminals
Now mainly for modem
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Bidirectional Shift Register
Shift either way
Now we have following possible
inputs Parallel load
Shift from left
Shift from right
Also no change
Schematic next
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Schematic
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Verilog for Shift Registermodule srg_4_r_v (CLK, RESET, SI, Q,SO);
input CLK, RESET, SI;output [3:0] Q;
output SO;
reg [3:0] Q;assign SO = Q[3];
always@(posedge CLK or posedge RESET)
begin
if (RESET)
Q
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Serial Transfer
Parallel transfer over as manywires as word (for example)
Serial transfer over a single wire Trade time for wires
Takes n times longer
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Example
Clocked 4 times
Why do this? Maybe
these are far apart
Could shift
data in
Whats on wire at each clock?
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Table Showing Shift
Hopefully weve figured it out
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Serial Addition
Shift value in serially
Then shift through
adder into A. Added
to 0 if A is empty.
At same time, new
value going into B
Adds one bit at a time
Stores carry one clock
Initially reset all
registers
Register A
accumulates
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Hardware Comparison
Serial vs. parallel adder
One full adder vs. n adders
Serial takes nunits of time, parallelonly one
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Arbitrary Count
One more type of counter is useful
Count an arbitrary sequence
Maybe you need a sequence of states
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Circuit and State Diagram
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Shift Registers
N-bit register with the provision for
shifting its stored data by a bit position
each tick of the clock.
Serial input specifies a new bit to
shifted into the register.
Serial output specifies the bits being
shifted out of the register
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References
http://www.eelab.usyd.edu.au/digital_tutorial/part2/hpage.html
http://
www.allaboutcircuits
.com
/vol_4
/index.html
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