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MIDTERM EXAM
1 Page Notes, 1 Text,1 Course Reader
The Midterm Exam is scheduledFriday, October 31, 2008
Time: 7:00-8:30
Location: Packard 101 andCISX Auditorium
EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 2
Midterm Review
Midterm--Fri, Oct. 31, 7-8:30, Pkrd 101 & CISX AudBand DiagramsFermi-Dirac and Boltzmann statistics, Fermi level
Donors and acceptorsFree carrier concentrations
Free Carrier MovementDrift, mobility, diffusion, diffusivityTransport equations and quasi-neutrality
Non-EquilibriumGeneration and recombination, Quasi-Fermi levelsContinuity equations and Poissons equation
P-N JunctionsDepletion approximationCharge, electric field and potential profilesI-V characteristics-Ideal diode, G-R currentsCapacitanceBreakdown voltage-avalanche and tunneling
Metal Contacts and Schottky Barrier Junctions
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EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 3
7-MOS CAPACITORSI. Band DiagramsMetal-Oxide-Silicon is the single most important component
for a large number of semiconductor devices.
The Al/SiO2/N-Si is a nearly ideal system with M=Sand is thereason that P-MOS devices developed before N-MOS devices
Si
MOS Structure
i=0.95 eV
Eg = 8 eV
= 4.05 eV SM = 4.1 eV
AluminumSilicon
Silicon Dioxide
EFEFEv
EC
EC
Ev
E0E0E0
EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 4
1)Bringing 3 materials into contact,EF = constant at thermalequilibrium just as in a Schottky contact or P-N diode.2) Currents through SiO2 are very small, a long time (decades) is
needed for equilibrium to be established. To realistically
establish equilibrium, an alternative conduction path must be
provided, e.g., the external circuit. This long storage time is the
foundation for flash memory.
Equilibrium Considerations
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EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 5
Bias Conditions for Ideal MOS Capacitor
M=
s
Name Flat Band Accumulation Depletion Inversion
EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 6
Equilibrium Flat BandBandstructure of Real MOS CapacitorM s
In this example, holes are at higher average energy in P-type Si than in metal(M
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EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 7
1. Equilibrium, Applied V = 01) Abrupt transition inEc andEv levels at material interfaces.
Ec = 2 - 1 and Ev = Eg2 - Eg1 - Ec2)A potential, VFB = (M- S), is dropped across the SiO2 plus the
depleted Si. The value depends onEF(s) in Si. This potential
can be supported because no current flows through SiO2.3)Substantial barriers exist for carriers flowing from S M and
from M S.4)Near the Si surface,EFis further fromEv than in bulk, the surface
is depleted of holes (DEPLETION).
Equilibrium in a Real MOS Capacitor
EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 8
2. Flat Band, Applied V = MS ( < 0 for the exampleshown)1)EFis constant in Si because SiO2 prevents any currentflowing (i.e., Si is at equilibrium).2) WhenEc andEv are flat, and the hole concentration isuniform in Si. = 0, electric field E = 0 in Si, E = 0 in SiO2(as indicated by flat Ec andEv).4) This is known as FLAT BAND, the voltage required toachieve this condition is VFB = MS= (M- S)
MOS Capacitor Flat Band Bias
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EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 9
Metal-SemiconductorWork Function Differences
N-type
P-type
The M-S work function difference is generally negative,requiring a negative gate voltage to reach flatband--What doesthis mean with respect to the electron or hole concentrations atthe surface?
EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 10
F
Potential and Surface Potential
(x)=1
qEi (bulk)Ei (x)[ ]
S=
1
qEi (bulk)Ei (surface)[ ]
[ ]FiF EbulkEq
= )(1
F=
kT
q ln
NA
ni
... p - type semiconductor
= kT
qln
NDni
...n - type semiconductor
where s is the surface potential, notthe semiconductor work-function, s
(positive)(negative)
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EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 11
3. Accumulation, Applied V < VFB
(more negative)
P-type bulk
EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 12
1)EF is still constant in Si.2)EF is closer toEv at the surface. There are more holesaccumulated at the surface than in the bulk (ACCUMULATION).
The solution to the hole distribution at the surface is similar to
that for a Schottky Ohmic contact from Chapter 6 on "Metal
Semiconductor Contacts". The Debye lengthLD, is about the
same as or thinner than the typical SiO2 thickness. The holes can
be approximated as a thin sheet of charge at the Si surface. The
situation is similar to that of a parallel plate capacitor.
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EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 13
4. Depletion, Applied V > VFB
P-type bulk
EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 14
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EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 15
The situation is similar to that of a Schottky contact under a
reverse bias except that some of the voltage will be droppedacross the SiO2. Assume a uniform NA and that the surface is
depleted of holes (DEPLETION). From Poisson's Equation,
By integrating the above equation, the electric field and thepotential in the depletion region are:
(1) (2)
00
2
2
s
A
s K
qN
Kdx
d
dx
d===
( ) ( ) ( )WxxWK
qNx
os
A= 0
E
E
x( ) =qNA
2KsoWx( )
20 x W( )
EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 16
From Gauss's Law, the electric displacement must be constant
across the Si/SiO2 interface
where o and s are dielectric constants of SiO2 and Si,respectively and Eox and Es are electric fields in SiO2 and Si,respectively. This is the source behind the huge efforts todayto produce a high o dielectrics such that the electric field,which controls the surface charge density, will be muchhigher in Si for the thicker insulator required to blocktunneling.
Ko ox = Ks sE E
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EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 17
(3, 4)
(5)Wcan be solved for known V,NA, andxo.
oo
Aox
K
WqN
=
oo
oAooxox
K
WxqNxV
==V =VFB +Vox +s
os
A
oo
oAFB
K
WqN
K
WxqNVV
2
2
++=
os
As
K
WqN
=
os
As
K
WqN
2
2
=E
E E
EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 18
5. Inversion, Applied V >> VFBP-type bulk
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EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 19
Unlike Schottky contacts,EFcan be defined and is constant in the Si,
even with bias because the insulator blocks all current flow. Ifs =F, the surface will become intrinsic. For F< s < 2 F, the surface
becomes lightly n-type (WEAK INVERSION). For s > 2 F, the
surface will have an electron concentration higher than the acceptor
(or hole) concentration in the bulk (STRONG INVERSION).Since
ns = nie
q
kTsF( )
EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 20
for s > 2F, the electrons at the surface will become the
dominant charge. Their distribution will be similar to that ofholes under accumulation and can be approximated by a sheet
of electrons at the Si surface.s = 2Fis defined as the onset of strong inversion. Beyond
this point, the depletion width remains approximately the
same. From equation (2)
os
TAF
K
WqN
22
2
=
A
FosT
qN
KW
4= (6)
Fis positive for p-type materialnegative for n-type (i.e. sign ofq changes)
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EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 21
The voltage required to reach the start of inversion from Eq.
(5) is called the threshold voltage, VT
VT =VFB +Vox +s
VT =VFB xo
Koo4KsoqNAF + 2F
=VFB 1
Cox4KsoqNAF + 2F (7)
Fis positive for p-type material and negative for n-type
and sign is positive for p-type and negative for n-type
EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 22
Charge Distribution and Potential
Once inversion is reached,very little additionalpotential drops across thesemiconductor because asmall change in the surfacepotential increases thesurface electronconcentration immensely.
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EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 23
1. Accumulation
(8)
P - Si
-
Cox
C
Cox
+ V
++++++++++
o
oo
o
x
KCC
=
II. C-V Characteristics
Capacitance is constant with Vbecause in accumulation, the mobilecarriers can follow the AC signal.
where indicates capacitance per unit area
EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 24
2. Flat Band
At VFB there is no charge in the device, but when a small ACvoltage is applied, there will be charge that appears on theaverage a Debye length from the surface. In other words, theaverage charge will not appear right underneath the oxide, butat a Debye length away from the oxide. This semiconductorcapacitance results from the movement of majority carriers,so can occur very rapidly. The capacitance at VFB is acombination of oxide capacitance Co and Si capacitance CS.
V
P - Si
-C
CFB
+
+ + + + ++ + +
Cox
Cs
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EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 25
(9)
In reality, CSis present during accumulation also. However,when there are lots of carriers, Debye length decreases, so CS
will increase to infinity, which would cause Cto be equal toCoonly.
1
11
+
=so CC
C
1
+=
os
D
oo
o
K
L
K
x
A
sD
Nq
kTKL
2
0
=
where,
EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 26
(10)
Cox
C
+
Cd
V
P - Si
Ionizedacceptor
atoms
+
- - - - -- - - - -h
11
11
+=
+
=
osoo
o
doK
W
K
x
CCC
3. Depletion
The only charge carriers that can followthe AC signal are at the back edge of thedepletion region in the semiconductor.
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EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 27
Three types of response-Low frequency and high frequency
with slow DC sweep and rapid DC sweepSlow D.C. sweep, low frequency A.C. signal (f < 1 Hz),
inversion layer (next to oxide is modulated at AC frequency.
(12)
P - Si
Cox
C
+
Cd
+ +
- - - -- - - -h
InversionLayer
Vmin
Xdmax
e
Cox
Cmin
Low freq.
High freq.
o
oo
o
x
KCC
=
4. Inversion
W
EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 28
Slow D.C. sweep, high frequency AC signal (f > 1 KHz), mobile
carriers at the back edge of the depletion region are modulatedbecause the generation recombination processes cant keep up with
the A.C. signal
(11)Fast DC sweep, high frequency AC signal, the generation process is
too slow to keep up with the change in the DC gate bias. The
capacitor goes into deep depletion and equation(10) continues to bevalid. Eventually the generation process supplies carriers to theinversion layer and the capacitance returns to the normal high
frequency value.
11
min
min
11
+=
+
=
osoo
o
doK
W
K
x
CCC
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EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 29
Surface Potential vs. Gate Bias
The surface potential changesvery little in accumulation orinversion as it takes very littlechange in the surface Fermilevel to increase the hole orelectron concentrations veryrapidly, while in depletion,there is very little surfacecharge independent of thevalue of the surface potential.
Lightly doped Si.In heavily doped Si, thechange in s is ~ 40 kT/q
EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 30
MOS C-V Characteristic (P-type Si)
The C-V characteristic for N-type Si is a mirror image of the
characteristic above. Note that while the dip in the lowfrequency curve looks somewhat symmetrical, it is alwayssteeper on the inversion side than on the depletion side becauseof the small change in surface potential required to increase thesurface charge.
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EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 31
The total charge in the accumulation layer, depletion region, or
inversion layer can be estimated by graphical integration.Q = C V( ) dV
EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 32
Flatband Shift due to
Work Function Difference
MSGV =
There will be a shift in the C-V curve from the ideal curve dueto the differences in the metal-semiconductor work functions.
This is generally negative because for most combinations, S >M. This is a problem for N-channel MOSFETs because theinversion channel has formed at zero gate voltage.
p-type MOScapacitor
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EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 33
Effect of Flatband Shift
Negative
MS shifts the C-V curve in the negative direction,which at zero bias results in,1. Inversion layer in p-type material (N-MOS), whichproduces a channel at zero bias--normally ON2. Accumulation layer in n-type material (P-MOS), whichproduces a strong blocking channel at zero bias--normallyOFF
The consequences of this were the initial development of P-MOS
rather than N-MOS, even though mobility favored N-MOS.(There were additional technological problems (positive charge inthe oxide) that favored P-MOS as well)
EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 34
III. Oxide and Interface Charges
Four types of charge:Interface charge, QIT, Fixed oxide charge, QF,Trapped oxide charge, QOTand mobile ion charge, QM
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EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 35
Types and origins of charge:1. Interface trapped-charge, QIT. Due to unterminated Si bonds atthe SiO2/Si interface, on the order of 1010cm-2.2. Fixed interface charge, QF. Believed to be due to uncompensated
silicon-silicon bonds in the SiO2, on the order of 1010 cm-23. Oxide trapped-charge, QOT. Due to defects in the SiO2 network,
usually negligible in today's MOS devices. Can be generatedafter a large amount of charges have passed through the SiO2 andbroken up the network.
4. Mobile charge QM. Due to alkaline ions (e.g., Na+, K+), usuallyvery low concentration ( 10
9
cm-2
) in today's technology.
EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 36
Effects on C-V characteristics:1. Fixed Charge (QF) For finite QFat the interfacethe flat-band voltage VFB will bedifferent from the theoretical value. This will cause a shiftin the C-V curves. By measuring the complete C-V curvesand comparing them with the ideal curves the shift will givethe value ofQF.
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EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 37
C
+ V
ExperimentalIdeal
VFB
= ---Qf
Cox
o
FMS
oo
oFMSFB
C
Q
K
xQV
'==
FFAsoo
o
oo
oF
MST qNK
x
K
xQ
V 24 ++=
VVcmQx FBFo 5.010A1000For211
===
EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 38
2. Oxide trapped-charge,QOTFor an arbitrary distribution of trapped-charge, QOT within
the oxide
( )
( )
( ) dxxx
xQCC
Q
dxx
xx
K
x
xdxxK
V
o
x
oOT
oo
F
x
oooo
o
x
o
FB
o
o
o
=
=
=
1
1
00
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EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 39
3. Mobile Charge (QM) By bias-temperature stress, QMcan be moved from the SiO2-Si interface to the metal-SiO2 interface. The wafer is heated at~300C and a small positive or negative gate bias, VG of 5-10V, is applied to move the mobile charge to the M-O interface(neg to gate) or to the O-S interface (pos to gate). The shiftin VFB indicates that there is mobile charge and the magnitudeof the shift can be used to estimate QM.
EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 40
P - Si
C
+ V
++++++++
P - Si
++++++++
+V
-V
VFB
For 1000 SiO2 1ppm NA+ (1016 cm-3) QM= 1011 /cm2, VFB = 0.5Vwithout great care, it is easy to have >1013 ions,VFB > 100V!!!
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EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 41
4. Interface Traps (QIT)
EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 42
Interface Traps (QIT)
Interface traps are very similar to the traps in a Schottky diodewhich pin the Fermi level at mid-gap, these interface traps haveenergy levels distributed in the band gap. The charge state ofthe traps depends on the Fermi level. Hence, as the surfacepotential is swept from flat band towards depletion, the trapswill try to pin the surface potential, i.e, it will take more gatevoltage to move the surface potential through the traps.
Acceptor likeDonor like
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EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 43
Effect of QF and QIT on C-V Characteristics
Interface traps cause a non-uniform shift in VG because theircharge state (QIT) is changing with bias and position of thesurface Fermi level
Effect of QIT
Effect of QF
EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 44
QITcan be estimated by comparing the difference between the
high-frequency C-V (when the traps cannot keep up with thehigh frequency AC signal) and the low-frequency C-V. Inpractice a slowly varying ramp is applied to the MOS capacitorand the resulting current is measured. For an ideal capacitor thecapacitance is,
If there were no interface traps C should be constant and thusthe currentI(t) should be constant. However, if there are trapspresent they can trap or release the charges as the capacitor
goes from accumulation to inversion. This generation -recombination current caused by the interface traps will changethe capacitance.
C=dQ
dV=
dQ
d Kt( )=
dQ / dt
K=
I t( )
K
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EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 45
a measure ofI(NIT) can give the value ofNIT
Effect of Surface Potential on p-n Diode CharacteristicsBreakdown voltage (VBR) is limited by junction curvatureReverse saturation currentIo depends on recombination in thedepletion regionIdeal Diode
( )( ) ( )
K
NItItC
IT+
=
EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 46
Diode with charges in the OxideCharges in the oxide change the surface potential. This leads
to changes in diode properties.
VBR increases because depletion layer width at the surface
increases leading to decrease in Efield.Io increases due to
increased surface recombination.
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EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 47
VBR decreases because depletion layer width at the surface
decreases leading to increase in Efield.Io decreases due to
reduced surface recombination.
EE 216 Principles and Models of Semiconductor Devices (Autumn 2008) Prof. J. S. Harris 48
Gated Diode
Both VBR andIo can be modulated in a controlled fashion by
controlling the surface potential at the edges of the diode by
applying a gate voltage, VG
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