D. Henry
CEA-Leti-Minatec
3D Integration developments & manufacturing offer @ CEA-LETI
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Eufanet 3D Workshop – D.Henry | 2
Introduction
3D Integration R&D activities overview
3D integration Manufacturing offer : Open 3D™ platform
Concept
Technological offer
Means & facilities
Conclusions / prospects
Outline
Introduction
3D Integration R&D activities overview
3D integration Manufacturing offer : Open 3D™ platform
Concept
Technological offer
Means & facilities
Conclusions / prospects
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Eufanet 3D Workshop – D.Henry | 3
CEA | The CEA at a glance – LETI at a glance
is one of the largest research organizations in Europe, focused on energy, health, information technologies, and national defense
10
16,037 People (10% PhD and Post Doc)
Research centers
Commissariat à l’Énergie Atomique et aux Énergies Alternatives
CEO Dr. Laurent Malier
Founded in 1967 as part of CEA
1,700 researchers
40 start-ups & 265 industrial partners
Over 1,700 patents
210 M€ budget190 PhD students + 34 post PhDwith 70 foreign students (30%)
~ 40M€ CapEx
265 generated in 2010 40% under license
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In electronics, a 3D integrated circuit is a chip in which two or more layers of active electronic components are integrated vertically into a single circuit, component or system.
Introduction : What is 3D Integration ?
3D Integration key drivers : Form factor decrease Performances improvement Heterogeneous integration Cost decrease
Interposer / substrate
Logic
Memorypassives
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Eufanet 3D Workshop – D.Henry | 5
3D name
Interconnect level
Supply chain
Key Techno approaches
Schematic view
Pad size (µm)
WL pack. CieOSATIDM
3D WLP (wafer level packaging)
Bond pad
C2W /TSV last / Interconnections
10 - 60
IDMFoundries
3D SIC (Stacked IC)
Global / Intermediate
C2W / W2WTSV last & first/ Direct bonding
1 - 15
IDMFoundries
3D Monolithic (or 3D IC)
Local
Low temp IC
10-2 - 1
OSATPackaging
subcon.
3D SiP or 3D packaging
Package
PoP / SiP / C2CWire bond / FC
> 60
Introduction : 3D Integration hierarchy
4 different worlds in 3D Integration :
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Main actors of 3D Integration / Geo mapping
Source : Yole developement
3 main areas : North America Europe Far east
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Introduction
3D Integration R&D activities overview
3D integration Manufacturing offer : Open 3D™ platform
Concept
Technological offer
Means & facilities
Conclusions / prospects
Outline
Introduction
3D Integration R&D activities overview
3D integration Manufacturing offer : Open 3D™ platform
Concept
Technological offer
Means & facilities
Conclusions / prospects
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Eufanet 3D Workshop – D.Henry | 8
3D Integration @ LETI : 3 research axes
3D Packaging evolution: Si Interposer
3D IC evolution
Fill the gap between advanced IC and Plastic Integrate “heavy” functions as near as possible from IC (Passives, Thermal management,…)
Solve memory logic bandwidth equation Mix different nodes to reduce the cost Compensate Moore law’s difficulties
Substrate evolution Advanced SOI substrates for More Moore More than silicon: Add new materials compatible with silicon technologies
Design (r)evolution
Design (r)evolution
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Eufanet 3D Workshop – D.Henry | 9
3D Integration @ LETI : 3 research axes
3D Packaging evolution: Si Interposer
3D IC evolution
Fill the gap between advanced IC and Plastic Integrate “heavy” functions as near as possible from IC (Passives, Thermal management,…)
Solve memory logic bandwidth equation Mix different nodes to reduce the cost Compensate Moore law’s difficulties
Substrate evolution Advanced SOI substrates for More Moore More than silicon: Add new materials compatible with silicon technologies
Design (r)evolution
Design (r)evolution
A common generic toolbox
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Eufanet 3D Workshop – D.Henry | 10
Thermo mechanical & thermal Modeling
Electrical ModelingMod
elin
g
C EA-Leti
R
L
GSi
COxCSi
GSi
COxCSi
Tech
nolo
gica
l m
odul
es
Thinning & Handling
Face to Face connections
Through Silicon Via (TSV)
Redistribution layers and Board connections
Components placement (WTW or CTW)
Layout & masks
Des
ign
layo
ut
Standard Design rules manuel & Design kitCh 1
5x5 router
Ch1 NorthCh1 SouthCh1 EastCh1 West
Ch1 NorthCh1 South
Ch1 EastCh1 West
Ch 05x5 router
Ch0 NorthCh0 SouthCh0 EastCh0 West
Ch0 NorthCh0 South
Ch0 EastCh0 West
Ch1 3D/Res
Ch0 3D/ Res
Ch1 3D/Res
Ch0 3D/Res
3D implementation & partitionningARM1176
CORE
WIFLEX
AS IP
UWB-LDPC
NoCnode
SME MephistoTRX
OFDM
ARM117 6
+
SM E
unit
RX-B IT+
HARQ
TR XOFDM
TRXOFD M
TRXOFDM
Mephisto M ephisto
Meph isto SME
SM E
TX-BIT+
NoC perf
Mephisto
SMEEXT SME
80C51
GALSadapter
LETI toolbox for 3D IntegrationIn
dust
. /
Mfg
Cost analysis
Test strategy
ReliabilityKelvin 5µm
0
20
40
60
80
100
0 0,1 0,2 0,3 0,4 0,5Resistance [W ]
%
09-Ref
10-Ref
11-Ref
12-Ref
13-Ref
14-Ref
15-SLE
16-SLE
17-SLE
Today’s presentation focus
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Eufanet 3D Workshop – D.Henry | 11
Toolbox : Temporary bonding / Thinning/handling
Device Temporary bonding 3D techno Debonding / handling / Stacking
Process flow summary
EVG 560 bonder Wafer bonded with temp. glue
Source : A. Jouve / Brewer Science / 3D IC 2009
Debonder EVG 805Debonded wafer (70 µm)
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Classic Flip chip (Ball or stud bump)
Pitch
Solder-free µ-inserts
Cu pillars
Cu-Cu Direct bonding
Si
Si
Cu
SiO2
Si
Si
Cu
SiO2
µtubes
> 100 µm 100-30 µm range Down to 5 µm30-10 µm range
Toolbox: Face to Face connection
Well-established process
Disruptive concepts
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Toolbox : TSV
TSV First (Polysilicon filled)
Trench AR 20, 5x100µm
TSV Middle (Copper or W filled)
AR 7 , 2 x 15µm AR 10, 10x100µm W filled
TSV Last (Copper liner or filled)
AR 1 80x80µm AR 2, 60x120µm
SiO2 flanc
métal RDL
BCB
bulle air sous BCB
60µm
AR 3, 40x120µm AR 7 , 2 x 15µm
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3D Integration : applications examples
3D Packaging evolution
3D IC evolution
Fill the gap between advanced IC and Plastic Integrate “heavy” functions as near as possible from IC (Passives, Thermal management,…)
Solve memory logic bandwidth equation Mix different nodes to reduce the cost Compensate Moore law’s difficulties
Substrate evolution Advanced SOI substrates for More Moore More than silicon: Add new materials compatible with silicon technologies
Design (r)evolution
Design (r)evolution
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Eufanet 3D Workshop – D.Henry | 15
Leti Interposer Technology
Die to Die Copper pillar
Die to substrate copper pillars
Thinned wafer (120 µm)
Via Last TSV (Aspect Ratio 2-3) Via Last Via Mid
or
Top Die
Silicon Interposer
Cu Pillars
TSV
Substrate
Component partitioning Advanced technology top die Mature technology Bottom die
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High Density Interposer Advanced components top dies High density routing
Metal line
Micro bump
Metal line + via
Top metal lineDebonded wafer on tape
Seed layer deposition
Leti Interposer Technology
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3D Integration : applications examples
3D Packaging evolution
3D IC evolution
Fill the gap between advanced IC and Plastic Integrate “heavy” functions as near as possible from IC (Passives, Thermal management,…)
Solve memory logic bandwidth equation Mix different nodes to reduce the cost Compensate Moore law’s difficulties
Substrate evolution Advanced SOI substrates for More Moore More than silicon: Add new materials compatible with silicon technologies
Design (r)evolution
Design (r)evolution
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Eufanet 3D Workshop – D.Henry | 18
Cmos on Cmos Integration
TSV’s Via Middle, Ø10µm x 80µm, 40µm pitch.
Cu Pillars 25µm wide, 30µm high
3D Partitioning demonstration Analogue/ Digital partitioning 65nm node, 7 metal layers + TSV 80µm
0,0 0,5 1,0 1,5 2,0 2,5 3,0
0
20
40
60
80
100
Pou
rcen
tage
cum
ulé
(%)
R ()
P01_2TSV P02_2TSV P01_10TSV P02_10TSV P01_50TSV P02_50TSV
Cumulated resistance of a 2, 10 & 50 TSV daisy chains
1st wafer 80% yield
Digital 65nm
Analogue
Cu Pillars
TSV
VFBGA, 4x4mm
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Eufanet 3D Workshop – D.Henry | 19
60µm
60µm
Substrate Die
Top Die
Bottom Die
Bottom Die
60µm
Copper PillarsVia middle
12µm
Multi-Stacking, N>2
NAND Flash Memories Via middle: ~Ø12µm x 60µm Cu pillar interconnections
Mem4
Mem3
Mem2
Mem1
Multi-partner project
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Eufanet 3D Workshop – D.Henry | 20
Introduction
3D Integration R&D activities overview
3D integration Manufacturing offer : Open 3D™ platform
Concept
Technological offer
Means & facilities
Conclusions / prospects
Outline
Introduction
3D Integration R&D activities overview
3D integration Manufacturing offer : Open 3D™ platform
Concept
Technological offer
Means & facilities
Conclusions / prospects
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Eufanet 3D Workshop – D.Henry | 21
The concept : Open 3D™ is a 3D technology offer, targeting industrial & academic customers Open 3D™ will give access to 3D innovative technologies with the following key
drivers : Cost effective technologies : Based on mature technologies Customization upon request Short cycle time Global offer including design, technology, tests & packaging Proof of concept (small quantity of wafers) or small volume production
Introduction to Open 3D™ Platform
Means & Facilities : Open 3D™ will operate on CEA-LETI technological platforms : 200 & 300 mm Support by LETI skills on layout, process, metrology, charac., tests & reliability
Open 3D customer’s typology : Laboratories, universities and international Institutions Fabless / “Niche” markets manufacturers & integrators IDM
Projects already started with :
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Passivation
RDL
Bottom dieor interposer
Top die
Pillars
Substrate or BGA or package
TSV
Front sideUBM
Back side UBM
Bumps
Micro-bumps
Micro pillars
Technological offer overview
Technological modules definitions : Through Silicon via (TSV) Redistribution layer (RDL) UBM
Interconnections Components stacking Packaging with partner collaboration
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Eufanet 3D Workshop – D.Henry | 23
Technological offer overviewDesign & Layout
3D Technology
TSV
Interconnections
Components stacking
MetalizationElectrical Tests
0,00%
10,00%
20,00%
30,00%
40,00%
50,00%
60,00%
70,00%
80,00%
90,00%
100,00%
0,00 0,50 1,00 1,50 2,00 2,50 3,00 3,50 4,00
P02P03P05P06P07P08P09P10P11P12
Open 3D™ TechBox
As a Lego™ approach
Contact : [email protected]
Packaging
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Technological offer in details : 3D design & layout
Complete Design Rules Manual (DRM) Implementation of customer design 3D Design kit (DK) Layout capabilities / Verifications
Cadence Virtuoso tool Mentor graphics Calibre tool
Mask generation
0pen 3D design approach
3D DRM & DK
TechnoLéti
DRML éti
TechnoCustomer
DRMCustomer
Design
Open 3D PDK Generator
Customer
PDKLéti
PDKCustomer
Design rules for Micro-bumps & RDL
Layout & verifications
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Technological offer in details : TSV + RDL
Wafer size : 200 & 300 mm TSV type : via last / Cu liner Minimum pitch : 80 µm TSV diameter : 30 to 100 µm Aspect Ratio (AR) : from 1:1 to 3:1
RDL material : Cu / protective layer possible RDL thickness : 1-10 µm RDL minimun width : 20 µm RDL minimun space : 20 µm
Customer Top passivation
TSV Metal liner
Customer Top metal
TSV Dielectric liner
Customer Metal 1
RDL
Backside Passivation
CMOS
Bulk contact
Backside UBM
Wafer 1
TSV & RDL DRM & schematic
AR 1:1AR 3:1
TSV & RDL morphological results
AR 2:1 Cu RDL integration : pillars on RDL + passivation
Solder bump
RDL
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TSV diameter 30 µm 40 µm 50 µm 60 µm
AR 1:1 & 1.5:1
AR 2:1
AR 3:1
Available
Not yet required
Available
Not yet required
Not yet demonstrated
Not yet demonstrated
Not yet demonstrated
Technological offer in details : TSV gallery
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Technological offer in details : Under bump metallurgy (UBM)
UBM DRM & schematic
UBM morphological results
AR 2:1
Wafer size : 200 & 300 mm UBM material : TiNiAu Possible on frontside and / or backside of the components UBM thickness : 0.5 – 1.5 µm UBM width : 20 – 800 µm UBM minimun pitch : 40 µm
Customer Top metal
Customer Top passivation
Frontside ubm
CMOS
Wafer 1/ Bot. die
Customer Top passivation
CMOS Customer Top metal
Backside ubm
Wafer 2/ Top die
Different shape possible :
- Square
- Polygons
- Circle
Available technology :
- Metal sputtering / thickness range : 0.5 – 1.5 µm
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Technological offer in details : Micro bumps & micro pillars
Micro bumps & micro pillars DRM & schematic
Micro bumps & micro pillars morphological results
Customer Top metal
Customer Top passivation
Cu stud
Protective layer
Micro pillar
CMOS
Wafer 1/ Bot. die
Wafer size : 200 & 300 mm Micro-bumps material : Cu post / SnAg solder Micro pillar material : Cu post / NiAu protection possible Minimum pitch : 50 µm Micro-bumps diameter : 25 µm Micro pillars diameter : 25 µm Micro-bumps thickness : 25 – 35 µm Micro pillars thickness : 8 – 12 µm
Micro-bumps after reflow
Micro-bumps characterization
Micro pillars with protective layer
Micro pillars on top metal
CMOS
Customer Top metal
Cu studSolder alloyMicro bump
Wafer 2/ Top die
Top passivation
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Technological offer in details : bumps & pillars
Bumps & pillars DRM & schematic
Bumps & pillars morphological results
TSV
Customer Metal 1
RDL
Backside Passivation
Cu stud
Solder alloy
CMOS
Bumps
Customer Top metal
Wafer size : 200 & 300 mm Pillars material : Cu stud / SnAg solder Minimum pitch : 120 µm Pillars diameter : 60 – 80 µm Pillars thickness : 60 – 80 µm
Bumps
Bumps cross section
Pillars integration with TSV
Solder bump
TSV
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Eufanet 3D Workshop – D.Henry | 30
Technological offer in details : 3D electrical tests
Electrical tests at each level Specific structures for 3D technologies Non invasive structures into dicing lines Using of Standard probe cards Data exploitation tool
Electrical test results & tools
Electrical test approach
0,00%
10,00%
20,00%
30,00%
40,00%
50,00%
60,00%
70,00%
80,00%
90,00%
100,00%
0,00 0,50 1,00 1,50 2,00 2,50 3,00 3,50 4,00
P02P03P05P06P07P08P09P10P11P12
3D tests structures
Electrical test tool
Probe cardElectrical test
results
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Eufanet 3D Workshop – D.Henry | 31
Introduction
3D Integration R&D activities overview
3D integration Manufacturing offer : Open 3D™ platform
Concept
Technological offer
Means & facilities
Conclusions / prospects
Outline
Introduction
3D Integration R&D activities overview
3D integration Manufacturing offer : Open 3D™ platform
Concept
Technological offer
Means & facilities
Conclusions / prospects
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Eufanet 3D Workshop – D.Henry | 32
MEMS 200Microtech for biology
CMOS 200 mm
Nanotech 300 + 3D 300
Design / layout
Nanoscale Characterization
B2i / applications building
Photonics
Open 3D™ platforms
Technological platforms @ Minatec campus General overview of LETI’s platforms @ MINATEC campus
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MEMS 200 tools
Litho cluster
In line Metrology
Metal etchingCleaning
Raider ECD
Stripping / Cleaning
Dry Metal etching
Metal deposition
Litho
CMP
Litho
Litho
Cleanrooms
MEMS 200 buildings & facilities
Cleanrooms
Mobile cleanroom between platforms
MEMS 200
Pilot Line
MEMS 200 pilot line
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Wet etch
ECD 2
Vacuum laminator
Reflow
Pick & place
Balling / Screen print.
Cleaning / deconta
ECD 1Grinding
Edge grinding
3D 300 future installation toolsComplete line for Q1 2012
Dry film laminator
Mask Aligner
Coater
Bonder
Stripping
Diel. Deposition
Metal deposition
3D 300 installed base
Deep etchnig
3D 300
Pilot Line
New 3D 300 pilot line (fully operationnal 2012)
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Eufanet 3D Workshop – D.Henry | 35
Conclusions / Prospects
Conclusions : Since 20 years, LETI has worked on 3D integration An original approach, based on a technological toolbox, has been developed Industrial transfers & technological demonstrations have been achieved since
few years Now, a new platform, Open 3D™, is proposed by LETI for academic &
industrial partners with the following key drivers : Cost effective / mature technologies Short cycle time Global offer including design, technology, test & packaging Operations on LETI facilities @ Minatec campus / Grenoble – France Proof of concept or small volume Already two projects have started on the platform
3D integration prospects : To continue the R&D projects in order to develop disruptive 3D technologies To continue to fill the Open 3D catalog with mature technologies in
accordance with our customer needs
Thank you for your attention
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