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MB8AA3020
20-port, 10GbE Switch Chip
Chip Specification
MB8AA3020
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Fujitsu Microelectronics America, Inc.
Confidential
Revision: 2.4
Last Updated: July, 2007
Document #: 10GE-RM-21246-6/2007
Copyright © 2001, 2002, 2003, 2004, 2005, 20062007 Fujitsu Laboratories of America, Inc. All rights reserved.
This document contains confidential information and trade secrets of Fujitsu Laboratories of America, Inc. which shall not be reproduced or transferred to other documents or disclosed to others or used for manufacturing or any other purpose without prior written permission of Fujitsu Laboratories of America, Inc. Use of copyright notice is precautionary and does not imply publication or intent thereof.
All information contained in this document is subject to change without notice. While the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness.
Chip Specification
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Table of Contents
1. Introduction.....................................................................................................................................................................1
1.1 General Description .................................................................................................................................................11.2 Features..................................................................................................................................................................1
2. Functional Description......................................................................................................................................................2
2.1 Frame Format .........................................................................................................................................................22.2 Input Port...............................................................................................................................................................22.3 Central Switching Structure ......................................................................................................................................32.4 Output Port ............................................................................................................................................................82.5 On-chip Code ..........................................................................................................................................................92.6 I2C Interface .........................................................................................................................................................102.7 Initialization .........................................................................................................................................................13
3. Network Management .....................................................................................................................................................15
3.1 Introduction..........................................................................................................................................................153.2 Management Information Base (MIB) Counters..........................................................................................................15
4.
Error Handling .............................................................................................................................................................19
4.1 Introduction..........................................................................................................................................................194.2 Input Errors..........................................................................................................................................................194.3 Bridge Errors ........................................................................................................................................................204.4 Output Errors .......................................................................................................................................................204.5 Hardware Errors....................................................................................................................................................20
5. IO Signals ......................................................................................................................................................................21
5.1 External Pins ........................................................................................................................................................21
6. Mechanical Description....................................................................................................................................................25
6.1 Dimensions ...........................................................................................................................................................256.2 Pin Organization ...................................................................................................................................................266.3 Pin Listing............................................................................................................................................................27
7. Electrical Description ......................................................................................................................................................35
7.1 Absolute Maximum Ratings.....................................................................................................................................357.2 Recommended Operating Conditions ........................................................................................................................357.3 ESD Ratings .........................................................................................................................................................357.4 Reference Clock Input (LVDS) Electrical Specifications ...............................................................................................367.5 2.5V CMOS IO Electrical Specifications ....................................................................................................................367.6 HSIO Electrical Specifications..................................................................................................................................397.7 Power Dissipation ..................................................................................................................................................407.8 Reset Sequence.......................................................................................................................................................40
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Chip Specification
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1. Introduction
1.1 General Description
This specification describes the 4th generation Fujitsu 10Gbps Ethernet switch chip, AXEL-X MB8AA3020. This chip supports twenty 10Gigabit ports which operate at wire speed with high speed IO (HSIO) interfaces. The HSIO interface supports XAUI (802.3ae) and 10GBASE-CX4 (802.3ak). It also supports 10G serial operation to directly connect the XFP device. The switch chip has a large shared packet memory using Stream memory technology. The memory realizes multi-port memory using conventional high-density memories as a solution for the memory bandwidth bottleneck in a shared memory switch and provides enough bandwidth required for a high performance switch. The switch chip supports congestion management, logical partitioning, and two 1Gigabit ports for easier and superior system design with significantly reduced cost. This chip also has several features such as Jumbo frame support, cut-through and priority queues to achieve higher performance in cluster applications.
1.2 Features
The switch chip has following features:
• Twenty 10Gigabit ports switching operation at wire speed and two 1Gigabit ports
• 400Gbps+ aggregate throughput
• Integrated SerDes
• Support XAUI,10GBASE-CX4, and 10G serial
• On-chip Multi-port Stream Memory and buffer management
• Cut-through, Priority queues and Jumbo Frame support for high-performance cluster
• Jumbo frame (Max. 16KB)
• up to 8 Priority queues
• Pin-to-pin switching latency of 300nS (including SerDes)
• Extended VLAN (up to 64) for Logical Partitioning
• Priority PAUSE
• Backward Congestion Notification Support
• Link aggregation (802.3 clause 43)
• IGMP and MLD snooping
• DiffServ for IPv4 and IPv6
• Deficit Round Robin (DRR) for fair bandwidth sharing
• Shaper (CIR: Committed Information Rate)
• Meter (PIR: Peak Information Rate)
• Port Security (Filtering based on Source MAC address)
• Early Detection to avoid blocking
• WAN PHY support
• Multiple chip configuration for cluster application
• L2 unicast forwarding, address learning and aging
• L2 lookup table with 16K MAC address
• Shared VLAN Learning (SVL) and Independent VLAN Learning (IVL)
• Less MAC Table consumption for IVL
• 802.1Q VLAN
• VLAN table with 4K VLAN address
• User-programmable VLAN Tag Protocol Type
• 802.1Q(802.1s) Multiple Spanning Tree
• 802.3ae Full-duplex operation using PAUSE flow control
• RMON and SMON statistics counters
• sFlow (RFC3176) support
• EEPROM Interface for initialization
• I2C Master Interface for XFP Register Access
• Ethernet Interface for housekeeping
• External NP support
• Port mirroring and VLAN mirroring
• 90nm CMOS Technology
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2. Functional Description
2.1 Frame Format
The switch chip supports standard Ethernet frames with lengths between 64bytes to 1518bytes (no VLAN), 1522bytes (VLAN) or 1526bytes (User/Extended VLAN Tag) and Jumbo frames with 16Kbytes. The frames less than 64bytes and longer than 16Kbytes are dropped at the input port. The minimum IPG is assumed to be 96bit IDLE plus 64bit preamble. The packets with shorter IPG are not dropped but the wire speed switching is not guaranteed.
2.2 Input Port
Each input port consists of the High speed IO Receiver, Media Access Control (MAC) Receiver and Input Control blocks as shown in Figure 1. The High speed IO Receiver performs following functions:
• Physical Interface to XAUI / 10GBASE-CX4 / 10G Serial (PHY)
• Receiver equalization
• Deserialization
• Comma Align, 8B/10B Decoder, Lane Deskew
• XGMII Interface to Media Access Control
Figure 1: Input Port
High speed IO Media Access Control(MAC) Receiver block
Input Control Block
Input Buffer
HSIO XGMII Proprietary Interface
HSIO: High Speed IO InterfaceXGMII: 10Gbit Media Independent Interface
Receiver block
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The MAC Receiver performs following IEEE 802.3ae compliant functions:
• XGMII Interface to the High speed block
• Receive PAUSE flow control packet and request the MAC Transmitter to stop sending a new packet
• Frame Check Sequence validation
• Station MAC address matching to detect a management packet designating the switch
• Statistics counters for network management
• Link fault detection
The Input Control performs protocol dependent and independent functions:
Protocol Dependent Functions
• Simple proprietary interface to the MAC Receiver
• Filtering frames based on the Acceptable Frame Type
• Assign the priority based on TOS field (IPv4) / Traffic Class (IPv6) field in the packet.
• Storing the packet temporarily into the Input Buffer
• Request to generate PAUSE flow control packet to the MAC Transmitter if necessary
Protocol Independent Functions
• Maintaining the credit for the flow control between the Stream Memory and the Input Control
• Maintaining the free list of the blocks which are assigned to the port
• Checking the credit and store the packet data into the Stream Memory based on the free list.
• Generating a forwarding request to the Central Agent for routing.
2.3 Central Switching Structure
Figure 2 shows the central switching structure for packet buffering and switching. The structure consists of the Multi-port Stream Memory, TAG Memory and the Central Agent. The packet data is stored in the Stream Memory by the Input Control and read from it by the Output Control for an outgoing packet. The control information which shows the next block storing the packet is stored in the TAG Memory.
The Central Agent performs the following protocol independent and dependent functions:
Protocol Independent Functions
• Maintains the free list of the blocks which belongs to the buffer pool
• Accept returned blocks from the output ports
• Counting the returned blocks for the multicast
• Generating a request to the Output Control
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Protocol Dependent Functions
•
MAC Address Table and VLAN Table Lookup
•
VLAN Ingress Check
•
VLAN Egress Filter
•
Filtering frames based on port states
•
Port Security (Source Address based filtering)
•
Link Aggregation
•
IGMP/MLD Snooping
Figure 2: Central Switching Structure
Multicast Mechanism
The AXEL-X chip uses the logical multicast to utilize the packet memory or Stream Memory efficiently. After MAC Address Table lookup, the address pointer is replicated and put into designated output queues. Each output port loads the packet from Stream Memory in parallel and sends it to the link.
IP Multicast Snooping
To avoid unnecessary traffic in IP Multicast, AXEL-X supports following standard protocols:
• Internet Group Management Protocol (IGMP) for IPv4.
• Multicast Lister Discovery (MLD) for IPv6.
If an incoming frames is Query or Report of membership for IP Multicast, a copy of the frame is forwarded to Management which sets MAC Address Table and destination ports for the MAC address.
TAG Memory
Multi-port Stream Memory
Central Agent
Input Port 0Input Port 1
... ...
Input Port 0Input Port 1
...
Input Port 0Input Port 1
...
Output Port 0Output Port 1
Output Port 0Output Port 1
...Output Port 0Output Port 1
...
MAC Address Table / VLAN Table
(Data Storage)
(Control Storage)
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MAC Address Table
Ethernet protocol uses MAC Address for routing frames. MAC Addresses are stored in the MAC Address Table in the Central Switching Structure. AXEL-X has an 8-way set-associative routing table that is 16K entry in total. In addition to this, it has 32-entry full set-associative routing table. Figure 3 shows MAC Address Table format.
Figure 3: MAC Address Table
Lookup, Learning and Aging are the three processes which are performed on MAC address table for routing.
1. A learning process creates and updates table entries (Dynamic address learning by On Chip Hardware, Static address learning by Management).
2. A lookup process examines table entries for forwarding decision (On Chip Hardware).
3. Aging process removes stale entries from the table on a regular basis (On Chip Hardware).
The table search algorithm is hash-based, with MAC address as input to create table index using CRC when SVL is used. MAC address and VLAN ID are input when IVL is used. The static entries are programmed by the Processor and not learned and not aged out. For dynamic entries, the chip learns source address in the incoming frames from 10G ports and stores them in MAC address table. If the source address already learned and port vector matches, the time stamp is updated. If port vector does not match, no further action is taken.
The chip looks up entries in the table using hash-based search for the destination address to determine the output port to forward the packet. If the destination address is not found, the frame will be flooded to all the ports that are member of the VLAN other than the incoming port.
AXEL-X also supports Port Security feature. When Port security feature is enabled at the source port. the chip also looks up entries in the table using hash-based search for the source address if it is already learned in the MAC Address Table. If the source address is not found, the frame is forwarded to Processor for further decision and processing. Processor may add the MAC Address in the MAC Address Table if it is ok. Processor may completely shut down the port if it is necessary for security reasons.
Switch chip does aging process to check the stale entries in the table and remove them. If an entry is valid and not updated for a specified time, the aging process clears the valid bit for that entry.
Switch chip provides the table access mechanism for Software on Processor to search, learn or delete an entry in the MAC address table.
Error Protection: ECC
012585
MAC Address
bit 0 Valid
bit 1 Static
for Dynamic entry
bit[37:26] VLAN ID
bit[85:38] MAC Address
ECC VLANId Port#, Tstamp or Port Vector
S V
bit[95:88] ECC
bit[25:21] Port Number
3795
16k+32Entries
bit[11:2] Time Stamp
for Static entrybit[25:2] Port Vector
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VLAN Table
AXEL-X supports Virtual LAN (VLAN) which is defined in IEEE standard 802.1Q. Figure 4 shows VLAN table format. The table contains Valid bit, Port state for Multiple Spanning Tree Protocol, USE for VLAN membership, and TAG for VLAN Tagging of outgoing frame and ECC. VLAN ID is used as an index for the table entries.
Figure 4: VLAN Table
Port state in the VLAN table is used when Multiple Spanning Tree Protocol is enabled because the port state is supposed to be VLAN dependent. If Multiple Spanning Tree is not enabled, Port state in the Port Configuration register is used.
Lookup and Learning are the two processes which are performed on VLAN table for routing.
1. A lookup process examines VLAN entries for routing. The flooding frames are sent to the ports which belong to the same VLAN (On Chip Hardware)
2. A learning process creates and updates table entries which define VLAN associations between VLAN ID and the membership (by Management).
Error Protection: ECC
USETAG
6688
4kVLAN Entries
0
ECC V
8999bit 0 Valid
bit[66:45] USE
bit[88:67] TAG
bit[99:92] ECC
44
bit[44:1] Port State
Port State: 2bits per 10G port, bit[44:43] for Port23, bit[42:41] for Port21,
00: Disable 01: Blocking and Listening 10: Learning 11: Forwarding
USE: bit[66] for Port 23, bit[65] for Port 21, bit[64] for Port 19, .. , bit[45] for Port 0
0: Not in USE 1: In USE
TAG: bit[88] for Port 23, bit[87] for Port 21, bit[86] for Port 19, .. , bit[67] for Port 0
0: No Tagging
1: Tagging
Port StateM
bit[89] VLAN Mirror
bit[40:39] for Port19, bit[38:37] for Port18, ..bit[2:1] for Port0
M: bit [89] VLAN Mirroring
0: No
1: Yes
Notes: The USE field indicates the port membership of the VLAN. The TAG field indicates whether or not the tag should be removed for egress traffic.
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Reserved Multicast Address
Following Multicast addresses are reserved for special use, for example, STP, GVRP, GMRP, PAUSE, etc.
• 01-80-c2-00-00-00 to 01-80-c2-00-00-10
• 01-80-c2-00-00-20 to 01-80-c2-00-00-2f
In the default configuration, AXEL-X chip handles frames with these reserved multicast addresses as follows:
• Packet received on 10G ports
• If Processor is attached, forward to Processor
• If no Processor is attached, lookup MAC address and VLAN tables and make forwarding decision
• Packet received on Processor port
• Lookup MAC address and VLAN tables and make forwarding decision
AXEL-X also an additional BPDU handling feature to support Provider VLAN (P802.1ad). Using this feature, some BPDU can be transferred as it is between customer peer while other BPDU is terminated by the provider bridge.
Partitioning
AXEL-X supports Extended VLAN feature to allow logical partitioning of the switch for server blade application This methods supports multiple AXEL-X chips (not limited to two chips).
• Extended VLAN Table (64 entries x 24-bit port-vector)
• Port Default Extended VLAN ID
• Extended VLAN tag handling
• Extended VLAN is distinguished by a set of programmable VLAN tag.
• Optionally, Extended VLAN Priority can be added in the VLAN tag.
Link Aggregation
AXEL-X support Link Aggregation (802.3 clause 43) for increased bandwidth and availability. Link Aggregation allows one or more links to be aggregated together to form a Link Aggregation Group (LAG) as if it were a single link. Based on a Distribution algorithm selected, all frames of a given conversation are forwarded to a single port. Distribution algorithm is based on either of DA, SA, DA/SA, Reception port, Src IP, Dest IP, Src/Dest IP, Src Port, Dest Port, Src/Dest Port or VLAN ID. In addition, a tuning mechanism is supported for better load balancing if the number of end stations is small. When a link failure happens in LAG, the conversation can be moved to another link in the LAG.
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2.4 Output Port
Each output port consists of the Output Control, Media Access Control (MAC) Transmitter and the High speed IO Transmitter blocks as shown in Figure 5.
The Output Control performs protocol independent and protocol dependent functions:
Protocol Independent Functions
• Accepting an output request from the Central Agent and puts the request in the output queues
• Arbitrating output requests in the output queues
• Sharing the bandwidth fairly using Deficit Round Robin (DRR)
• Loading the packet data from the Stream Memory
Protocol Dependent Functions
• Filtering frames based on VLAN egress rules
• Output the packet data to the MAC Transmitter
• Simple proprietary interface to the MAC Transmitter
Figure 5: Output Port
The MAC Transmitter performs following IEEE 802.3ae compliant functions:
•
XGMII Interface to the high speed block including PHY register access
•
Generate PAUSE flow control packet by a request from the Input Control
•
Stop sending a new packet by a request from the MAC receiver
•
Frame Check Sequence generation and insertion
•
Statistics counters for network management
•
Link fault signaling
•
WAN-PHY (OC-192) data rate control
Media Access Control(MAC) Transmitter
Output Control Block
HSIO XGMIIProprietary Interface
HSIO: High Speed IO InterfaceXGMII: 10Gbit Media Independent Interface
High speed IO
blockTransmitter block
Output Queues
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The High speed IO Transmitter performs following functions:
• XGMII Interface to Media Access Control
• 8B/10B Encoder
• Serialization
• Transmitter equalization
• XAUI / 10GBASE-CX4 / 10G Serial (PHY) to physical Interface
Scheduling
The codepoint is mapped to a priority using the Priority Mapping Register. The Strict Priority, DRR or Strict+DRR is used for arbitration between 8 priorities. The scheduling is done on packet level.
2.5 On-chip Code
The On-Chip code communicates with AXEL-X Driver for initialization, handling management protocols, transferring frames, performing MAC address Table, VLAN Table updates and support network management functions.
The management packets to be processed by Management are as follows:
• BPDU for the spanning tree protocol
• GVRP for the virtual LAN
• ICMP for the switch control such as ping
• SNMP for the network management such as statistics monitoring and switch reset
• IGMP / MLD Snooping
• sFLOW
• BCN (Backward Congestion Notification)
Figure 6: An Example of Software Configuration
NIC Driver
On-Chip Code API
AXEL-X
AXEL-X On-Chip Code
AXEL-X Driver
API
Layer 2 Software
OS
for Management
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2.6 I2C Interface
AXEL-X has two I2C ports. One is I2C port1 (XB_SCL1 and XB_SDA1), and the other is I2C port2 (XB_SCL2 and XB_SDA2). Table 1 shows supported functions of each port.
Table 1: I2C Interface
Note that AXEL-X supports single master configuration when AXEL-X is the master device.
I2C Read/Write Operation (AXEL-X as a Master Device)
AXEL-X supports the following I2C read/write operation when AXEL-X is master device.
• Random read (Figure 7, Figure 9)
• Sequential write (Figure 8, Figure 10)
• Read operation packet error checking (Figure 11)
• Write operation packet error checking (Figure 12)
Abbreviation in the Figures is described below.
S = Start, P = Stop, W = Write, R = Read, A = Ack, N = Nack, M = MSB, L = LSB
Figure 7: Random Read (2 bytes address; n bytes data)
Initialization from EEPROM
a
a. XI_CONFIG[1] EEPROM Presence bit must be set to perform initialization from EEPROM that is initiated by power on or hard reset. It can also be initiated by I2C Port2 EEPROM Control Register.
Access to devices with 2-byte address
b
b. Write operation is initiated by I2C Port2 EEPROM Control Register, and read operation is initiated by I2C Port2 XFP Control Register.
Access to devices with 1-byte address
Work as a slave device
I2C port1 Not Supported Not Supported Supported
c
c. It’s initiated by I2C Port1 XFP Control Register.
Supported
I2C port2 Supported Supported Supported
d
d. It’s initiated by I2C Port2 XFP Control Register.
Not Supported
Format Figure 7 Figure 7, Figure 8 Figure 9, Figure 10, Figure 11, Figure 12
Figure 13
Master S W M L M L S
x x x x x x x 0 0 x x x x x x x x 0 x x x x x x x x 0 1 0 1 0 0 0 0
Slave A A A
Master R AA N P
1 0 x x x x x x x x 0 x x x x x x x x 0 x x x x x x x x 1
Slave A M L M L M L
Memory Address 1DEV Address Memory Address 0 DEV Address
…
Data word 0 Data word 1 Data word n
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Figure 8: Sequential Write (2 byte address; n bytes data)
Figure 9: Random Read (1 byte address; 1, 2, 4 bytes data)
Figure 10: Sequential Write (1 byte address; 1, 2, 4 bytes data)
Figure 11: Read Operation Packet Error Checking (1 byte address; 1, 2 ,4 bytes data)
Figure 12: Write Operation Packet Error Checking (1 byte address; 1, 2 ,4 bytes data)
Master S W
x x x x x x x 0 0 x x x x x x x x 0 x x x x x x x x 0
Slave A A A
Master M LM L
M L M L
M L P
x x x x x x x x 0 x x x x x x x x 0 x x x x x x x x 0
Slave A A A
Data Word 0 Data Word 1
Memory Address 1
Data Word n
…
DEV Address Memory Address 0
M LMaster S W S R
x x x x x x x 0 0 x x x x x x x x 0 1 0 1 0 0 0 0 1 0
Slave A A A
Master A A A N P
x x x x x x x x 0 x x x x x x x x 0 x x x x x x x x 0 x x x x x x x x 1
Slave M LM L M L M L
DEV Address
Data word 0 Data word 1
DEV Address Memory Address
Data word 3Data word 2
Master S W
x x x x x x x 0 0 x x x x x x x x 0 x x x x x x x x 0
Slave A A A
Master P
x x x x x x x x 0 x x x x x x x x 0 x x x x x x x x 0Slave A A A
Data Word 3Data Word 1 Data Word 2
Memory AddressDEV Address Data Word 0
M L M L
M L M L
M L
Master S W M LM L
x x x x x x x 0 0 x x x x x x x x 0 x x x x x x x x 0
Slave A A A
Master S R A A
1 0 1 0 0 0 0 1 0 x x x x x x x x 0 x x x x x x x x 0
Slave A M L M L
M LM L
Master A A N P
x x x x x x x x 0 x x x x x x x x 0 x x x x x x x x 1
Slave M L CRC-8
# of BytesDEV Address Memory Address
DEV Address
Data word 0 Data word 1
Data word 2 Data word 3
S W M LM L # of BytesDEV Address Memory AddressMaster
x x x x x x x 0 0 x x x x x x x x 0 x x x x x x x x 0
Slave A A A
Master M L M LM L
x x x x x x x x 0 x x x x x x x x 0 x x x x x x x x 0
Slave A A A
Master M L P
x x x x x x x x 0 x x x x x x x x 0 x x x x x x x x 0
Slave A A *
Data Word 0 Data Word 1 Data Word 2
* XFP responds with an ACK if CRC-8 is correct and a NACK if the CRC-8 is incorrect.
Data Word 3 CRC-8 CABM LM L
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Auxiliary Register Interface (AXEL-X as a Slave Device)
The auxiliary register interface (or I2C interface) is also provided to access registers in the switch. The address space of switch registers is 16-bit so that it uses indirect 16-bit addressing by sending two 8-bit data first to read or write the registers. Figure 13 shows the Auxiliary Register Interface Data Format. Note that once the address is set by read or write access, it’s not necessary for the following read accesses to the same address to set read address again.
Figure 13: Auxiliary Register Interface Data Format
EEPROM Data Format
The EEPROM Interface is provided for the configuration and initialization of the switch. If there is no EEPROM, the switch is configured and initialized through Auxiliary Register Interface.
Figure 14 shows the data formats of the EEPROM of 8bit wide. The EEPROM Interface loads the data based on these formats and writes them into the registers or tables. This procedure repeats until the End of Data is detected. The packet size for Table Data is equal or greater than 8 and depends on the table entry size.
Master S W M L M L P1 0 1 0 0 0 0 0 0 x x x x x x x x 0 x x x x x x x x 0
Slave A A A
DEV Address Memory Address 0 Memory Address 1
Master S W
x x x x x x x 0 0 x x x x x x x x 0 x x x x x x x x 0
Slave A A A
Master M L M L P
x x x x x x x x 0 x x x x x x x x 0 x x x x x x x x 0 x x x x x x x x 0
Slave A A A A
Data Word 2 Data Word 3Data Word 0 Data Word 1
DEV Address Memory Address 0 Memory Address 1
Master S R A
1 0 1 0 0 0 0 1 0 x x x x x x x x 0 x x x x x x x xSlave A M LM L
Master A A N P
0 x x x x x x x x 0 x x x x x x x x 1
Slave M LM L
Data word 1
Data word 2
DEV Address
Data word 3
Data word 0
M L M L
M L M L
2 Byte Write: Set read address.
6 Byte Write: Write 32 bit data to the specified 16 bit address.
4 Byte Read: Retrieve read data.
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Figure 14: EEPROM Data Format
2.7 Initialization
The initialization is a three step processes.
1. Hardware Initialization
2. Load Initialization by EEPROM / Management
3. Port State Initialization using Spanning Tree Protocol (optional)
The hardware initialization includes the followings:
• Internal registers
The all internal registers are initialized to their default values as defined in the Chapter 4.
• TAG Memory
TAG Memory is initialized to store indices which shows the next blocks, that is, address 0 is initialized to 1, address 1 is initialized to 2, and so forth.
• MAC address and VLAN Tables
All entries are initialized as invalid.
• Built In Self Test (BIST)
ex. to write 01020304h into
07h04h00h
00h
04h03h02h01h
General Purpose Register (0004h)
‘00000111’ (Byte length)
Address[7:2] ‘00’
Address[15:8]
Data[7:0]
7 0
0
1
2
Data[15:8]
Data[23:16]
Data[31:24]
3
4
5
6
‘00000000’ (End of Data)
7 0
0
Register Data End of Data
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The load initialization includes the followings:
• Internal registers
The internal registers are initialized based on the configuration.
• MAC address and VLAN Tables
The static entries are loaded and initialized as valid.
The port state initialization using Spanning Tree Protocol includes the followings:
• Port states
The port states can be programmed to be in the port states as required by the spanning tree protocol if this option is enabled.
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3. Network Management3.1 IntroductionSwitch chip facilitates for collecting management information by using various statistical counters. These counters are accessed by the processor through register access mechanism. The counters support BRIDGE MIB, RMON MIB, SMON MIB, IF MIB, Etherlike MIB. Routine Network Management packet transactions are performed on processor interface between switch chip and processor. Management packet handler provides a mechanism for data transfer.
3.2 Management Information Base (MIB) CountersEthernet Switch Chip supports a number of MIB counters for network management. These MIB counters are updated based on data received and transmitted by MAC, Input Control, Output Control, MAC address Table, VLAN table and Processor Interface. These counters are accessed by CPU periodically through the Processor Interface. All counter is defined as 32bit wide registers and actual counter width is specified in the following tables. For the counters with actual width less than 32 bits, unused upper bits are padded by 0.
Table 2: Transmit and Receive Counters (per port)
Name Width Description
TRC64 25 bits Transmit and Receive 64 Byte Frame Counter
TRC127 25 bits Transmit and Receive 65 to 127 Byte Frame Counter
TRC255 25 bits Transmit and Receive 128 to 255 Byte Frame Counter
TRC511 25 bits Transmit and Receive 256 to 511 Byte Frame Counters
TRC1000 25 bits Transmit and Receive 512 to 1023 Byte Frame Counters
TRC1500 25 bits Transmit and Receive 1024 to 1518 Byte Frame Counters
TRMGVC 25 bits Transmit and Receive 1519 to 1522 Byte Good VLAN Frame CNT
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Table 3: Receive Statistics Counters (per port)
Table 4: Transmist Statistics Counters (per port)
Name Width Description
RXBYTC 31 bits Number of Bytes received
RXPKTC 25 bits Number of Packets received
RXFCSC 25 bits Number of FCS errors received
RXMCAC 25 bits Number of Multicast packets
RXBCAC 25 bits Number of Broadcast packets received
RXCFC 16 bits Number of Control frames received
RXPFC 16 bits Number of Pause Frame packets received
RXUOC 16 bits Number of Unknown OP codes received
RXALNC 16 bits Number of Alignment Errors received
RXFLRC 25 bits Number of Frame Length Errors receiveda
a. Length errors are not counted in VLAN Tagged frame.
RXCDEC 25 bits Number of Code Errors received
RXCSEC 16 bits Number of Carrier Sense Errors received
RXUNDC 16 bits Number of Undersize packets received
RXOVRC 25 bits Number of oversize packets received
RXFRGC 16 bits Number of Fragments received
RXJBRC 25 bits Number of Jabbers received
RXDRPC 25 bits Number of packets dropped
RXPFC_Pn (n=0-7) 16 bits Number of received Priority Pause frames with Priority n
RXPFC_TRn (n=0-7) 16 bits Number of transition from “not paused” to “paused” for priority n
Name Width Description
TXBYTC 31 bits Number of bytes transmitted
TXPKTC 25 bits Number of packets transmitted
TXMCAC 25 bits Number of Multicast packets transmitted
TXBCAC 25 bits Number of Broadcast packets transmitted
TXPFC 16 bits Number of PAUSE control frames transmitted
TXTOC 16 bits Number of packets dropped because of Lifetime
TXDRPC 25 bits Number of Dropped frames
TXJBRC 25 bits Number of Jabber frames
TXFCSC 25 bits Number of FCS errors
TXCFC 16 bits Number of Control frames
TXOVRC 25 bits Number of Oversize frames
TXUNDC 14 bits Number of Undersize frames
TXFRGC 14 bits Number of Fragments frames
TXPFC_Pn (n=0-7) 16 bits Number of transmitted Priority PAUSE frames with Priority n
Chip Specification
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Table 5: Flow Control Statistics Counters (per port)
Table 6: VLAN Statistics Counters (per monitored VLANa)
a. up to 32 VLANs can be monitored, xxxByteL needs to be read before xxxByteH to guarantee correct 35 bit value.
Table 7: Priority Statistics Counters (per port)
Name Width Description
FWpkts 29 bits Number of good frames that were forwarded as normal
FLDpkts 25 bits Number of good frames that were flooded due to an unknown destination
VLANDrops 25 bits Number of good frames that were dropped because of different VLANs for source/destination
FULLDrops 25 bits Number of good frames that were dropped because the Input Buffer is full
STMDrops 25 bits Number of good frames that were dropped because of the Storm Control
EDDrops 25 bits Number of good frames that were dropped because of the Early Detection Control
CMDrops 25 bits Number of good frames that were dropped because of the OQ Congestion Management
PortLearnDrops 25 bits Number of learning drops that were dropped by a port.
Name Width Description
VLANunicastPkts 29 bits Number of good unicast packets received on a designated VLAN
VLANunicastBytesL 32 bits Lower 32 bits of Number of bytes in good unicast packets received on a designated VLAN
VLANunicastBytesH 3 bits Upper 3 bits of Number of bytes in good unicast packets received on a designated VLAN
VLANMulticastPkts 29 bits Number of good Multicast packets received on a designated VLAN
VLANMulticastBytesL 32 bits Lower 32 bits of Number of bytes in good Multicast packets received on a designated VLAN
VLANMulticastBytesH 3 bits Upper 3 bits of Number of bytes in good Multicast packets received on a designated VLAN
Name Width Description
RxPriority0Pkts 25 bits Number of good packets received at 802.1Q user priority levela 0
a. This is the priority level in the incoming packet.
RxPriority0Bytes 31 bits Number of bytes in good packets received at 802.1Q user priority level 0
RxPriority1Pkts 25 bits Number of good packets received at 802.1Q user priority level 1
RxPriority1Bytes 31 bits Number of bytes in good packets received at 802.1Q user priority level 1
RxPriority2Pkts 25 bits Number of good packets received at 802.1Q user priority level 2
RxPriority2Bytes 31 bits Number of bytes in good packets received at 802.1Q user priority level 2
RxPriority3Pkts 25 bits Number of good packets received at 802.1Q user priority level 3
RxPriority3Bytes 31 bits Number of bytes in good packets received at 802.1Q user priority level 3
RxPriority4Pkts 25 bits Number of good packets received at 802.1Q user priority level 4
RxPriority4Bytes 31 bits Number of bytes in good packets received at 802.1Q user priority level 4
RxPriority5Pkts 25 bits Number of good packets received at 802.1Q user priority level 5
RxPriority5Bytes 31 bits Number of bytes in good packets received at 802.1Q user priority level 5
RxPriority6Pkts 25 bits Number of good packets received at 802.1Q user priority level 6
RxPriority6Bytes 31 bits Number of bytes in good packets received at 802.1Q user priority level 6
RxPriority7Pkts 25 bits Number of good packets received at 802.1Q user priority level 7
RxPriority7Bytes 31 bits Number of bytes in good packets received at 802.1Q user priority level 7
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Table 8: Host Monitoring Statistics
Statistics Collection TaskSwitch software is assumed to use Polling scheme to collect statistics with one second interval. The procedure using AUTOZ* mode is as follows:
1. Wait for one second
2. Read all counter registers
3. Go to 1)
*If AUTOZ is enabled, a counter is cleared when it is read.
The width of counters are decided based on packet switching rate and this statistics collection task with one second interval. Therefore an overflow won’t happen in normal operation. If it happened, an interrupt will be generated.
If AUTOZ is disabled, Carry registers can be used to detect rollover conditions and adjust counter values maintained by Management agent.
Name Width Description
Hostinpkts 25 bits Number of frames transmitted to Host
Hostoutpkts 25 bits Number of good frames received from host
HostoutErrors 25 bits Number of bad frames received from host.
Chip Specification
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4. Error Handling4.1 IntroductionThis chapter describes how the AXEL-X chip handles errors. There are five categories of errors:
• Input errors
• Bridge errors
• Output errors
• Hardware errors
• Software errors
These error groups are described in the following sections.
The error level is defined as follows:
• F: Fatal
• NFC: Non Fatal Correctable
• NFU: Non Fatal Uncorrectable
4.2 Input ErrorsTable 9 shows Input errors, levels and switch actions.
Table 9: Input Errors
Error Type Level Switch Action Note
Local Link Fault NFU Report the status
Remote Link Fault NFU Report the status
Symbol Error NFU Count and drop the packet
Alignment Error NFU Count and drop the packet
Length Error NFU Count and drop the packet
FCS Error NFU Count and drop the packet or abort the transmission of the packet.
Input buffer Full NFU Drop incoming packet
Acceptable Frame Filter NFU Count and drop the packet
Storm Control NFU Drop the packet
VLAN Ingress Check NFU Drop the packet
VLAN Filter Hit NFU Drop the packet and report the event VLAN setting may not be correct.
Port Security Violation NFU Forward the packet to CPU and report the event Firmware needs to check SA in the frame.
Loopback Alert NFU Report the event
Lookup Backpressure NFU Report the event Max. Pending Lookup may not be appropriate.
Input buffer Underflow NFU Truncate the packet and report the event
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4.3 Bridge ErrorsTable 10 shows Bridge errors, levels and switch actions.
Table 10: Bridge Errors
4.4 Output ErrorsTable 11 shows Output errors, levels and switch actions.
Table 11: Output Errors
4.5 Hardware ErrorsTable 12 shows Hardware errors, levels and switch actions.
Table 12: Hardware Errors
Error Type Level Switch Action Note
Life Timeout NFU Count and drop the packet
Error Type Level Switch Action Note
VLAN Egress Filter NFU Drop the packet
Local Link Fault NFU Report the status and signalling
Remote Link Fault NFU Report the status
Tx XOFF State NFU Report the event
Error Type Level Switch Action Note
CM Buffer MBE F Log and report the event need chip reset
Tag Memory MBE F Log and report the event need chip reset
Drop Queue MBE F Report the event need chip reset
Output Queue MBE F Report the event need chip reset
IBUF Tag MBE NFU Report the event need port reset
MAC Address Table MBE NFU Log and report the event need to delete the entry
VLAN Table MBE NFU Log and report the event need to delete the entry
MST MBE NFU Log, count and report the event if error count becomes large, need chip reset
Stream Memory Tag MBE NFU Report the event
CM Buffer SBE NFC Log and report the event
Tag Memory SBE NFC Log and report the event. Writeback when SBE Writeback is enabled.
Drop Queue SBE NFC Report the event
Output Queue SBE NFC Report the event
IBUF Tag SBE NFC Report the event
MAC Address Table SBE NFC Report the event
VLAN Table SBE NFC Log and report the event. Writeback when SBE Writeback is enabled.
MST SBE NFC Log and report the event. Writeback when SBE Writeback is enabled.
Stream Memory Tag SBE NFC Report the event
Chip Specification
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5. IO Signals5.1 External PinsTable 14 shows the external pin definition of the Ethernet Switch Chip. The external pins consist of the following groups.
• HSIO Ports (320 pins)
• GMII/MII Ports (50 pins)
• Serial Bus Interface (8 pins)
• Configuration and Miscellaneous (20 pins)
• Clock and Reset (15 pins)
• JTAG Port (5 pins)
• Test Pins (8 pins))
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Table 13: Ethernet Switch Chip External Pins
Signal IO Type Descriptions
HSIO Ports (nn=00,..,19) (16 pins x 20 ports)
XI_Pnn_RXP[3:0]XI_Pnn_RXN[3:0]
I differential HSIO port (port nn) receiver signals.
RXP is the positive of a pair, and RXN is the negative of the pair. ([0]: 10.3Gbps/3.2Gbps, [3:1]: 3.2Gbps)
XO_Pnn_TXP[3:0]XO_Pnn_TXN[3:0]
O differential HSIO port (Port nn) transmitter signals.
TXP is the positive of a pair, and TXN is the negative of the pair. ([0]: 10.3Gbps/3.2Gbps, [3:1]: 3.2Gbps)
GMII/MII Ports (25 pins x 2 ports)
XI_RX_CLK1 I 2.5VCMOS Rx clock inputs.
(125MHz for 1000Mbps, 25MHz for 100Mbps, 2.5MHz for 10Mbps)
XI_RXD1[7:0] I 2.5VCMOS Rx data.
XI_RX_DV1 I 2.5VCMOS RX data valid.
XI_RX_ER1 I 2.5VCMOS RX error.
XO_GTX_CLK1 O 2.5VCMOS GMII Tx clock output.
(125MHz for 1000Mbps)
XI_TX_CLK1 I 2.5VCMOS MII Tx clock inputs.
(25MHz for 100Mbps, 2.5MHz for 10Mbps)
XO_TXD1[7:0] O 2.5VCMOS Tx data.
XO_TX_EN1 O 2.5VCMOS Tx enable.
XO_TX_ER1 O 2.5VCMOS Tx error.
XI_COL1 I 2.5VCMOS Collision.
XI_CRS1 I 2.5VCMOS Carrier sense.
XI_RX_CLK2 I 2.5VCMOS Rx clock inputs.
(125MHz for 1000Mbps, 25MHz for 100Mbps, 2.5MHz for 10Mbps)
XI_RXD2[7:0] I 2.5VCMOS Rx data.
XI_RX_DV2 I 2.5VCMOS RX data valid.
XI_RX_ER2 I 2.5VCMOS RX error.
XO_GTX_CLK2 O 2.5VCMOS GMII Tx clock output.
(125MHz for 1000Mbps)
XI_TX_CLK2 I 2.5VCMOS MII Tx clock inputs.
(25MHz for 100Mbps, 2.5MHz for 10Mbps)
XO_TXD2[7:0] O 2.5VCMOS Tx data.
XO_TX_EN2 O 2.5VCMOS Tx enable.
XO_TX_ER2 O 2.5VCMOS Tx error.
XI_COL2 I 2.5VCMOS Collision.
XI_CRS2 I 2.5VCMOS Carrier sense.
Chip Specification
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Serial Bus Interface (8 pins)
XB_SCL1 IO 2.5VCMOS (O/D) I2C port 1 clock line.
XB_SDA1 IO 2.5VCMOS (O/D) I2C port 1 data line.
XB_SCL2 IO 2.5VCMOS (O/D) I2C port 2 clock line.
XB_SDA2 IO 2.5VCMOS (O/D) I2C port 2 data line.
XO_MDC1 O 2.5VCMOS MDIO port 1 clock line.
XB_MDIO1 IO 2.5VCMOS (O/D) MDIO port 1 data line.
XO_MDC2 O 2.5VCMOS MDIO port 2 clock line.
XB_MDIO2 IO 2.5VCMOS (O/D) MDIO port 2 data line.
Chip Configuration and Miscellaneous Signals (20 pins)
XI_CONFIG[7:0] I 2.5VCMOS Chip Configuration.
[7] must be set to 0
[6:4] Lower 3 bits of slave address. The slave address is represented by 4’b1010, XI_CONFIG[6:4]
Valid configuration: 3’b001~3’b111
[3] Buffer Configuration (1: by Management, 0: use Default)
[2] I2C bus speed (1: 400KHz, 0: 100KHz)
[1] EEPROM presence (1: with EEPROM)
[0] must be set to 1
XO_STS_OUT[8:0] O 2.5VCMOS Status Output.
See “Debug Port Selection Register” in Register Description.
XO_IRQ_N[2:0] O 2.5VCMOS (O/D) Interrupt Request. (active low)
[2] fatal errors.
[1] correctable errors.
[0] service required for non-error operations.
Clock and Reset (15 pins) (mm=01,03,12,13,14,15)
XI_Pmm_REFCLKPXI_Pmm_REFCLKN
I LVDS External clock inputs for core logic and HSIO (156.25MHz, differential)
XI_PWRGOOD I 2.5VCMOS Power good signal (active high)
XI_RESET_N I 2.5VCMOS Reset input for core logic (active low)
XI_RESET_PLL_N I 2.5VCMOS Reset input for core PLL (active low)
JTAG Port (5 pins)
XI_TCK I 2.5VCMOS JTAG test clock input.
XI_TMS I 2.5VCMOS JTAG test mode select input.
XI_TDI I 2.5VCMOS JTAG test data input.
XI_TRST_N I 2.5VCMOS JTAG test reset input. (active low)
XO_TDO O 2.5VCMOS JTAG test data output.
Table 13: Ethernet Switch Chip External Pins (Continued)
Signal IO Type Descriptions
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Test Pins (8 pins)
XI_HTMODE I 2.5VCMOS HSIO test mode select (1: test mode 0: normal)
XI_HTSCK I 2.5VCMOS HSIO test clock
XI_HTXRST I 2.5VCMOS HSIO test register reset (active low)
XO_HTCLKO O 2.5VCMOS HSIO test clock output
XI_SCK I 2.5VCMOS Auxiliary clock input for test mode
XI_PLLBP I 2.5VCMOS PLL bypass mode input (1: bypass 0: normal)
XI_VPD1 I 2.5VCMOS IDDQ test control input (1: test mode 0: normal)
XI_VPD2 I 2.5VCMOS IDDQ test control input (1: test mode 0: normal)
Power Pins (mm=01,03,12,13,14,15)
VDE +2.5V 2.5V power supply for CMOS IO
VDD +1.2V 1.2V power supply for core logic
VSS GND Common ground
VDP +2.5V 2.5V power supply for HSIO
VDN +1.2V 1.2V power supply for HSIO
VDR analog Termination for HSIO
VSN GND Ground for HSIO
AVD +1.2V 1.2V power supply for core PLL
AVS GND Ground.for core PLL
XI_Pmm_CKVTT I analog Center tap of LVDS inputs (XI_Pmm_REFCLKP/N)
Table 13: Ethernet Switch Chip External Pins (Continued)
Signal IO Type Descriptions
Chip Specification
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6. Mechanical DescriptionThis chapter describes the pin assignments and the mechanical specifications.
6.1 DimensionsThe mechanical specifications are shown in Table 14.
Figure 15: Drawing Details for FCBGA1156
Parameter Value
Package type FC-BGA (Flip Chip Ball Grid Array)
Total pin count 1156
Package size 35 x 35 sq mm
Ball pitch 1.0 mm
Thermal Resistance (°C/W) θjc = 0.73θja = 8.45 (0 m/s air), 6.67 (1 m/s air), 4.45 (3 m/s air)
Drawing details for FCBGA1156 Preliminary & Confidential
Dimensions in millimeters
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6.2 Pin Organization
Figure 16: Package Pins
indexA
Axel-X package pins version 08 (01/19/2006)Bottom View FCBGA1156
B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
VSS (Gnd)
VDD (1.2V)
VDE (2.5V, I0)
VSN (Gnd for HSI0)
VDP (2.5V for HSI0)
VDN (1.2V for HSI0)
VDR (0.8V, Termination for HSI0)
differential (HSI0)
differential (clock)
single-ended
chip peripheral
Chip Area
HSIO Port
core side
TX1-
TX1+
TX3-
TX3+
TX0-
TX0+
TX2-
TX2+
RX0+
RX3-
RX2-
RX2+
RX0-
RX3+
RX1-
RX1+
Chip Specification
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Pin Name
A1 VDN
A2 XI_P08_RXP[0]
A3 XI_P08_RXN[0]
A4 XI_P08_RXP[2]
A5 XI_P08_RXN[2]
A6 XI_P12_RXP[0]
A7 XI_P12_RXN[0]
A8 XI_P12_RXP[2]
A9 XI_P12_RXN[2]
A10 XI_P16_RXP[0]
A11 XI_P16_RXN[0]
A12 XI_P16_RXP[2]
A13 XI_P16_RXN[2]
A14 XI_P17_RXP[0]
A15 XI_P17_RXN[0]
A16 XI_P17_RXP[2]
A17 XI_P17_RXN[2]
A18 XI_P13_RXP[0]
A19 XI_P13_RXN[0]
A20 XI_P13_RXP[2]
A21 XI_P13_RXN[2]
A22 XI_P09_RXP[0]
A23 XI_P09_RXN[0]
A24 XI_P09_RXP[2]
A25 XI_P09_RXN[2]
A26 VSN
A27 VDN
A28 XI_RESET_N
A29 XI_PLLBP
A30 VDD
A31 VSS
A32 XB_SDA1
A33 VDD
A34 VSS
B1 VSN
B2 VDN
B3 XI_P08_RXP[1]
B4 XI_P08_RXN[1]
B5 XI_P08_RXP[3]
B6 XI_P08_RXN[3]
B7 XI_P12_RXP[1]
B8 XI_P12_RXN[1]
B9 XI_P12_RXP[3]
B10 XI_P12_RXN[3]
B11 XI_P16_RXP[1]
B12 XI_P16_RXN[1]
B13 XI_P16_RXP[3]
B14 XI_P16_R XN[3]
B15 XI_P17_RXP[1]
B16 XI_P17_RXN[1]
B17 XI_P17_RXP[3]
B18 XI_P17_RXN[3]
B19 XI_P13_RXP[1]
B20 XI_P13_RXN[1]
B21 XI_P13_RXP[3]
B22 XI_P13_RXN[3]
B23 XI_P09_RXP[1]
B24 XI_P09_RXN[1]
B25 XI_P09_RXP[3]
B26 XI_P09_RXN[3]
B27 VSN
B28 NC
B29 XI_PWRGOOD
B30 VSS
B31 VDD
B32 XB_SCL1
B33 XO_TX_ER1
B34 VDD
C1 VDN
C2 VSN
C3 VDN
C4 VDP
Pin Name
C5 VDR
C6 VSN
C7 VDN
C8 VDP
C9 VDR
C10 VSN
C11 VDN
C12 VDP
C13 VDR
C14 VSN
C15 VDN
C16 VDP
C17 VDR
C18 VSN
C19 VDN
C20 VDP
C21 VDR
C22 VSN
C23 VDN
C24 VDP
C25 VDR
C26 VSN
C27 VDN
C28 XI_RESET_PLL_N
C29 VSS
C30 VDD
C31 VSS
C32 XO_TX_EN1
C33 XO_TXD1[0]
C34 XO_TXD1[1]
D1 VSN
D2 VDN
D3 XO_P08_TXP[2]
D4 XO_P08_TXN[2]
D5 XO_P08_TXP[0]
D6 XO_P08_TXN[0]
Pin Name
D7 XO_P12_TXP[2]
D8 XO_P12_TXN[2]
D9 XO_P12_TXP[0]
D10 XO_P12_TXN[0]
D11 XO_P16_TXP[2]
D12 XO_P16_TXN[2]
D13 XO_P16_TXP[0]
D14 XO_P16_TXN[0]
D15 XO_P17_TXP[2]
D16 XO_P17_TXN[2]
D17 XO_P17_TXP[0]
D18 XO_P17_TXN[0]
D19 XO_P13_TXP[2]
D20 XO_P13_TXN[2]
D21 XO_P13_TXP[0]
D22 XO_P13_TXN[0]
D23 XO_P09_TXP[2]
D24 XO_P09_TXN[2]
D25 XO_P09_TXP[0]
D26 XO_P09_TXN[0]
D27 VSN
D28 VSS
D29 XO_STS_OUT[0]
D30 XI_SCK
D31 VDD
D32 VSS
D33 XO_TXD1[2]
D34 XO_TXD1[3]
E1 VSN
E2 XO_P08_TXP[3]
E3 XO_P08_TXN[3]
E4 XO_P08_TXP[1]
E5 XO_P08_TXN[1]
E6 XO_P12_TXP[3]
E7 XO_P12_TXN[3]
E8 XO_P12_TXP[1]
Pin Name
6.3 Pin ListingTable 15 shows pin listing. Note that NC stands for No Connection.
Table 15: Pin Listing
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E9 XO_P12_TXN[1]
E10 XO_P16_TXP[3]
E11 XO_P16_TXN[3]
E12 XO_P16_TXP[1]
E13 XO_P16_TXN[1]
E14 XO_P17_TXP[3]
E15 XO_P17_TXN[3]
E16 XO_P17_TXP[1]
E17 XO_P17_TXN[1]
E18 XO_P13_TXP[3]
E19 XO_P13_TXN[3]
E20 XO_P13_TXP[1]
E21 XO_P13_TXN[1]
E22 XO_P09_TXP[3]
E23 XO_P09_TXN[3]
E24 XO_P09_TXP[1]
E25 XO_P09_TXN[1]
E26 VSN
E27 VDN
E28 XO_STS_OUT[3]
E29 XO_STS_OUT[2]
E30 XO_STS_OUT[1]
E31 VSS
E32 XO_TXD1[4]
E33 XO_TXD1[5]
E34 VSS
F1 VDN
F2 VSN
F3 VDN
F4 VSN
F5 VDN
F6 VSN
F7 VDN
F8 VSN
F9 VDN
F10 VSN
F11 VDN
F12 VSN
F13 VDN
Pin Name
F14 VSN
F15 VDN
F16 VSN
F17 VDN
F18 VSN
F19 VDN
F20 VSN
F21 VDN
F22 VSN
F23 VDN
F24 VSN
F25 VDN
F26 VSN
F27 XO_STS_OUT[4]
F28 NC
F29 XO_STS_OUT[5]
F30 XO_STS_OUT[6]
F31 XO_TXD1[6]
F32 XO_TXD1[7]
F33 VSS
F34 XO_GTX_CLK1
G1 VSN
G2 XI_P04_RXN[3]
G3 VSN
G4 XO_P04_TXN[0]
G5 VSN
G6 VDP
G7 VSN
G8 VDN
G9 VDP
G10 XI_P12_CKVTT
G11 VSN
G12 XI_P12_REFCLKP
G13 XI_P12_REFCLKN
G14 VDN
G15 VDP
G16 VDN
G17 VSN
G18 VDN
Pin Name
G19 XI_P13_CKVTT
G20 VDP
G21 VSN
G22 XI_P13_REFCLKP
G23 XI_P13_REFCLKN
G24 VDN
G25 VDP
G26 NC
G27 NC
G28 VSS
G29 XO_STS_OUT[7]
G30 XO_MDC1
G31 VDD
G32 VSS
G33 XI_COL1
G34 VSS
H1 XI_P04_RXN[2]
H2 XI_P04_RXP[3]
H3 VDR
H4 XO_P04_TXP[0]
H5 XO_P04_TXN[1]
H6 VSN
H7 VDN
H8 VSN
H9 VDN
H10 VSN
H11 VDN
H12 VSN
H13 VDN
H14 VSN
H15 VDN
H16 VSN
H17 VDN
H18 VSN
H19 VDN
H20 VSN
H21 VDN
H22 VSN
H23 VDN
Pin Name
H24 VSN
H25 VDE
H26 NC
H27 XB_MDIO1
H28 XO_STS_OUT[8]
H29 VSS
H30 VDD
H31 XI_RXD1[0]
H32 XI_CRS1
H33 XI_RX_ER1
H34 XI_RX_DV1
J1 XI_P04_RXP[2]
J2 XI_P04_RXN[1]
J3 VDP
J4 XO_P04_TXN[2]
J5 XO_P04_TXP[1]
J6 VDN
J7 VSN
J8 VDN
J9 VSN
J10 VDN
J11 VSN
J12 VDN
J13 VSN
J14 VDN
J15 VSN
J16 VDN
J17 VSN
J18 VDN
J19 VSN
J20 VDN
J21 VSN
J22 VDN
J23 VSN
J24 VDN
J25 VSS
J26 VDE
J27 VSS
J28 VDD
Pin Name
Table 15: Pin Listing (Continued)
Chip Specification
Fujitsu Microelectronics America, Inc. 29Confidential
J29 XI_TX_CLK1
J30 VSS
J31 XI_RXD1[1]
J32 XI_RXD1[2]
J33 XI_RXD1[3]
J34 XI_RXD1[4]
K1 XI_P04_RXN[0]
K2 XI_P04_RXP[1]
K3 VDN
K4 XO_P04_TXP[2]
K5 XO_P04_TXN[3]
K6 VSN
K7 VDP
K8 VSN
K9 VDD
K10 VSS
K11 VDD
K12 VSS
K13 VDD
K14 VSS
K15 VDD
K16 VSS
K17 VDD
K18 VSS
K19 VDD
K20 VSS
K21 VDD
K22 VSS
K23 VDD
K24 VSS
K25 VDD
K26 VSS
K27 VDE
K28 VSS
K29 VDD
K30 XI_RX_CLK1
K31 NC
K32 XI_RXD1[5]
Pin Name
K33 XI_RXD1[6]
K34 XI_RXD1[7]
L1 XI_P04_RXP[0]
L2 XI_P00_RXN[3]
L3 VSN
L4 XO_P00_TXN[0]
L5 XO_P04_TXP[3]
L6 VDN
L7 VSN
L8 VDN
L9 VSS
L10 VDD
L11 VSS
L12 VDD
L13 VSS
L14 VDD
L15 VSS
L16 VDD
L17 VSS
L18 VDD
L19 VSS
L20 VDD
L21 VSS
L22 VDD
L23 VSS
L24 VDD
L25 VSS
L26 VDE
L27 VSS
L28 AVS
L29 VSS
L30 VDN
L31 VSN
L32 VDP
L33 VSN
L34 VDN
M1 XI_P00_RXN[2]
M2 XI_P00_RXP[3]
Pin Name
M3 VDR
M4 XO_P00_TXP[0]
M5 XO_P00_TXN[1]
M6 VSN
M7 VDN
M8 VSN
M9 VDD
M10 VSS
M11 VDD
M12 VSS
M13 VDD
M14 VSS
M15 VDD
M16 VSS
M17 VDD
M18 VSS
M19 VDD
M20 VSS
M21 VDD
M22 VSS
M23 VDD
M24 VSS
M25 VDD
M26 VSS
M27 VDE
M28 AVD
M29 VDN
M30 XO_P05_TXP[3]
M31 VDN
M32 VSN
M33 VDN
M34 XI_P05_RXP[0]
N1 XI_P00_RXP[2]
N2 XI_P00_RXN[1]
N3 VDP
N4 XO_P00_TXN[2]
N5 XO_P00_TXP[1]
N6 VDN
Pin Name
N7 VSN
N8 VDN
N9 VSS
N10 VDD
N11 VSS
N12 VDD
N13 VSS
N14 VDD
N15 VSS
N16 VDD
N17 VSS
N18 VDD
N19 VSS
N20 VDD
N21 VSS
N22 VDD
N23 VSS
N24 VDD
N25 VSS
N26 VDE
N27 VSS
N28 VDD
N29 VSN
N30 XO_P05_TXN[3]
N31 XO_P05_TXP[2]
N32 VDN
N33 XI_P05_RXP[1]
N34 XI_P05_RXN[0]
P1 XI_P00_RXN[0]
P2 XI_P00_RXP[1]
P3 VDN
P4 XO_P00_TXP[2]
P5 XO_P00_TXN[3]
P6 VSN
P7 VDP
P8 VSN
P9 VDD
P10 VSS
Pin Name
Table 15: Pin Listing (Continued)
MB8AA3020
30 Fujitsu Microelectronics America, Inc. Confidential
P11 VDD
P12 VSS
P13 VDD
P14 VSS
P15 VDD
P16 VSS
P17 VDD
P18 VSS
P19 VDD
P20 VSS
P21 VDD
P22 VSS
P23 VDD
P24 VSS
P25 VDD
P26 VSS
P27 VDE
P28 VSS
P29 VDN
P30 XO_P05_TXP[1]
P31 XO_P05_TXN[2]
P32 VDP
P33 XI_P05_RXN[1]
P34 XI_P05_RXP[2]
R1 XI_P00_RXP[0]
R2 XI_P03_RXN[3]
R3 VSN
R4 XO_P03_TXN[0]
R5 XO_P00_TXP[3]
R6 VDN
R7 VSN
R8 VDN
R9 VSS
R10 VDD
R11 VSS
R12 VDD
R13 VSS
R14 VDD
Pin Name
R15 VSS
R16 VDD
R17 VSS
R18 VDD
R19 VSS
R20 VDD
R21 VSS
R22 VDD
R23 VSS
R24 VDD
R25 VSS
R26 VDE
R27 VSS
R28 XI_P01_CKVTT
R29 VSN
R30 XO_P05_TXN[1]
R31 XO_P05_TXP[0]
R32 VDR
R33 XI_P05_RXP[3]
R34 XI_P05_RXN[2]
T1 XI_P03_RXN[2]
T2 XI_P03_RXP[3]
T3 VDR
T4 XO_P03_TXP[0]
T5 XO_P03_TXN[1]
T6 VSN
T7 VDN
T8 VSN
T9 VDD
T10 VSS
T11 VDD
T12 VSS
T13 VDD
T14 VSS
T15 VDD
T16 VSS
T17 VDD
T18 VSS
Pin Name
T19 VDD
T20 VSS
T21 VDD
T22 VSS
T23 VDD
T24 VSS
T25 VDD
T26 VSS
T27 VDE
T28 VSN
T29 VDN
T30 XO_P01_TXP[3]
T31 XO_P05_TXN[0]
T32 VSN
T33 XI_P05_RXN[3]
T34 XI_P01_RXP[0]
U1 XI_P03_RXP[2]
U2 XI_P03_RXN[1]
U3 VDP
U4 XO_P03_TXN[2]
U5 XO_P03_TXP[1]
U6 VDN
U7 XI_P03_REFCLKN
U8 VDN
U9 VSS
U10 VDD
U11 VSS
U12 VDD
U13 VSS
U14 VDD
U15 VSS
U16 VDD
U17 VSS
U18 VDD
U19 VSS
U20 VDD
U21 VSS
U22 VDD
Pin Name
U23 VSS
U24 VDD
U25 VSS
U26 VDE
U27 VSN
U28 XI_P01_REFCLKP
U29 VSN
U30 XO_P01_TXN[3]
U31 XO_P01_TXP[2]
U32 VDN
U33 XI_P01_RXP[1]
U34 XI_P01_RXN[0]
V1 XI_P03_RXN[0]
V2 XI_P03_RXP[1]
V3 VDN
V4 XO_P03_TXP[2]
V5 XO_P03_TXN[3]
V6 VSN
V7 XI_P03_REFCLKP
V8 VSN
V9 VDE
V10 VSS
V11 VDD
V12 VSS
V13 VDD
V14 VSS
V15 VDD
V16 VSS
V17 VDD
V18 VSS
V19 VDD
V20 VSS
V21 VDD
V22 VSS
V23 VDD
V24 VSS
V25 VDD
V26 VSS
Pin Name
Table 15: Pin Listing (Continued)
Chip Specification
Fujitsu Microelectronics America, Inc. 31Confidential
V27 VDN
V28 XI_P01_REFCLKN
V29 VDN
V30 XO_P01_TXP[1]
V31 XO_P01_TXN[2]
V32 VDP
V33 XI_P01_RXN[1]
V34 XI_P01_RXP[2]
W1 XI_P03_RXP[0]
W2 XI_P07_RXN[3]
W3 VSN
W4 XO_P07_TXN[0]
W5 XO_P03_TXP[3]
W6 VDN
W7 VSN
W8 VDE
W9 VSS
W10 VDD
W11 VSS
W12 VDD
W13 VSS
W14 VDD
W15 VSS
W16 VDD
W17 VSS
W18 VDD
W19 VSS
W20 VDD
W21 VSS
W22 VDD
W23 VSS
W24 VDD
W25 VSS
W26 VDD
W27 VSN
W28 VDN
W29 VSN
W30 XO_P01_TXN[1]
Pin Name
W31 XO_P01_TXP[0]
W32 VDR
W33 XI_P01_RXP[3]
W34 XI_P01_RXN[2]
Y1 XI_P07_RXN[2]
Y2 XI_P07_RXP[3]
Y3 VDR
Y4 XO_P07_TXP[0]
Y5 XO_P07_TXN[1]
Y6 VSN
Y7 XI_P03_CKVTT
Y8 VSS
Y9 VDE
Y10 VSS
Y11 VDD
Y12 VSS
Y13 VDD
Y14 VSS
Y15 VDD
Y16 VSS
Y17 VDD
Y18 VSS
Y19 VDD
Y20 VSS
Y21 VDD
Y22 VSS
Y23 VDD
Y24 VSS
Y25 VDD
Y26 VSS
Y27 VDN
Y28 VSN
Y29 VDN
Y30 XO_P02_TXP[3]
Y31 XO_P01_TXN[0]
Y32 VSN
Y33 XI_P01_RXN[3]
Y34 XI_P02_RXP[0]
Pin Name
AA1 XI_P07_RXP[2]
AA2 XI_P07_RXN[1]
AA3 VDP
AA4 XO_P07_TXN[2]
AA5 XO_P07_TXP[1]
AA6 VDN
AA7 VSS
AA8 VDE
AA9 VSS
AA10 VDD
AA11 VSS
AA12 VDD
AA13 VSS
AA14 VDD
AA15 VSS
AA16 VDD
AA17 VSS
AA18 VDD
AA19 VSS
AA20 VDD
AA21 VSS
AA22 VDD
AA23 VSS
AA24 VDD
AA25 VSS
AA26 VDD
AA27 VSN
AA28 VDP
AA29 VSN
AA30 XO_P02_TXN[3]
AA31 XO_P02_TXP[2]
AA32 VDN
AA33 XI_P02_RXP[1]
AA34 XI_P02_RXN[0]
AB1 XI_P07_RXN[0]
AB2 XI_P07_RXP[1]
AB3 VDN
AB4 XO_P07_TXP[2]
Pin Name
AB5 XO_P07_TXN[3]
AB6 VSN
AB7 NC
AB8 VSS
AB9 VDE
AB10 VSS
AB11 VDD
AB12 VSS
AB13 VDD
AB14 VSS
AB15 VDD
AB16 VSS
AB17 VDD
AB18 VSS
AB19 VDD
AB20 VSS
AB21 VDD
AB22 VSS
AB23 VDD
AB24 VSS
AB25 VDD
AB26 VSS
AB27 VDN
AB28 VSN
AB29 VDN
AB30 XO_P02_TXP[1]
AB31 XO_P02_TXN[2]
AB32 VDP
AB33 XI_P02_RXN[1]
AB34 XI_P02_RXP[2]
AC1 XI_P07_RXP[0]
AC2 VDN
AC3 VSN
AC4 VDN
AC5 XO_P07_TXP[3]
AC6 VDN
AC7 NC
AC8 VDE
Pin Name
Table 15: Pin Listing (Continued)
MB8AA3020
32 Fujitsu Microelectronics America, Inc. Confidential
AC9 VSS
AC10 VDD
AC11 VSS
AC12 VDD
AC13 VSS
AC14 VDD
AC15 VSS
AC16 VDD
AC17 VSS
AC18 VDD
AC19 VSS
AC20 VDD
AC21 VSS
AC22 VDD
AC23 VSS
AC24 VDD
AC25 VSS
AC26 VDD
AC27 VSN
AC28 VDN
AC29 VSN
AC30 XO_P02_TXN[1]
AC31 XO_P02_TXP[0]
AC32 VDR
AC33 XI_P02_RXP[3]
AC34 XI_P02_RXN[2]
AD1 VDN
AD2 VSN
AD3 VDP
AD4 VSN
AD5 VDN
AD6 VSS
AD7 XI_VPD2
AD8 VSS
AD9 VDE
AD10 VSS
AD11 VDD
AD12 VSS
Pin Name
AD13 VDD
AD14 VSS
AD15 VDD
AD16 VSS
AD17 VDD
AD18 VSS
AD19 VDD
AD20 VSS
AD21 VDD
AD22 VSS
AD23 VDD
AD24 VSS
AD25 VDD
AD26 VSS
AD27 VDN
AD28 VSN
AD29 VDN
AD30 XO_P06_TXP[3]
AD31 XO_P02_TXN[0]
AD32 VSN
AD33 XI_P02_RXN[3]
AD34 XI_P06_RXP[0]
AE1 NC
AE2 NC
AE3 XI_RXD2[7]
AE4 XI_RXD2[6]
AE5 XI_RXD2[5]
AE6 XI_HTMODE
AE7 XI_RX_CLK2
AE8 VDE
AE9 VSS
AE10 VDD
AE11 VSS
AE12 VDD
AE13 VSS
AE14 VDD
AE15 VSS
AE16 VDD
Pin Name
AE17 VSS
AE18 VDD
AE19 VSS
AE20 VDD
AE21 VSS
AE22 VDD
AE23 VSS
AE24 VDD
AE25 VSS
AE26 VDD
AE27 VSN
AE28 VDP
AE29 VSN
AE30 XO_P06_TXN[3]
AE31 XO_P06_TXP[2]
AE32 VDN
AE33 XI_P06_RXP[1]
AE34 XI_P06_RXN[0]
AF1 XI_RXD2[4]
AF2 XI_RXD2[3]
AF3 XI_RXD2[2]
AF4 XI_RXD2[1]
AF5 VSS
AF6 XI_TX_CLK2
AF7 VSS
AF8 VDD
AF9 VDE
AF10 VSS
AF11 VDN
AF12 VSN
AF13 VDN
AF14 VSN
AF15 VDN
AF16 VSN
AF17 VDN
AF18 VSN
AF19 VDN
AF20 VSN
Pin Name
AF21 VDN
AF22 VSN
AF23 VDN
AF24 VSN
AF25 VDN
AF26 VSN
AF27 VDN
AF28 VSN
AF29 VDN
AF30 XO_P06_TXP[1]
AF31 XO_P06_TXN[2]
AF32 VDP
AF33 XI_P06_RXN[1]
AF34 XI_P06_RXP[2]
AG1 XI_RX_DV2
AG2 XI_RX_ER2
AG3 XI_CRS2
AG4 XI_RXD2[0]
AG5 VDD
AG6 VSS
AG7 XO_HTCLKO
AG8 XB_MDIO2
AG9 XI_TMS
AG10 VDE
AG11 VSN
AG12 VDN
AG13 VSN
AG14 VDN
AG15 VSN
AG16 VDN
AG17 VSN
AG18 VDN
AG19 VSN
AG20 VDN
AG21 VSN
AG22 VDN
AG23 VSN
AG24 VDN
Pin Name
Table 15: Pin Listing (Continued)
Chip Specification
Fujitsu Microelectronics America, Inc. 33Confidential
AG25 VSN
AG26 VDN
AG27 VSN
AG28 VDN
AG29 VSN
AG30 XO_P06_TXN[1]
AG31 XO_P06_TXP[0]
AG32 VDR
AG33 XI_P06_RXP[3]
AG34 XI_P06_RXN[2]
AH1 VSS
AH2 XI_COL2
AH3 VSS
AH4 VDD
AH5 XO_MDC2
AH6 XI_CONFIG[7]
AH7 VSS
AH8 XI_HTSCK
AH9 XI_TCK
AH10 VDP
AH11 VDN
AH12 XI_P15_REFCLKN
AH13 XI_P15_REFCLKP
AH14 VSN
AH15 VDP
AH16 XI_P15_CKVTT
AH17 VDN
AH18 VSN
AH19 VDN
AH20 VDP
AH21 VDN
AH22 XI_P14_REFCLKN
AH23 XI_P14_REFCLKP
AH24 VSN
AH25 XI_P14_CKVTT
AH26 VDP
AH27 VDN
AH28 VSN
Pin Name
AH29 VDP
AH30 VSN
AH31 XO_P06_TXN[0]
AH32 VSN
AH33 XI_P06_RXN[3]
AH34 VSN
AJ1 XO_GTX_CLK2
AJ2 VSS
AJ3 XO_TXD2[7]
AJ4 XO_TXD2[6]
AJ5 XI_VPD1
AJ6 XI_CONFIG[4]
AJ7 XI_CONFIG[5]
AJ8 XI_CONFIG[6]
AJ9 VSN
AJ10 VDN
AJ11 VSN
AJ12 VDN
AJ13 VSN
AJ14 VDN
AJ15 VSN
AJ16 VDN
AJ17 VSN
AJ18 VDN
AJ19 VSN
AJ20 VDN
AJ21 VSN
AJ22 VDN
AJ23 VSN
AJ24 VDN
AJ25 VSN
AJ26 VDN
AJ27 VSN
AJ28 VDN
AJ29 VSN
AJ30 VDN
AJ31 VSN
AJ32 VDN
Pin Name
AJ33 VSN
AJ34 VDN
AK1 VSS
AK2 XO_TXD2[5]
AK3 XO_TXD2[4]
AK4 VSS
AK5 XI_CONFIG[1]
AK6 XI_CONFIG[2]
AK7 XI_CONFIG[3]
AK8 VDN
AK9 VSN
AK10 XO_P11_TXN[1]
AK11 XO_P11_TXP[1]
AK12 XO_P11_TXN[3]
AK13 XO_P11_TXP[3]
AK14 XO_P15_TXN[1]
AK15 XO_P15_TXP[1]
AK16 XO_P15_TXN[3]
AK17 XO_P15_TXP[3]
AK18 XO_P19_TXN[1]
AK19 XO_P19_TXP[1]
AK20 XO_P19_TXN[3]
AK21 XO_P19_TXP[3]
AK22 XO_P18_TXN[1]
AK23 XO_P18_TXP[1]
AK24 XO_P18_TXN[3]
AK25 XO_P18_TXP[3]
AK26 XO_P14_TXN[1]
AK27 XO_P14_TXP[1]
AK28 XO_P14_TXN[3]
AK29 XO_P14_TXP[3]
AK30 XO_P10_TXN[1]
AK31 XO_P10_TXP[1]
AK32 XO_P10_TXN[3]
AK33 XO_P10_TXP[3]
AK34 VSN
AL1 XO_TXD2[3]
AL2 XO_TXD2[2]
Pin Name
AL3 VSS
AL4 XO_TDO
AL5 XO_IRQ_N[2]
AL6 XI_CONFIG[0]
AL7 VSS
AL8 VSN
AL9 XO_P11_TXN[0]
AL10 XO_P11_TXP[0]
AL11 XO_P11_TXN[2]
AL12 XO_P11_TXP[2]
AL13 XO_P15_TXN[0]
AL14 XO_P15_TXP[0]
AL15 XO_P15_TXN[2]
AL16 XO_P15_TXP[2]
AL17 XO_P19_TXN[0]
AL18 XO_P19_TXP[0]
AL19 XO_P19_TXN[2]
AL20 XO_P19_TXP[2]
AL21 XO_P18_TXN[0]
AL22 XO_P18_TXP[0]
AL23 XO_P18_TXN[2]
AL24 XO_P18_TXP[2]
AL25 XO_P14_TXN[0]
AL26 XO_P14_TXP[0]
AL27 XO_P14_TXN[2]
AL28 XO_P14_TXP[2]
AL29 XO_P10_TXN[0]
AL30 XO_P10_TXP[0]
AL31 XO_P10_TXN[2]
AL32 XO_P10_TXP[2]
AL33 VDN
AL34 VSN
AM1 XO_TXD2[1]
AM2 XO_TXD2[0]
AM3 XO_TX_EN2
AM4 VSS
AM5 VDD
AM6 VSS
Pin Name
Table 15: Pin Listing (Continued)
MB8AA3020
34 Fujitsu Microelectronics America, Inc. Confidential
AM7 XO_IRQ_N[1]
AM8 VDN
AM9 VSN
AM10 VDR
AM11 VDP
AM12 VDN
AM13 VSN
AM14 VDR
AM15 VDP
AM16 VDN
AM17 VSN
AM18 VDR
AM19 VDP
AM20 VDN
AM21 VSN
AM22 VDR
AM23 VDP
AM24 VDN
AM25 VSN
AM26 VDR
AM27 VDP
AM28 VDN
AM29 VSN
AM30 VDR
Pin Name
AM31 VDP
AM32 VDN
AM33 VSN
AM34 VDN
AN1 VDD
AN2 XO_TX_ER2
AN3 XB_SCL2
AN4 VDD
AN5 VSS
AN6 XO_IRQ_N[0]
AN7 XI_TDI
AN8 VSN
AN9 XI_P11_RXN[3]
AN10 XI_P11_RXP[3]
AN11 XI_P11_RXN[1]
AN12 XI_P11_RXP[1]
AN13 XI_P15_RXN[3]
AN14 XI_P15_RXP[3]
AN15 XI_P15_RXN[1]
AN16 XI_P15_RXP[1]
AN17 XI_P19_RXN[3]
AN18 XI_P19_RXP[3]
AN19 XI_P19_RXN[1]
AN20 XI_P19_RXP[1]
Pin Name
AN21 XI_P18_RXN[3]
AN22 XI_P18_RXP[3]
AN23 XI_P18_RXN[1]
AN24 XI_P18_RXP[1]
AN25 XI_P14_RXN[3]
AN26 XI_P14_RXP[3]
AN27 XI_P14_RXN[1]
AN28 XI_P14_RXP[1]
AN29 XI_P10_RXN[3]
AN30 XI_P10_RXP[3]
AN31 XI_P10_RXN[1]
AN32 XI_P10_RXP[1]
AN33 VDN
AN34 VSN
AP1 VSS
AP2 VDD
AP3 XB_SDA2
AP4 VSS
AP5 VDD
AP6 XI_TRST_N
AP7 XI_HTXRST
AP8 VDN
AP9 VSN
AP10 XI_P11_RXN[2]
Pin Name
AP11 XI_P11_RXP[2]
AP12 XI_P11_RXN[0]
AP13 XI_P11_RXP[0]
AP14 XI_P15_RXN[2]
AP15 XI_P15_RXP[2]
AP16 XI_P15_RXN[0]
AP17 XI_P15_RXP[0]
AP18 XI_P19_RXN[2]
AP19 XI_P19_RXP[2]
AP20 XI_P19_RXN[0]
AP21 XI_P19_RXP[0]
AP22 XI_P18_RXN[2]
AP23 XI_P18_RXP[2]
AP24 XI_P18_RXN[0]
AP25 XI_P18_RXP[0]
AP26 XI_P14_RXN[2]
AP27 XI_P14_RXP[2]
AP28 XI_P14_RXN[0]
AP29 XI_P14_RXP[0]
AP30 XI_P10_RXN[2]
AP31 XI_P10_RXP[2]
AP32 XI_P10_RXN[0]
AP33 XI_P10_RXP[0]
AP34 VDN
Pin Name
Table 15: Pin Listing (Continued)
Chip Specification
Fujitsu Microelectronics America, Inc. 35Confidential
7. Electrical Description7.1 Absolute Maximum Ratings
7.2 Recommended Operating Conditions
7.3 ESD Ratings
Table 16: Absolute Maximum Ratings
Parameter Symbol Ratings Units Notes
Power supply voltage 1.2V VDDVDNAVD
-0.5 to 1.8 V
2.5V VDEVDP
-0.5 to 3.6 V
Input Voltage 2.5V IO VI -0.5 to VDE + 0.5 (≤ 3.6) V
Storage temperature Tj -40 to 125 oC
Table 17: Recommended Operating Conditions
Parameter Symbol Min. Typ. Max. Units Notes
Power supply voltage 1.2V VDDVDNAVD
1.14 1.2 1.26 V
2.5V VDEVDP
2.37 2.5 2.63 V
H level input voltage 2.5V IO VIH 1.7 - VDE+0.3 V
L level input voltage 2.5V IO VIL -0.3 - 0.7 V
Operating temperature(Ambient)
TA 0 70 oC
Table 18: ESD Ratings
Parameter Terminal Symbol Min. Max. Units Notes
HBM XI_Pnn_TXP[3:0], XI_Pnn_TXN[3:0], XI_Pnn_RXP[3:0], XI_Pnn_RXN[3:0]
VESDH1 1000 - V
XI_Pmm_REFCLKP, XI_Pmm_REFCLKN, XI_Pmm_CKVTT, VDR
VESDH2 2000 - V
Other Terminals VESDH3 2000 - V
MM XI_Pnn_TXP[3:0], XI_Pnn_TXN[3:0], XI_Pnn_RXP[3:0], XI_Pnn_RXN[3:0]
VESDM1 100 - V
XI_Pmm_REFCLKP, XI_Pmm_REFCLKN, XI_Pmm_CKVTT, VDR
VESDM2 200 - V
Other Terminals VESDM3 200 - V
MB8AA3020
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7.4 Reference Clock Input (LVDS) Electrical Specifications
7.5 2.5V CMOS IO Electrical Specifications
Table 19: DC specification
Parameter Symbol Minimum Typical Maximum Unit Notes
Input Voltage Range Vir 825 - 1575 mV
Input Differential Threshold Vidth -100 - 100 mV
Differential Input Impedance Zref 80 100 120 W
Table 20: AC specification
Parameter Symbol Minimum Typical Maximum Unit Notes
Operation frequency Fref 156.25 − 100ppm 156.25 156.25 + 100ppm MHz
Duty Cycle Trefduty 40 50 60 % Defined as differential
Differential Skew Trefskew - - 200 ps
Rise / Fall Time Tr 100 - 700 ps 20% to 80%
Jitter Tjrefp - - 40 ps Peak to peak jitter
AC Common Mode Voltage ∆Vos - - 25 mVrms Rload = 100Ω ± 1%
Table 21: DC specification
Parameter Symbol Minimum Typical Maximum Unit Notes
Supply current IDDS V
H-level output voltage VOH VDE-0.2 - VDE V
L-level output voltage VOL 0 - 0.2 V
Pull up/Pull down resistance RP 25 kΩ
Chip Specification
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Table 22: AC specification for GMII Interface
Parameter Symbol Minimum Maximum Unit Notes
XO_GTX_CLK1 Frequency CLKGTX_CLK1 125 - 100ppm 125 + 100ppm MHz
XO_GTX_CLK2 Frequency CLKGTX_CLK2 125 - 100ppm 125 + 100ppm MHz
XI_RX_CLK1 Frequency CLKGRX_CLK1 125 - 100ppm 125 + 100ppm MHz
XI_RX_CLK2 Frequency CLKGRX_CLK2 125 - 100ppm 125 + 100ppm MHz
XO_TXD1, XO_ TX_EN1, XO_TX_ER1 Setup to XO_GTX_CLK1 tSETUP_GT1 2.50 ns
XO_TXD2, XO_ TX_EN2, XO_TX_ER2 Setup to XO_GTX_CLK2 tSETUP_GT2 2.50 ns
XI_RXD1, XI_RX_DV1, XI_RX_ER1 Setup to XI_RX_CLK1 tSETUP_GR1 2.00 ns
XI_RXD2, XI_RX_DV2, XI_RX_ER2 Setup to XI_RX_CLK2 tSETUP_GR2 2.00 ns
XO_TXD1, XO_ TX_EN1, XO_TX_ER1 Hold from XO_GTX_CLK1 tHOLD_GT1 0.50 ns
XO_TXD2, XO_ TX_EN2, XO_TX_ER2 Hold from XO_GTX_CLK2 tHOLD_GT2 0.50 ns
XI_RXD1, XI_RX_DV1, XI_RX_ER1 Hold from XI_RX_CLK1 tHOLD_GR1 0.00 ns
XI_RXD2, XI_RX_DV2, XI_RX_ER2 Hold from XI_RX_CLK2 tHOLD_GR2 0.00 ns
XO_GTX_CLK1 Time High tHIGH1 2.5 ns Cload = 5pF
XO_GTX_CLK2 Time High tHIGH2 2.5 ns Cload = 5pF
XO_GTX_CLK1 Time Low tLOW1 2.5 ns Cload = 5pF
XO_GTX_CLK2 Time Low tLOW2 2.5 ns Cload = 5pF
XO_GTX_CLK1 Rise Time tR1 1.0 ns Cload = 5pF
XO_GTX_CLK2 Rise Time tR2 1.0 ns Cload = 5pF
XO_GTX_CLK1 Fall Time tF1 1.0 ns Cload = 5pF
XO_GTX_CLK2 Fall Time tF2 1.0 ns Cload = 5pF
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AC specification for MDIO interface follows “IEEE P802.3ae”.
Table 23: AC specification for MII Interface
Parameter Symbol Minimum Maximum Unit Notes
XI_TX_CLK1 Frequency CLKTX_CLK1 25 - 100ppm for 100Mbps2.5 - 100ppm for 10Mbps
25 + 100ppm for 100Mbps2.5 + 100ppm for 10Mbps
MHz
XI_TX_CLK2 Frequency CLKTX_CLK2 25 - 100ppm for 100Mbps2.5 - 100ppm for 10Mbps
25 + 100ppm for 100Mbps2.5 + 100ppm for 10Mbps
MHz
XI_RX_CLK1 Frequency CLKRX_CLK1 25 - 100ppm for 100Mbps2.5 - 100ppm for 10Mbps
25 + 100ppm for 100Mbps2.5 + 100ppm for 10Mbps
MHz
XI_RX_CLK2 Frequency CLKRX_CLK2 25 - 100ppm for 100Mbps2.5 - 100ppm for 10Mbps
25 + 100ppm for 100Mbps2.5 + 100ppm for 10Mbps
MHz
XI_TX_CLK1 to XO_TXD1, XO_ TX_EN1, XO_TX_ER1 tDOUT1 25 ns
XI_TX_CLK2 to XO_TXD2, XO_ TX_EN2, XO_TX_ER2 tDOUT2 25 ns
XI_RXD1, XI_RX_DV1, XI_RX_ER1 Setup to XI_RX_CLK1
tSETUP_R1 10 ns
XI_RXD2, XI_RX_DV2, XI_RX_ER2 Setup to XI_RX_CLK2
tSETUP_R2 10 ns
XI_RXD1, XI_RX_DV1, XI_RX_ER1 Hold from XI_RX_CLK1
tHOLD_R1 0 ns
XI_RXD2, XI_RX_DV2, XI_RX_ER2 Hold from XI_RX_CLK2
tHOLD_R2 0 ns
Table 24: AC Specification for I2C Interface
Parameter Symbol
Standard Fast
UnitMin Max Min Max
SCL clock frequency fSCL 0 100 0 400 kHz
Hold time (repeated) START condition. After this period, the first clock pulse is generated
tHD;STA 4.0 - 0.6 - µs
LOW period of the SCL clock tLOW 4.7 - 1.3 - µs
HIGH period of the SCL clock tHIGH 4.0 - 0.6 - µs
Set-up time for a repeated START condition tSU;STA 4.7 - 0.6 - µs
Data hold time tHD;DAT 0 3.45 0 0.9 µs
Data setup time tSU;DAT 250 - 100 - ns
Rise time of both SDA and SCL signals tr - 1000 - 300 ns
Fall time of both SDA and SCL signals tf - 300 - 300 ns
Setup time for STOP condition tSU;STO 4.0 - 0.6 - µs
Bus free time between a STOP and START condition tBUF 4.7 - 1.3 - µs
Table 25: AC specification for reset signals
Parameter Symbol Minimum Maximum Unit Notes
Rise time of XI_RESET_N, XI_RESET_PLL_N, and XI_PWRGOOD TR_RESET 20 ns
Chip Specification
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7.6 HSIO Electrical SpecificationsTable 26: DC Specification
Parameter Symbol Minimum Typical Maximum Unit Notes
Transmitter Differential Output Impedance Ztd - 100 - W DC
Transmitter DC Common Mode Voltage Vtcmd 0 600 1300 mV
Transmitter Differential Output Voltage Vtamp 360 - 1600 mV differential peak-peak(determined by TX equalizer configuration parameters)
Receiver Differential Input Impedance Zrd - 100 - W DC
Receiver DC common Mode input (VDR) Volt-age
Vrcmd 700 750 800 mV
Table 27: AC Specification
Parameter Symbol Minimum Typical Maximum Unit Notes
Transmitter Output Data Rate Ftd 10.3125 -100 ppm 10.3125 10.3125 +100 ppm Gbps 10G serial mode
3.125-100 ppm
3.125 3.125 +100 ppm CX-4 mode
Transmitter Output Rise/Fall Time Ttrf 24 - - ps 20% - 80%(depends on the TX equalizer configuration parameters)
Transmitter Differential peak-to-peak output voltage difference
Vtdppd - - 150 mV lane-to-lane difference in CX-4 mode
Transmitter Differential Output Return Loss
SDD11 10 - - dB 0.1-0.625 GHz
A - - dB 0.625-3.943 GHz,A=10-10*Log10(F/0.625)
2 - - dB 3.943-10 GHz
Transmitter Output Total Jitter Ttj - - 0.3 UI 1UI=97.0ps, peak to peak
Receiver Data Rate Frd 10.3125 -100 ppm 10.3125 10.3125 +100 ppm Gbps 10G serial mode
3.125 -100 ppm 3.125 3.125 +100 ppm CX-4 mode
Receiver Differential Input Return Loss SDD11 9 - - dB 0.1-2 GHz
A - - dB 2-7.5 GHz,A=9-12.2*Log10(F/2)
Receiver Common mode Input Return Loss
SCC11 6 - - dB 0.1-2.5 GHz
Receiver Jitter Tolerance JT 0.65 - - UI
Receiver CDR Lock Up Time Trlock - - 60 µs
XFP Clock Output Frequency Fck - 10.3125/64 - GHz Frequency is exactly equal to the Baudrate/64.
XFP Clock Output Differential Amplitude
Vcamp 640 - 1600 mVpp
XFP Clock Duty Cycle Duty 40 50 60 %
XFP Clock Output Rise/Fall Time Tckrf 200 - 1250 ps 20% - 80%
XFP Clock RMS Random Jitter Sigma - - 10 ps Up to 100MHz
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7.7 Power Dissipation
7.8 Reset SequenceThe reset sequence is defined for the following external pins.
• XI_RESET_N
• XI_RESET_PLL_N
• XI_PWRGOOD
Figure 17 shows the reset sequence using these external pins and Table shows AC specification for the reset sequence.
Figure 17: Reset Sequence
Table 28: Power Dissipation
Parameter Symbol Min
Typical
Max Unit NotesXFIa
a. power consumption when all 10G ports are 10G serial.
XAUIb
b. power consumption when all 10G ports are XAUI.
Power Dissipation PD 18.6 18.0 W Total power dissipation
1.2V for core PVDD 7.3 W
2.5V for I/O PVDE 0.1 W
1.2V for HSIO SerDes PVDN 11.1 10.5 W XFI: Tx: default, Rx: 32/63c
XAUI: Tx: default, RX: bypass
c. DC gain is 32, and 1st gain is 64.
2.5V for HSIO SerDes PVDP 0.1 0.1 W
VDD, VDE, VDN, VDP, AVD
XI_PWRGOOD
XI_RESET_PLL_N
XI_RESET_N
external clocks and power must be stable
Tpg Tpll_res Tm_res
XI_Pmm_REFCLKP
XI_Pmm_REFCLKN
Chip Specification
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Table 29: Reset Sequence
Parameter Min. Value Max. Value Description
Tpg 0 µs N/A ≥ 0µs
Tpll_res 25 µs N/A PLL reset time.
Tm_res 200 µs N/A Master reset time.
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All company and product names are trademarks or registered trademarks of their respective owners.
Printed in U.S.A. 10GE-RM-21246-6/2007
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