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IEEE SYMBOL: TRUTH TABLE:
LOGIC GATE SYMBOL:
RTL SCHEMATIC:
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REALIZATION OF LOGIC GATES
AIM:
Write the VHDL code for logic gates and verify its functional response.
APPARATUS:1. Xilinx ISE Suite 1 .! version.. ISi" si"ulator#$odelSi" si"ulator.
THEORY:% logic gate is an ele"entary &uilding &loc' of a digital circuit. $ost logic gates have
t(o inputs and one output. %t any given "o"ent) every ter"inal is in one of the t(o &inaryconditions lo( *+, or high *1,) represented &y different voltage levels. -he logic state of ater"inal can) and generally does) change often) as the circuit processes data. In "ost logic
gates) the lo( state is approxi"ately ero volts *+v,) (hile the high state is approxi"atelyfive volts positive */0v,. -here are seven logic gates %2D) 34) 23-) 2%2D) 234) X34 and X234. 2%2D and 234 are also called as universal gates. AND GATE: -he %2D gate is so"eti"es called the 5 all or nothing gate6. 7or %2D gate operationinputs are %)8 and output is 9. If a high voltage appears at inputs % and 8) then the output isHI:H. 7or re"aining co"&inations of inputs output is L3W. OR GATE: -he 34 gate is so"eti"es called the 5 any or all gate6. 7or 34 gate operation inputs are%)8 and output is 9. If a lo( voltage appears at inputs % and 8) then the output is L3W. 7or re"aining co"&inations of inputs output is HI:H.
NOT GATE: %2 inverter is a single input device; it perfor"s no logic interaction function &et(eent(o varia&les.-he 23- circuit perfor"s the &asic logical function called inversion or co"ple"entation. -hat is (hy) it is also 'no(n as inverter. -he 23- circuit has only inputand one output. -he purpose of this gate is to give an output that is not the sa"e as the input.When a HI:H level is applied to an inverter) a L3W level appears at its output and viceversa. NAND GATE: 2%2D is universal gate. -he truth
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234 is universal gate. -he truth
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EXNOR GATE:-he uni=ue output of the X234 gate is a L3W only (hen an odd nu"&er of inputs are
HI:H. -he output of X234 gate is the co"ple"ent of X34 truth ta&le.VHDL PROGRAM:
1.AND GATE:
li&rary ieee;
use ieee.stdAlogicA11B!.all;use ieee.stdAlogicAarith.all;use ieee.stdAlogicAunsigned.all;entity andgate is port *%)8 in stdAlogic; C out stdAlogic,;end andgate;architecture Dataflo( of andgate is &egin C % and 8;end Dataflo(;
=================================================================* Fina R!"#$% *=================================================================4-L -op Level 3utput 7ile 2a"e andgate.ngr
-op Level 3utput 7ile 2a"e andgate
3utput 7or"at 2:C
3pti"i ation :oal Speed
Feep Hierarchy 2o
D!&i'n S%a%i&%i(&
G I3s
Cell sage
G 8ELS 1
G L - 1
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G I3 8uffers
G I8 7
G 38 7 1
-i"ing Detail
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IEEESYMBOL: TRUTHTABLE:
LOGIC GATE SYMBOL:
RTL SCHEMATIC:
(VLSI Laboratory-I) M.Tech-I Sem Sri Aditya Engineering College
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,.OR GATE:
li&rary ieee;
use ieee.stdAlogicA11B!.all;
use ieee.stdAlogicAarith.all;
use ieee.stdAlogicAunsigned.all;
entity orgate is
port *%)8 in stdAlogic;
C out stdAlogic,;
endorgate;
architecture Dataflo( of orgate is
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&egin
C % or 8;
end Dataflo(;
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TIMING DIAGRAM:
* Fina R!"#$% *
4-L -op Level 3utput 7ile 2a"e orgate.ngr -op Level 3utput 7ile 2a"e orgate
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3utput 7or"at 2:C3pti"i ation :oal SpeedFeep Hierarchy 2oD!&i'n S%a%i&%i(&G I3s
C! U&a'! :G 8ELS 1G L - 1G I3 8uffers G I8 7 G 38 7 1-i"ing Detail
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LOGIC GATE SYMBOL :
RTL SCHEMATIC:
+.NOT GATE:
li&raryieee;
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use ieee.stdAlogicA11B!.all;
use ieee.stdAlogicAarith.all;
use ieee.stdAlogicAunsigned.all;
entity notgate is port *% in stdAlogic;
8 out stdAlogic,;
end notgate;
architecture Dataflo( of notgate is
&egin
8 not % ;
end Dataflo(;
Fina R!"#$% *
4-L -op Level 3utput 7ile 2a"e notgate.ngr -op Level 3utput 7ile 2a"e notgate3utput 7or"at 2:C3pti"i ation :oal SpeedFeep Hierarchy 2o
Design StatisticsG I3s
TECHNOLOGY SCHEMATIC:
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TIMING DIAGRAM:
C! U&a'! :G 8ELS 1G I2V 1
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G I3 8uffers G I8 7 1G 38 7 1-i"ing Detail
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li&rary ieee;
use ieee.stdAlogicA11B!.all;
use ieee.stdAlogicAarith.all;
use ieee.stdAlogicAunsigned.all;entity norgate is
port *%)8 in stdAlogic;
C out stdAlogic,;
end norgate;
architecture Dataflo( of norgate is
&egin
C % nor 8;
end Dataflo(;
* Fina R!"#$% *
4-L -op Level 3utput 7ile 2a"e norgate.ngr -op Level 3utput 7ile 2a"e norgate
3utput 7or"at 2:C3pti"i ation :oal SpeedFeep Hierarchy 2o
Design StatisticsG I3s
TECHNOLOGY SCHEMATIC:
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TIMING DIAGRAM:
Cell sage (VLSI Laboratory-I) M.Tech-I Sem Sri Aditya Engineering College
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G 8ELS 1G L - 1G I3 8uffers G I8 7 G 38 7 1
-i"ing Detail
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IEEE SYMBOL: TRUTH TABLE:
LOGI GATE SYMBOL:
RTL SCHEMATIC:
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).NAND GATE:
li&rary ieee;
use ieee.stdAlogicA11B!.all;
use ieee.stdAlogicAarith.all;use ieee.stdAlogicAunsigned.all;
entity nandgate is
port *%)8 in stdAlogic;
C out stdAlogic,;
end nandgate;
architecture Dataflo( of nandgate is
&egin
C % nand 8;
end Dataflo(;
* Fina R!"#$% *
4-L -op Level 3utput 7ile 2a"e nandgate.ngr -op Level 3utput 7ile 2a"e nandgate3utput 7or"at 2:C3pti"i ation :oal SpeedFeep Hierarchy 2o
Design StatisticsG I3s
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C! U&a'! :G 8ELS 1G L - 1G I3 8uffers G I8 7
G 38 7 1-i"ing Detail
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IEEE SYMBOL: TRUTH TABLE:
LOGIC GATE SYMBOL:
RTL SCHEMATIC
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-.EX0OR GATE:
li&rary ieee;
use ieee.stdAlogicA11B!.all;
use ieee.stdAlogicAarith.all;
use ieee.stdAlogicAunsigned.all;
entity xorgate is
port *%)8 in stdAlogic;
C out stdAlogic,;
end xorgate;
architecture Dataflo( of xorgate is
&egin
C % xor 8;
end Dataflo(;
* Fina R!"#$% *
4-L -op Level 3utput 7ile 2a"e exorgate.ngr
-op Level 3utput 7ile 2a"e exorgate3utput 7or"at 2:C3pti"i ation :oal SpeedFeep Hierarchy 2o
Design StatisticsG I3s
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TECHNOLOGY SCHEMATIC:
TIMING DIAGRAM:
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C! U&a'! :G 8ELS 1G L - 1G I3 8uffers G I8 7
G 38 7 1-i"ing Detail
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IEEE SYMBOL: TRUTH TABLE:
LOGIC GATE SYMBOL:
RTL SCHEMATIC:
.EX0NOR GATE:
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li&rary ieee;
use ieee.stdAlogicA11B!.all;
use ieee.stdAlogicAarith.all;
use ieee.stdAlogicAunsigned.all;entity xnorgate is
port *%)8 in stdAlogic;
C out stdAlogic,;
end xnorgate;
architecture Dataflo( of xnorgate is
&egin
C % xnor 8;
end Dataflo(;
RESULT:
* Fina R!"#$% *
4-L -op Level 3utput 7ile 2a"e exnorgate.ngr -op Level 3utput 7ile 2a"e exnorgate3utput 7or"at 2:C3pti"i ation :oal SpeedFeep Hierarchy 2o
TECHNOLOGY SCHEMATIC:
(VLSI Laboratory-I) M.Tech-I Sem Sri Aditya Engineering College
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TIMING DIAGRAM:
Design StatisticsG I3s Cell sage
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G 8ELS 1G L - 1G I3 8uffers G I8 7 G 38 7 1
-i"ing Detail
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8EH%VI3 4%L 1 !.JJK +.JJB 1 +++ +.+J1
S-4 C- 4%L 1 !.JJK +.JJB 1 +++ +.+J1
EX34
D%-%7L3W 1 !.JJK +.JJB 1 +++ +.+J18EH%VI3 4%L*if, 1 !.JJK +.JJB 1 +++ +.+J1
8EH%VI3 4%L 1 !.JJK +.JJB 1 !+ ! +.+J1S-4 C- 4%L 1 !.JJK +.JJB 1 !+ ! +.+J1
EX234
D%-%7L3W 1 !.JJK +.JJB 1 +++ +.+J1
8EH%VI3 4%L*if, 1 !.JJK +.JJB 1 +++ +.+J1
8EH%VI3 4%L 1 !.JJK +.JJB 1 1!! +.+J1
S-4 C- 4%L*not)and)or, 1 !.JJK +.JJB 1 K!! +.+J1
S-4 C- 4%L*exor)not, 1 !.JJK +.JJB 1 K!! +.+J1COMPARISION TABLE:
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