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A HIGH RESOLUTION DIGITAL CM OS TIME-TO-DIGITAL CONVERTER
BASED ON NESTED DELAY LOCK ED LOOPS
Antti Mantyniemi Timo Rahkonen Juha Kostamovaara
University of Oulu, Electronics laboratory, Department of Electrical En gineering and Infotech Oulu
Linnanmaa, FIN-90570 OULU , FINLAND
ABSTRACT
This paper describes an integrated digital CMOS time-to-digital
converter, TDC , with sub-g ate-de lay LSB width and SO ps single
shot resolution which equals 7 mm in time-of-flight laser range-
finding measurement. The circuit was fabricated in an 0.8 pm
standard digital CMOS process. The measurement is based on a
counter and a novel two step parallel interpolation that uses only
32 delay elements in two nested 16 element delay locked loops to
provide 128 LSBs in the interpolator that resolves the timing
within the reference clock cycle. The T DC has a fast conversion
rate because of flash principle and requires no external calibration
because the delay elements used for timing have been delay locked
to the reference clock period. This TDC also has a very good
temperature stability of 0.03 ps/ C and a low current consum ption
of
<
20 mA from a
+5
V supply.
1
INTRODUCTION
An integrated digital CMOS time-to-digital converter (TDC) was
designed to be used in a pulsed time-of-flight (TOF) laser range-
finder. Th e circuit measures the transit time of the light pulse from
a laser to the target and back to a light detector.
The single-shot resolution of timing detection in laser range-
finding applications depends on the signal-to-noise ratio and rise
time of the timing pulses and is typically around 100 ps
[l].
If the
measuring instants are asyn chron ous to the measurement time
base, the resolution can be improved in proportion to
I d N
by
taking an average of
N
successive measurements [2]. Because the
rate of this improvement is slow it is desira ble that the resolution
of the time measurement is better than the resolution of the timin g
detection. Hence, a time dig itizer with a single-shot resolution 0
value of about SO ps was d esign ed here.
Several methods exist to reach resolution better than the de lay of a
basic noninverting gate normally used as a time unit in digital
interpolators using digital CMOS technology. A TDC with
comparable resolution has been reported in [3],but uses a principle
where an array of 168 delay elements
is
used to achieve the same
resolution with the same reference clock frequency. It is also
possible to use two parallel delay lines with different unit delays
[4]. The resolution is then determin ed by the difference of the unit
delays. This approach would require two delay lines with 128
delay elements in each to give comparable resolution. Both of
these two methods suffer from the large amount of circuitry
needed for realization of a TDC. As the number of delay elements
needed increases, the power consumption and the cumulative
nonlinearities of the interpolators increase as well. One approach
is to apply the vernier principle to the delay line interpolation by
locking the delay of the delay line to an odd harmonic of the
reference clock cycle [ 5 ] This m akes it possible to increase the
clock frequency and thus improve the resolution, but each
LSB
within the reference clock cycle is still represented by a delay
element and increasing the clock frequency increases the power
consumption.
Even though a one channel TDC is described in this paper, the
architecture of the circuit was designed
so
that it can easily be
extended to have multiple stop channels. Such a multichannel
TD C can then be used e.g. in 3D-imaging lidar systems based on
time-of-flight laser range-finding [ 6 ] ,
7]
2. CIRCUIT ARCHITECTURE
Th e TDC described and implemented h ere is based on a counter
and a novel parallel two step interpolation method based on nested
delay locked loops. This makes it possible to digitize a reference
clock cycle with 128 steps using only 32 delay elements. It also
helps to minimize the interp olator nonlinearities and power
consumption.
The conceptual timing diagram of the new TDC principle is
presented in Fig. 1. The m easurement ra nge is extended to over 2
ps
a few hundred meters in distan ce in laser range-finding, using
an 8-bit counter that is clocked by the 85 MHz reference clock.
Th e counter digitizes the time-of-flight with a resolution of -12 ns,
71
in Fig.
I .
The counter is started by a ST ART pulse from the laser
diode and the state of the counter is stored by a ST OP pulse from
the optical receiver. The first coarse interpolator consists of a 16
eleme nt delay line, 8 element delay lin e in Fig. 1 for clarity, that is
delay locked to the cycle of the reference clock. This provides 1 6
different phases of the reference clock. As the state of the
interpolator is stored by the START and STOP pulses, the
interp olator actually measures the ph ase difference between the
next rising edge of the reference and the ST ART and ST OP pulses
with a resolution of a few hundred ps, 72 in Fig. 1. As the input
signal, START or STOP, samples the state of the delay line to
resolv e the reference cloc k phase propagating in the delay line, the
16 phases of the reference clock in the de lay line interpolator at the
same time synchronize the input signal as if it was synchronized to
a clock with a frequency 16 times the reference clock frequency,
i.e. over
1 GHz.
The first synchronized signal rising is found by a
16-in put wired-OR ga te, the output of which is fed as a strobe
signa l to the fine interpola tor as seen in the block diagram in Fig.
2.
The phase difference between these synchronized pulses,
STARTSYNC and STOPSY NC, and the actual START and STO P
pulses is measured using two fine interpo lators that span over two
phases of the coarse interpolator. Th e unsynchronized input signal
propagates through the 16 branches
of
the fine parallel interpolator
with < 1 ps delay difference. When thes e
16
signals are sampled
with the synchronized input signal, we can determine the arrival
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moment of the input signal within the coarse delay line
interpolator with a resolution better than 100 ps, 23 in Fig. 1.
Instead of having a dedicated delay element for each digitized
LSB, we reuse the elements of the fine interpolators 16 times
within the reference clock cycle. The measurement result, Tmeas
in Fig. 1, is obtained by combining the results from the counter and
the two interpolators (T1 1, T12, T21, T22 in Fig. 1). The T DC
described here is basically a flash converter where the states of the
counter and the interpolators are sampled with the input signals.
Th e measurement result is available as soon as the stop pulse has
arrived thus enabling fast conv ersion rate.
Tmeas
4
b:
REFCLK21
START
, , \
STOP
. b
21
STOPSYNC
-?,I 22
0
\
COUNTER
1 :
n X '
1
/
DELAY LIN
=
21 / 16
START FINE
STOP FINE
:'Ti2
23 = 2*22 / 16 = 21 / 128
Figure
1. Conceptual timing diagram.
COARSE SERIAL
INTERPOLATOR
REFCLK
START
STO P
I
I
I
S T A R T 4
STO P 1
I
I
fi=T- >YNC 16-OR x 4 bit
I
I FINE PARALLEL
I INTERPOLATORS
I - x 4 bit
-+
I I
I I
Figure
2. Block diagram.
3.
NESTED DELAY LOC KED LOOPS
The co arse delay line consists of 16 delay elemen ts, 22 in Fig.
3,
in series and is delay locked to the reference clock and w orks as
the outer loop in the nested delay locked loops. Th e absolute gate
delay is used as the time unit. In the fine interpolators the delay
elements, 23 in Fig. 3 are connected in parallel.
A
delay element
with one load transistor and an other one with seventeen load
transistors in the fine interpolators are used as reference points in
the other inner delay locked loops used for locking the fine
interpolators continuously to two delay units of the coarse delay
line interpolator providing < 100 ps LSB width. The delay scaling
is done by scaling the MOS load capacitance of the first inverter as
the delay of an inverter is proportional to the load capacitance. The
gate propagation delay difference is used as the time unit in the fine
interpolator. The g ate delays are adjusted by current starving the
first inverters in the delay elements. The delay locking provides
continuous calibration of the measurement. The delay locking
principle is presented in Fig.
2.
Ideally the eight middle elements
of the fine interpolators are used for measuring purposes, see Fig.
1, whereas four elements at the edges allow for timing m ismatches
between the synchronized and unsynchronized input signal paths
caused by process and temperature variations.
I I I
22 23
Figure 3. Delay elements 22 and 23
4. INPUT SYNCHRONIZATION
Because the start and stop timing signals are asynchronous with
respect to the reference clock and the clock phases propagating in
the delay line interpolator, careful synchronizations schemes m ust
be employed. T he input signals can not be arbitrarily synchronized
to the next propagating clock phase because there exists a risk of
violating the flip-flop setup time, which in turn would affect the
flip-flop propagation delay or even cau se metastable behaviour.
Fig. 4 shows an example of a simulation of the flip-flop delay
change as a function of the input signal setup time. The arrival
moment of th e input signal D is swept with respect to the clock
signal C by
50
ps with a step of 2 ps. The delay from the clock edge
to the flip-flop output Q changes more than 1 ns because of the
setup time violation. Clearly this would affect the linearity of the
time-interval measurement. Therefore we use the latches that store
the state of the delay line interpolator as guides to select which
of
the clock edges is a safe o ne to synchronize the input signal to.
According to the worst case simulations the output of a latch will
settle to either of its stable states in about 4 ns even when the setup
time has been violated. Fig. 5 shows an example of the behaviour
of the latch output when the setup time has been violated. The
input signal D am val mom ent is swept with respect to the clock
signal
e
ov er a period of 20 fs with a step of 1 fs leading to
metastable behaviour of the output signal Q.
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Figure
4.
Flip-flop propagation delay change.
5
4
3
[V
2
1
0
Figure 5. Latch metastable behaviour.
If we wait for lon ger than the time it takes
a
latch to settle , six times
~2 in this circuit - 4.5 ns, we can use the latches to select th e clock
phase that provides synchronization with a reduced probability of
error. Fig.
6
shows an example in which signal IN (START or
STOP) am ves ust before the rising edge of the clock phase 0 1 n
the delay line interpolator.
O
@
4
@2
@ 3
@5
@6
I
I1
@7
I
I
I I I
IN
INSYNd
DL151bJ
I
fh
I
Waiting time before synchronization
Phase difference to be measured
with fine parallel interpolator
Figure 6. Synchronization principle timing diagram.
After the latch propagation delay the signal DLl, the inverted
output of the latch, is the first one to settle to logic 1 thus enabling
the clock phase 0 7 o synchronize the input signal with flip-flop
output signal DF7, a s seen in Fig. 7 to provide the signal INSYNC
which will be used to sample the unsynchronized input signal
propagating in the fine interpolator. This synchronization p rinciple
generates a difference signal that has the cycle and the amplitude
of the delay element 22 as seen in Fig.
8.
The additional delay
caused by the waiting time in the synchronization must be
compensated for in the propagation delay of the input signal to the
fine interpolator.
R EF
CLK
DELAY LINE INTERPOLATOR
- - - .
O
@ l
DF15
U
U U
DF6 DF7 DFS
Figure 7.
Synchronization principle circuit diagram.
Waiting time for the latches to settle
to allow setu p time for the flip-flops
t
I I I I
I
I I I
I +
I 0 @ l @ 2 @ 3 @4 D5
Delay from IN to reference clock phases (@O:@lS)
Figure 8
Difference signal characteristics.
5 MEA SUREM ENT RESULTS
The circuit was designed for the Austria Mikro System e
0.8
p
digital single poly, double metal CMOS process. The layout area
is 3.1 x 2.2 mm2 including pads. Special attention was paid to
match the propagation d elays and signal slopes to reduce the effect
of systematic errors to the interpolators and delay locked loops.
Also the propagation delays in the start and stop channels were
carefully matched to reach goo d temperature stability.
The measurements were carried out using an external 85 MHz
reference clock giving 92 ps LSB width reliably in the temperature
range from -30 C to +60 C.
In all
the measurements the
CMOS
level start and stop signals were asynchronou s with respect to the
reference clock.
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The coarse serial delay line interpolator was characterized by
collecting the start and stop signal hits to the 16 delay elements and
determining from there the differential and integral nonlinearities
of the interpolator. Fig.
9
shows that the typical DNL of the
interpolator is less than 1 0 ps and the cumulative error of the INL
is no more than 25 ps. Because th e serial delay line interpolator is
used for synchronizing the input signals to provide a strobe signal
for the fine parallel interpolator the cumulative errors in the serial
delay line should be less than 46 ps i.e. half the LSB width of the
fine interpolator.
500 5 IO 15
DELAY ELEM ENT DELAY ELEM ENT
Figure
9.
Coarse delay line DNL and INL.
The fine interpolator was tested by collecting the start and stop
signal hits in the 16 elements of the fine interpolator. The hits are
distributed to 9 elements as expected, as shown in Fig.
10.
The
typical deviation from the ideal 9 2 ps channel width is 20 ps which
is well below half an LSB width. Furthermore, Fig. 10 shows how
the timing between the input signal propagating in the fine
interpolator and the strobe signal from the coarse interpolator
changes only about 20 ps in the whole m easured temperature range
moving the distribution to the right towards the last element of the
fine interpolator.
START, T = +60 “C START, T = -30 “C
_ _
DELAYLEMENT
DELAY ELEME NT
Figure 10. Fine interpolator histograms.
Fig.
11
shows the measurement result distribution
of
a measured
constant delay of about 1 11s. 99.9
of
the results are distributed
to three adjacent LSBs and all measurement results are distributed
to five LSBs. The typical single shot resolution sigma value of the
measurements is 50 ps. Temperature stability of the T DC chip w as
determined by measuring constant time d elays in the temperature
range from -30 “C to +60 “C. The temperature dependence was
measured to be 0.03 ps/”C. The current consumption of the circuit
is
<
20 mA from a single
+5
V supply.
6
SUMMARY
This paper describes a TDC implemented in a standard digital
CMOS process. The measurement is based on a counter and a
novel two step parallel interpolation based on nested delay locked
loops which reduces the number of the delay elements needed for
time digitization. The typical single-shot resolution o -value is 50
18
I
I08~/0
10875 l o a 8 5HANNEL (LSB) 10890 10895
Figure
11.
Measurement result distribution.
ps which equals 7 mm in distance measurement. Th e TDC has a
fast conversion rate because of flash principle and requires no
external calibration because the delay elements used for timing
have been locked to the reference clock. Thi s TDC also has a very
low temperature dependence of 0.03 ps/”C and a low current
consumption of
<
20 mA from a
+5
V supply.
7.
ACKNOWLEGMENT
This work was supported by the Academy of Finland which is
gratefully acknowledged.
8. REFERENCES
[11 K. Maatta, J. Ko stamova ara and R. Myllyla, “Time-to-Digital
Converter for fast, accurate laser rangefinding”, Proc. SPIE
International Conference on Industrial Inspection (EC Ol) , pp.
60-67, September 19 88, Hamburg.
[2] Hewlett-Packard, “Fundamentals
of
Time Interval
Measurements”, Application N ote 200-3.
[3] M. M ota, J. Christiansen: “A four ch annel self-calibrating, high
resolution, Time To Digital Converter”, Proc. ICECS 1998, vol
1, pp. 409-412, S eptember 1998, Lisboa, Portugal.
[4] T.Rahkonen,
J
Kostamovaara, “The Use of Stabilized CMOS
Delay Lines in the Digitization of S hort Time Intervals”,
IEEE
Journal of Solid State Circuits, vol. 28, no. 8, pp. 887-894,
August 1993.
[5] M.
S.
Gorbics,
J
Kelly, K. M. Ro berts and R. L. Sumner, “A
High Resolution M ultihit Time to D igital Converter Integrated
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[6] R. Myllyla, J. Marszalec, A. Mantyniemi, J Kostamovaara, S.
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[7] A. Mantyniemi, T. Rahkonen and
J
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