ZVxPlus Application: Transistor Characterization, Reliability and Model Verification

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ZVxPlus Application: Transistor Characterization, Reliability and Model Verification April 2009

Transcript of ZVxPlus Application: Transistor Characterization, Reliability and Model Verification

Page 1: ZVxPlus Application: Transistor Characterization, Reliability and Model Verification

ZVxPlus Application:Transistor Characterization,

Reliability andModel Verification

April 2009

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Outline

The Device Under Test (DUT): EPA120B-100P Measurement Setup “Fire and Go...” Calibration and Deembedding Process DC IV Application DC+RF Measurement

• Frequency Domain• Time Domain• Terminating Impedances

Advanced Display: Dynamic lines Model Verification Conclusions

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EPA120B-100P

EPA120B-100P• high efficiency heterojunction power FET• power output: + 29.0dBm typ.• power gain: 11.5dB typ. @ 12 GHz

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Measurement Setup

Port 1 Port 2

DUT

Synchroniser

Port 3Excitation

Source a1

20 dB

b1 a2b2 a3

Vg Vd

20 dB

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“Fire and Go...”

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DUT properly working? (1)

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DUT properly working? (2)

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Next Step?

Calibration

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DC Calibration

Port 1 Port 2

Synchroniser

Port 3ExcitationSource a1

20 dB

b1 a2b2 a3

Vg Vd

20 dB

Load

Load

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RF Calibration

Port 1 Port 2

Synchroniser

Port 3ExcitationSource a1

20 dB

b1 a2b2 a3

Vg Vd

20 dB

OSMPWMHPR

OSM

T

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DUT in pinch off?

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i1(t) i2(t)

v2(t)

Cal Plane A2Cal Plane A1

v1(t)

Some words about deembedding

The DUT is placed on a PCB

→ using calibration plane A1 and A2 we measure the behaviour of the DUT AND PCB

→ using Multiline TRL (thru-reflect-line) we move the calibration plane to the DUTwe measure the behaviour ONLY of the DUT

i1(t) i2(t)

v1(t) v2(t)

Cal Plane B2Cal Plane B1

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Some words about deembedding

Include package

Using the FET Model, provided by the manufacturerthe package can be included

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DUT in pinch off (with deembedding)

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ICE DC IV Application

Capability to force the control variablesin the calibration plane

Defining limits atDC source andin calibration plane

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ZVxPlus: Frequency Domain Characterisation - Phase

amplitude phaseVgs

=-0.6V, Vds

=5V f0=1GHz

Pin=-25dBm Pin=0dBm

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ZVxPlus: Time Domain Characterisation

b1

a1

Pin=-25dBm

Pin=0dBm

Vgs

=-0.6V, Vds

=5V f0=1GHz

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ZVxPlus: Time Domain Characterisation – Pinch OffV

gs=-1.3V, V

ds=5V f

0=1GHz

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ZVxPlus: Terminating Impedances

Output Impedance with 50 Ohm terminationat fundamental and 2 harmonics

Output Impedance with Open terminationat fundamental and 2 harmonics

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ZVxPlus: Dynamic Loadline

Compare the static Vgate

with the dynamic Vgate

through color Z-axis

Vgs

=-0.6V, Vds

=4V f0=1GHz Pin = 0 dBm

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ZVxPlus: Dynamic Gm and Input CapacitanceDynamic Gm

“Dynamic Input Capacitance”

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Exporting Measurements

a1(f)b1(f)a2(f)b2(f)

CITIfile ADS

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Model Verification in ADS

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Measurement vs Simulation

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Conclusions

Prepare measurement setup and ICE Calibration steps Deembedding capability DC and RF Transistor Characterization Basic Displays Advanced Displays: Dynamic Lines Model Verification