Zero-Energy Sag Corrector With Reduced Device Count

1646 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 6, JUNE 2009

Zero-Energy Sag Corrector With ReducedDevice Count

Anish Prasai, Student Member, IEEE, and Deepak M. Divan, Fellow, IEEE

Abstract—Voltage sags are the leading cause of unscheduleddowntime in industrial plants with high levels of automation.Zero-energy sag correctors (ZESCs) that utilize energy from thosephases that have sufficient remaining voltage on them promise lev-els of protection that are comparable with conventional energystorage based sag correctors, but in a more compact package. Thispaper presents a ZESC topology with reduced device count usingreadily available device packages that can realize similar perfor-mance as the original ZESC circuit. The proposed ZESC behaveslike a “thin ac converter,” and can be integrated with existing assetssuch as transformers and switchgears. This paper presents detailsof the operation, design, and experimental results for such a ZESCcircuit.

Index Terms—AC–AC boost, power disturbance statistics,power quality, voltage sags, zero-energy sag corrector.

I. INTRODUCTION

Y EARS of data collection have confirmed that voltage sagsrepresent the most common type of disturbance on the

power grid [1]. Caused by faults on the system ranging fromlightning strikes to squirrels entering transformers, voltage sagsare the leading cause of unscheduled downtime in highly auto-mated industrial plants. A whole line of voltage sag correctorproducts are commercially available based on the dynamic sagcorrector or the dynamic voltage restorer (DVR) [2]–[4]. In bothcases, the sag corrector requires significant amount of storedenergy and often requires low-frequency magnetics. This hasresulted in large size and high cost and has limited the marketpenetration of this type of equipment. There have been papersthat analyze the potential for using classical dc–dc convertersas direct ac/ac converters for sag and swell correction [5]–[9].However, their ability to correct deep, asymmetrical sags islimited.

Data from monitoring thousands of locations on the powergrid clearly confirm that the vast majority of sag events areasymmetrical in nature, reflecting the physical cause of the dis-turbance. In a previous paper, the authors have analyzed thetype of disturbance using data from www.i-grid.com [10], [11],the impact on the equipment to be protected, and the amountof energy required to provide ride-through to typical industrialloads [12], [13].

Manuscript received October 22, 2008; revised January 27, 2009. Currentversion published June 10, 2009. This paper was presented in part at The IEEEPESC 2008 Conference, Rhodes, Greece, June 15–19, 2008. This study wassupported by the Intelligent Power Infrastructure Consortium (IPIC), GeorgiaInstitute of Technology, Atlanta, GA. Recommended for publication by Asso-ciate Editor J. H. R. Enslin.

The authors are with the School of Electrical and Computer Engineer-ing, Georgia Institute of Technology, Atlanta, GA 30318 USA (e-mail:[email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2009.2015319

Fig. 1. (a) Single-phase direct matrix converter and (b) single-phase ZESCconverter with three ac switches.

The somewhat surprising result showed that over 96% ofdisturbances have at least 50% remaining voltage in two of thephases. This in turn led to the concept of the zero energy sagcorrector (ZESC), which uses remaining voltage in the phasesto synthesize the output voltage in order to prevent load tripping[12], [13]. A single-phase ZESC is shown in Fig. 1(b). Thecircuit is configured as a cross-phase boost ac/ac converter andis seen to use three bidirectional ac switches realized typicallyusing six gate turn-OFF devices like IGBTs.

It is important to understand the basis for the design of suchZESC systems. The typical approach in engineering product de-sign is to use the worst case conditions that are anticipated andto establish design specifications accordingly. For protectionagainst disturbances that follow a normal distribution, it is pro-hibitively expensive to design for protection against all possibleevents. In such cases, a mix of protection and self- or outsideinsurance is used to meet the financial impact caused by theinfrequent occurrences. This is true for diverse protection func-tions ranging from automobiles to lightning to power reliability.Cost-effective and affordable protection then becomes an issueof understanding the probability of an out-of-range event occur-ring and the cost of protecting against such an occurrence. In thecase of voltage sag correctors, the issues to consider include theprobability, severity and phase distribution of the disturbancesat a given location, the current profile of the load includingstart-up and peak currents, as well as sustained operating cur-rent levels. For instance, [13] showed that the probability ofshort-duration peak load coinciding with a deep and symmetri-cal voltage sag is extremely low and that protection against suchevents did not make sense if it added significant cost to the unit.Taking a system-driven protection philosophy allows the realiza-tion of cost-effective and novel-form factors for sag correctors.This paper presents a cost-effective voltage sag corrector that is

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PRASAI AND DIVAN: ZERO-ENERGY SAG CORRECTOR WITH REDUCED DEVICE COUNT 1647

Fig. 2. Various realizations of ac switches.

compact, can be integrated into diverse assets that are currentlybeing used in industry, and can be scaled to meet low-voltageend-user needs in the industrial and commercial sectors.

II. DIRECT AC/AC CONVERTERS

Direct ac/ac conversion is well known and provides an al-ternative to more conventional ac/dc/ac converter systems thatutilize multiple power conversion stages. Although direct ac/acconverters using gate turn-OFF ac switches, or matrix convert-ers as they are often called, have been known for over 20 years,their use in industry has been very limited. This is because of theneed to have switches that conduct current and block voltage in abidirectional manner, switches that are not easily realized usingavailable power semiconductor technology. This has forced therealization of the ac switch with two series-connected unipo-lar switches, such as MOSFETs or IGBTs. As a consequence,a three-phase to single-phase matrix converter realization, asshown in Fig. 1(a), requires six unipolar switches, in additionto capacitive and inductive filter elements. The switches canbe controlled using pulse width modulation (PWM) techniquesthat are well known to one skilled in the art.

For applications that require only a line-conditioning functionand do not require a change in frequency, simpler topologies maybe realized. Recent disclosures and publications show methodsfor realizing a “zero-energy sag corrector” (ZESC), using sixunipolar gate turn-OFF devices like IGBT per phase, as shownin Fig. 1(b). The ZESC converter provides a cross-phase boostfunction, allowing the output voltage to be maintained evenunder severe input voltage sag conditions.

All the direct ac/ac converters, including the ZESC, haveused one of four switch implementations, as shown inFig. 2(a)–(d), although the implementation in Fig. 2(d) is rarelyused. Control of the switch transitions is complicated by diodereverse recovery and minimum deadtime issues. Complex se-quences have been developed based on sensing the polarity ofthe switch voltages and currents. Further, to handle inevitabledelays in timing (necessary to prevent shoot-through conduc-tion of the devices), one has to use snubber circuits that cantrap and usually dissipate the trapped energy. Fig. 3 shows anexample of a dissipative snubber circuit that can be used withan ac chopper circuit. Energy losses in the snubbers represent asignificant problem.

Finally, if one looks at the implementation of the ac/ac con-verters, it becomes clear that conventional implementations re-quire isolated IGBT switches and cannot utilize the commonlyused form factor of a “dual IGBT module,” where two IGBTs

Fig. 3. Dissipative snubber circuit used in an ac chopper circuit.

Fig. 4. Proposed four-device ZESC topology shown for Phase A.

and reverse conducting diodes are stacked so as to realize a dc/acinverter pole, one of the most commonly available configura-tions. The need to procure form factors that are not commonlyavailable has also been a severe limitation in the ability to realizea direct ac/ac converter at a low cost.

III. PROPOSED FOUR-SWITCH ZESC

Due to limited availability, long lead time, and higher costassociated with ac switches, the ZESC topology that employstwo standard IGBT duals, as shown in Fig. 4, is proposed. Asingle-phase diode bridge comprising of diodes D7 − D10 isconnected to phase B and C, which rectifies the line-to-linevoltage and establishes a positive and a negative rail. Two smallcapacitors, CS1 and CS2 , are placed on the two rails to act assnubbers during switch transitions and to store small amountsof energy when the polarity of the current in the inductor, LF ,is not the same as the polarity of the phase voltage, VAN . Thelatter function is explained shortly. Diodes D5 and D6 provide abidirectional flow of current to the output. An ac filter capacitor,CF , is utilized before the load.

To prevent the filter inductor, LF , from saturating, volt–second balance is maintained during the control of the converterand is given by the following equations:

VAN − DVAO − (1 − D)VNEG = 0 V refAN > 0 (1)

VAN − DVAO − (1 − D)VPOS = 0 V refAN < 0. (2)

When solving for the duty cycle D, the variable VAO , isreplaced by the respective phase reference voltage, V ref

AN in (1)and (2).

The behavior of each of the switches is different dependingon the quadrant and mode of operation. There are four different


TABLE IQUADRANT AND MODES OF OPERATION AND THE RESPECTIVE

ACTIVE DEVICES

quadrants and two modes of operation. The active devices foreach combination of the quadrant and mode are given by Table I.

Under normal operating conditions, i.e., when the input volt-age is within normal bounds, switches S2 and S3 are gated ondepending on the current polarity of the inductor current ILA .When a voltage sag event is detected, the mode of operationis changed, and a boost mode is initiated. For instance, whenthe input voltage and current both are positive, turning on S3and S4 applies the more negative of the line voltages, VB orVC , to the inductor at the point VX . The inductor voltage thenbecomes VA − VX , causing the current ILA to increase. Turningoff S4 now forces the current to flow into the output capaci-tor CF , demonstrating a “boost converter” action. Similarly, forthe case when input voltage and current both are negative un-der voltage sag conditions, the converter would cycle betweenhaving S2 and D5 conducting and having S1 and S2 conduct.The voltage VX under this condition would be the most positiveof the voltages VB or VC , and the inductor voltage would beVA − VX .

A more complex mode of operation occurs when the ZESC isoperating in a quadrant where the polarity of the line voltage isdifferent from the polarity of the line current. With VAN positiveand ILA negative, to get the boost function, it is necessary toswitch VX between the negative rail and the output. This occurswith D3 and D4 conducting, charging the capacitor CS2 , reversebiasing the diodes D9 and D10 , and then discharging to theoutput capacitor CF through S2 and D5 . A similar cycle can bedescribed for the case when VAN is negative and ILA is positive.Here, the boost mode occurs when VX switches between thepositive rail and the output. To get to the positive rail, diodes D1and D2 must conduct in the boost mode, charging the capacitorCS1 , reverse biasing diodes D7 and D8 , and then dischargingto the output capacitor CF through S3 and D6 in the normalmode. The charge on the capacitors CS1 and CS2 can be resetwhen the converter goes back to operating in quadrant 1 and 3.The proposed converter cannot handle continuous regenerationwithout having a dissipative snubber to discharge CS1 and CS2 .

A simple feed-forward control algorithm to calculate the nec-essary duty cycle for each of the four switches is outlined inFig. 5(a). Until a voltage sag event is detected on the input side,the switches S2 and S3 are conducting continuously such thatwhatever appears on the input goes through to the output. Whena sag event is detected, then appropriate duty cycle is applied to

Fig. 5. (a) Feed-forward control algorithm for controlling the switches witha duty cycle D and (b) a simplified switching behavior measured at VX withreference to neutral.

the appropriate switches based upon the quadrant of operation.Feedback control topology is not shown, but a simple PI con-troller should be adequate enough to track the reference voltagefairly well.

Simplified sketch of the characteristic waveform of VX isshown in Fig. 5(b). The input voltage VAN has dropped to 0.0 perunit (p.u.), while voltages VBN and VCN have dropped to 0.8 p.u.The output voltage VAO is maintained at 1.0 p.u. by boosting theinductor at the rail of the opposite polarity and then dischargingit to the output capacitor CF . The sketch assumes that the inputvoltage is always of the same polarity as the inductor currentand that switches are ideal such that the snubber capacitors CS1and CS2 are not utilized.

Fig. 6 shows simulation waveforms of a 10 kW system, con-firming that the converter can implement the desired ZESCfunction. In the simulation, phase A drops to 0.0 p.u., whilephase B and C drop to 0.5 p.u. The output waveform looks lessthan ideal because only a simple feed-forward control describedin Fig. 5(a) is utilized. However, for most applications, such asimple control is adequate enough to sustain the load for thesplit second duration of a sag event.

The proposed circuit exhibits some important benefits whencompared with the original ZESC system, as well as with othersag correctors. The total device count has been reduced to fourper phase. The devices are rated to handle the peak currentstresses (that are relatively high if full sag protection is needed).


Fig. 6. Simulation waveforms where input voltages, output voltage, voltage atthe point VX , and the inductor current are given from top to bottom, respectively.

As a result, the devices can handle normal overloads associatedwith powering up connected loads, without having to oversizethe device current ratings. As all devices are IGBTs, the re-sponse time is essentially instantaneous. No delays associatedwith thyristor turn-OFF need to be handled. It should be notedthat snubber operation is automatically ensured here, withoutany losses—giving higher overall efficiency. All the compo-nents are small sized, allowing for a “thin converter” that canbe easily integrated with the incoming transformer or with aswitchgear. Finally, the ability to use dual IGBT modules thatare readily available in the market will provide a cost-effectiveimplementation.

The proposed ZESC converter topology is shown to havelower device count, lower cost, and comparable protection asthe original ZESC converter proposed earlier. It also uses avail-able dual IGBT modules and incorporates a lossless snubberfunction. It has applicability for sag correctors rated at up to afew megawatts.

IV. CONVERTER DESIGN

Design equations have been developed and given in Table Ithat facilitates the selection of switching devices and passivesfor the converter shown in Fig. 4. The symbols used in Table Iare defined in Table II.

Based on the design parameters of Table I, a design of single-phase module as part of a three-phase 100 kW converter ratedat 480 V with a switching frequency of 10 kHz is undertaken.

The module, implemented for phase A, is designed to handlea sag condition of 0.0, 0.8, and 0.8 p.u. on the input phases A, B,and C, respectively, and keep the output phase A at 1.0 p.u. Dueto the nature of the converter, the duty varies from 0 to 0.667over a cycle. So, each of the design equation is set to employ

TABLE IIDESIGN OF ZESC CONVERTER

TABLE IIIDEFINITION OF SYMBOLS

TABLE IVDESIGN OF 480 V, 60 HZ, 100 kW ZESC CONVERTER

Fig. 7. Analysis of the percentage of events with certain voltage remaining oneach of the phases.

the worst case duty. The result of the design is highlighted inTable IV.

The reduced device count topology in comparison with thestandard topology introduced in [12] and [13] makes a tradeoffwith slightly higher device rating and use of larger snubbercapacitors for fewer devices that are readily available off theshelf in dual configurations. It should be noted that sizes of thesnubber capacitors depends directly upon the power factor ofthe load: the higher the power factor, the smaller the snubbercapacitors.

In this design example, the converter is sized to handle asubstantial degree of voltage sag where one phase has droppedentirely to zero. Fig. 7 indicates that over 85% of the eventshave at least 80% of voltage remaining on at least two of the


TABLE VTOPOLOGY COMPARISON OF REDUCED-COUNT ZESC AND FOUR-WIRE

BACK-TO-BACK CONVERTER FOR A 100 kWTHREE-PHASE OR 33.33 kW SINGLE-PHASE APPLICATION

lines. This means that the converter can protect the full load of100 kW from 85% of the sag events. However, a plant rated at100 kW might remain at this peak load for only a small period oftime on a given day with a very small probability of a voltage sagcoinciding during the same period. To put this into perspective,if the peak load of 100 kW occurs for 10% of the time, and thereare average of 30 short-duration (less than six cycles) voltagesags in a given year, the probability of a sag occurring at thepeak load is 1 × 10−6%. Thus, for the rest of the time when theload is not at its peak, the amount of protection realized by theconverter, rated for full load, is higher.

An alternate way to think about this is to say that a designdoes not necessarily need to protect against a given percentageof the events at the full load. Realizing that the load remains atits peak only for a short duration of time, converter ratings canbe statistically optimized to realize the highest level of returnon investment.

Similarly rated and commercially available DVRs have a de-vice rating of 150 A under normal operating conditions. How-ever, under current overload conditions, such as when handlingin-rush or fault current, devices with significantly higher ratingsare required. For the ZESC converter, the devices are alreadyrated high enough to handle the overload conditions. And thethermal stresses on devices and passives are at a minimum dueto infrequent use (about 30 times a year for several cycles) ofthe ZESC converter in the sag compensation mode. Further, theissues of transformer saturation and handling of the electrolyticcapacitor’s failure modes are entirely eliminated.

Table V provides a comparison between the ZESC, shown inFig. 4, and the back-to-back, four-wire, voltage source inverter(VSI)-based converter shown in Fig. 8. The comparison is madefor a 100 kW three-phase (or 33.33 kW single-phase) load wherethe grid voltages VA , VB , VC are, respectively, 0.5, 0.8, 0.8 perunit. The primary advantage of ZESC is its capability to providethe desired voltage synthesis without using bulk energy storage

Fig. 8. Single-phase back-to-back VSI-based converter.

elements as found in back-to-back converters. The lack of largeelectrolytic capacitors for energy storage combined with fewernumbers of active devices with lower VA ratings lead to higherreliability, lower cost, and simpler controllers.

V. DESIGN OF THE CONTROL ARCHITECTURE

Safe commutations of switches in direct ac–ac convert-ers present a unique challenge that need to be addressedappropriately. There are primarily two ways to minimize stressesand faults on the devices through: 1) single-step commutationand use of snubbers and 2) multistep commutations that elim-inate shoot-through while continuously maintaining a path forthe current to flow, and thus obviating the use of snubbers en-tirely. The latter is a much more attractive solution as the lossesin a snubber circuit present a significant issue.

In order to effectively achieve multistep commutation, accu-rate feedback of converter’s state information is of paramountimportance. This constitutes passing the quadrant at whichthe converter is currently operating to the controller. Basedon this information, coupled with an ideal switching wave-form, the controller then determines the safe commutation se-quence of all the switching devices to achieve the desired con-trol objective as dictated by the ideal switching waveform.Proper commutation is critical to ensure proper functioningof direct ac–ac converters, from simple ac choppers tomatrix converters and the full-fledged ZESC converter[12], [13].

While the ZESC topology has been reduced to utilize dualmodules in this paper, the converter can still take advantageof multistep commutations in order to avoid unsafe switchingstates. The switching states to avoid include (1111), (1110),and (0111), where “1” indicates that the device is ON, and “0”indicates that the device is OFF, for the switches S1 ,S2 ,S3 , andS4 . Deadtime can be utilized to avoid landing in one of theseunsafe states by turning all four switches OFF. However, thatunnecessarily increases the size of the snubber capacitors CS1and CS2 and takes away from the concept of “zero-energy sagcorrector.”

In order to build the control framework for achieving multi-step commutation, the architecture depicted in Fig. 9 is devisedand built. The given architecture is for a single-phase module,but the same architecture can be duplicated onto the other twophases while employing a single DSP to control all three phases.The TMS320F2812 DSP by Texas Instruments is chosen as theprimary controller. The DSP samples analog signals coming in


Fig. 9. Simplified diagram of the control architecture used in controlling theZESC converter.

from the power stage that include state information such as in-ductor current and input and output voltages and generates theideal PWM waveform as well as set appropriate bits to indicatethe quadrant that the converter is operating under. A sag correct-ing device operates for only a very small period of time, whilebeing in a bypass mode most of the time. Thus, it falls to theDSP to also indicate when a voltage sag has occurred such thatthe rest of the time, the converter can be configured to operatein the bypass mode.

The output of the DSP is then fed into a finite state machinethat is used to achieve the appropriate multistep commutation.Although a simple 8-bit EEPROM with a clocked latch is quitecapable of handling the task, field-programmable gate array(FPGAs) can also be used for implementing state machines thatare much more complicated and have more than 16 states (24).The first four bits of the 8-bit addressable data in the EEPROMare used to store the actual input to the gate driver, while theother four bits store the state number itself. The 8-bit output ofthe EEPROM is then latched. The state number from the latchis fed back to both the DSP and the EEPROM to indicate thepresent state of the state machine.

The latch can be clocked in one of two ways. The first wayis to set a constant clock frequency whose period is longerthan the longest of either the turn-ON or turn-OFF time of theIGBT devices. The second way is to implement a feedbackthat provides a pulse to the latch clock when the IGBTs havecommutated to the desired switching state. So when the output ofthe latch and states of the IGBTs match, the latch can be clockedto proceed to the next step in the commutation sequence, thusensuring glitch- and fault-free transitions.

Fig. 10. Finite state machine used to determine proper commutation of theIGBT devices for a single-phase ZESC module.

TABLE VIOUTPUT OF THE STATES IN FIG. 7 TO THE GATE DRIVER

A simple diagram of the state machine used in generating theswitching signal during the voltage sag mode is given by Fig. 10.In the diagram, the states are dependent entirely on the quadrantinformation and the ideal switching behavior given by Q = 0 or1. For each of the states 1 through 11 of the state machine, theEEPROM outputs the switching signal to the IGBT devices, asgiven by Table VI. As can be observed in Fig. 8 and Table VI,the critical states are avoided by transitioning through states 9,10, and 11.

VI. EXPERIMENTAL RESULTS

A single-phase module, shown in Fig. 11, is built as partof a three-phase system rated at 10 kW to be fed from a480 V line. The details of the converter design are given byTable VII.

A voltage sag of 0.0 p.u. on the input phase A is gener-ated, with nominal voltage imposed upon input phases B and C.The resulting waveform captured with an oscilloscope is givenby Figs. 12 and 13. The measurements are taken at a lowerpower level and with the controller running in an open loop.In Fig. 12, at time T1 , a voltage sag event occurs. Without any


Fig. 11. Prototype of the single-phase ZESC module depicted in Fig. 4.

TABLE VIIPART NUMBER AND RATINGS OF THE VARIOUS COMPONENTS

USED IN THE CONVERTER PROTOTYPE

Fig. 12. Input voltages on the top with phase A sagging to zero, and the outputphase A voltage on the bottom.

compensation, the output of the converter sags with the input.However, at time T2 , the converter is triggered to start correctingthe sag, and thus the output is built back to the nominal levelsagain by stealing energy from phases B and C.

Fig. 13. Effect of switching seen on the voltage at the point VX depicted inFig. 4 on top, and inductor current on bottom.

Fig. 14. Integrating ZESC onto an existing three-phase transformer where(a) depicts ZESC connected to a delta-wye transformer and (b) depicts internalphase-to-phase connection.

Slight distortion of the output voltage can be observedaround the peaks of the sine wave in Fig. 12. This is pri-marily due to the measurements being taken with the con-verter controlled in an open loop and thus inability of the con-verter to compensate for resonant and other waveform-distortingeffects.

The voltage at the point VX (see Fig. 4) and current throughthe inductor is given by Fig. 13. The heart-shaped waveform thatis characteristic of ZESC converters is present at the point VX .The distortion that is observed on the output voltage can also beseen in both waveforms in Fig. 13. By closing the loop on boththe voltage and current, this distortion can be controlled.

The experimental measurements validate that the convertercan compensate for even the worst sags (0.0 p.u.) and keep theload online.


VII. REALIZING A THIN AC CONVERTER

The proposed ZESC converter exhibits characteristics of athin ac converter (TACC) [14], and thus, is suitable for in-tegrating with an existing transformer or switchgear. Fig. 14depicts a drawing of such an integration taking place with athree-phase, delta-wye transformer. As shown in Fig. 14(b), theZESC functionality is realized using three phase-independentmodules. Each of these modules comprises entirely of small LCcomponents and semiconductor switches and control circuits,all of which results in a “thin” form factor.

VIII. CONCLUSION

This paper has presented a novel ZESC that utilizes two IGBTdual packages to realize a direct ac/ac converter. The reduceddevice count and the ability to use readily available IGBT dualpackages greatly simplify the design of the converter and allowscaling from a few hundred watts to several megawatts. Elimi-nation of low-frequency magnetics and energy storage allows acompact package and provides the opportunity to integrate thefunctionality into existing assets to realize new devices such as“sag correcting transformers.”

Operation of the patent-pending, reduced-count ZESC topol-ogy is detailed, and proof of concept has been realized andvalidated through simulation and experimental results. The con-verter exhibits similar performance as the original full-fledgedZESC converter, but with fewer numbers of devices and withsimpler control requirements.

A control architecture, utilizing ROM to implement a finitestate machine, has been discussed that is effectively able toprovide a degree of control necessary to achieve snubber-lessmultistep commutation for a direct AC/AC line of converters.The architecture has been validated through experimental mea-surements.

REFERENCES

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[2] A. Bendre, D. Divan, W. Kranz, and W. Brumsickle, “Equipment failurescaused by power quality disturbances,” in Proc. IEEE IAS Conf. Record,2004, p. 489

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[4] W. E. Brumsickle, R. S. Schneider, G. A. Luckjiff, D. M. Divan, andM. F. McGranaghan, “Dynamic sag correctors: Cost-effective industrialpower line conditioning,” IEEE Trans. Ind. Appl., vol. 37, no. 1, pp. 212–217, Jan./Feb. 2001.

[5] S. Srinivasan and G. Venkataramanan, “Design of a versatile three-phaseAC line conditioner,” in Proc. IEEE Ind. Appl. Soc., Oct. 1995, vol. 3,pp. 2492–2499.

[6] S. Srinivasan and G. Venkataramanan, “Comparative evaluation of PWMAC–AC converters,” in Proc. IEEE Power Electron. Spec. Conf., Jun.1995, vol. 1, pp. 529–535.

[7] S. M. Hietpas and R. Pecen, “Simulation of a three-phase AC–AC boostconverter to compensate for voltage sags,” in Proc. Rural Electr. PowerConf., Apr. 1998, p. b4-1-7.

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[12] A. Prasai, N. Kelkar, and D. Divan, “Zero energy storage voltage sagcorrectors for industrial applications,” in Proc. IEEE PESC, Jun. 2007,pp. 3086–3091.

[13] A. Prasai and D. Divan, “Zero energy sag correctors—Optimizing dynamicvoltage restorers for industrial applications,” in Proc. IAS, Sep. 2007,pp. 1585–1592.

[14] D. Divan, J. Sastry, A. Prasai, and H. Johal, “Thin AC converters—A newapproach for making existing grid assets smart and controllable,” in Proc.IEEE PESC ’08, Jun. 2008, pp. 2340–2345.

Anish Prasai (S’01) received the B.S. and M.S. de-grees in electrical engineering with a focus on powerelectronics from Virginia Polytechnic Institute andState University, Blacksburg, in 2004 and 2006, re-spectively. He is currently working toward the Ph.D.degree at Georgia Institute of Technology, Atlantaunder Prof. Deepak M. Divan.

His current research interests include power elec-tronics for industrial, wind, and microgrid applica-tions.

Deepak M. Divan (S’78–M’78–SM’91–F’98) re-ceived the B. Tech. degree from the Indian Instituteof Technology, Kanpur, India, in 1975, and the M.Sc.and Ph.D. degrees from the University of Calgary,Calgary, AB, Canada, in 1979 and 1983, respectively.

He is currently a Professor in the School of Elec-trical and Computer Engineering, Georgia Instituteof Technology, Atlanta, where he is also the Direc-tor of the Intelligent Power Infrastructure Consortium(IPIC). He is the Chairman and the Chief TechnologyOfficer (CTO) at Innovolt, Inc., Atlanta. From 1995

to 2004, he was the Chairman and the Chief Executive Officer (CEO)/CTO ofSoft Switching Technologies, a company in the industrial power quality market.He is the author or coauthor of more than 200 papers, and holds 28 issuedand four pending patents. His current research interests include application ofpower electronics for power quality, power reliability, and utility and industrialapplications.

Dr. Divan is the President of the IEEE Power Electronics Society for 2009–2010 and was Chair of the IEEE Energy 2030 Conference in Nov. 2008. He wasthe recipient of the 2006 IEEE William E. Newell Award for contributions inpower electronics.

Zero-Energy Sag Corrector With Reduced Device Count

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