yamin/ yamin/lectures/VerilogHDL.pdf · 28. Click on Report YAMIN LI, CIS, HOSEI UNIVERSITY Verilog...
Transcript of yamin/ yamin/lectures/VerilogHDL.pdf · 28. Click on Report YAMIN LI, CIS, HOSEI UNIVERSITY Verilog...
http://cis.k.hosei.ac.jp/∼yamin/
Verilog HDL – p.1/76YAMIN LI, CIS, HOSEI UNIVERSITY
HDL —¦¦¦��� }}}~~~yyydddyyy���½½½Verilog HDL
IEEE Standard 1364-1995 (Verilog-1995)IEEE Standard 1364-2001 (Verilog-2001)
VHDL — VHSIC HDLIEEE Standard 1076-1987
AHDL — Altera HDL
SystemVerilog HDLIEEE Standard 1800-2005
SystemC
· · ·
Verilog HDL – p.2/76YAMIN LI, CIS, HOSEI UNIVERSITY
⇓
Verilog HDL – p.3/76YAMIN LI, CIS, HOSEI UNIVERSITY
There are many tools (free or not)
I am using 2 free tools
On Windows: Quartus II Web Edition
A CPLD/FPGA design tool by Altera
On Linux: Icarus Verilog
Support transistor level design
Also for Windows
Verilog HDL – p.4/76YAMIN LI, CIS, HOSEI UNIVERSITY
1. Download Quartus II fromhttp://storage.cis.k.hosei.ac.jp/pub/CISOnly/QuartusII/
2. Install Quartus II
3. Create a working directory, ex. C\:CPU
4. Start up Quartus II
Verilog HDL – p.5/76YAMIN LI, CIS, HOSEI UNIVERSITY
5. File - New Project Wizard...
Verilog HDL – p.6/76YAMIN LI, CIS, HOSEI UNIVERSITY
6. Working directory: C\:CPU,project name: mux2x32
Verilog HDL – p.7/76YAMIN LI, CIS, HOSEI UNIVERSITY
7. Click on Next >
Verilog HDL – p.8/76YAMIN LI, CIS, HOSEI UNIVERSITY
8. Device family: FLEX10K
Verilog HDL – p.9/76YAMIN LI, CIS, HOSEI UNIVERSITY
9. Click on Next >
Verilog HDL – p.10/76YAMIN LI, CIS, HOSEI UNIVERSITY
10. Click on Finish
Verilog HDL – p.11/76YAMIN LI, CIS, HOSEI UNIVERSITY
11. File - New...Select Verilog HDL File, then click on OK.
Verilog HDL – p.12/76YAMIN LI, CIS, HOSEI UNIVERSITY
12. Input mux2x32.v code in edit windowFile - Save (file name: mux2x32.v)Project - Add Current File to Project
module mux2x32 (a0,a1,s,y);
input [31:0] a0,a1; // a0,a1: 32-bit input s; // s: 1-bit
output [31:0] y; // y: 32-bit
assign y = s ? a1 : a0; // like C
endmodule
Verilog HDL – p.13/76YAMIN LI, CIS, HOSEI UNIVERSITY
13. Processing - Start - Start Analysis & Synthesis
Verilog HDL – p.14/76YAMIN LI, CIS, HOSEI UNIVERSITY
14. Analysis & Synthesis will be OK, click on OK
Verilog HDL – p.15/76YAMIN LI, CIS, HOSEI UNIVERSITY
15. Processing - Simulator Tool
Verilog HDL – p.16/76YAMIN LI, CIS, HOSEI UNIVERSITY
16. Select Functional mode
Verilog HDL – p.17/76YAMIN LI, CIS, HOSEI UNIVERSITY
17. Click on Generate Functional Simulation Netlist
Verilog HDL – p.18/76YAMIN LI, CIS, HOSEI UNIVERSITY
18. Click on Open
Verilog HDL – p.19/76YAMIN LI, CIS, HOSEI UNIVERSITY
19. Edit - Insert - Insert Node or Bus...
Verilog HDL – p.20/76YAMIN LI, CIS, HOSEI UNIVERSITY
20. Select Radix: Hexadecimal
Verilog HDL – p.21/76YAMIN LI, CIS, HOSEI UNIVERSITY
21. Click on Node Finder
Verilog HDL – p.22/76YAMIN LI, CIS, HOSEI UNIVERSITY
22. Select Filter: Pins: all
Verilog HDL – p.23/76YAMIN LI, CIS, HOSEI UNIVERSITY
23. Named: ??, click on List
Verilog HDL – p.24/76YAMIN LI, CIS, HOSEI UNIVERSITY
24. Select all pins and click on≥, OK, OK
Verilog HDL – p.25/76YAMIN LI, CIS, HOSEI UNIVERSITY
25. Edit - Zoom. Select region and double-click on it
Verilog HDL – p.26/76YAMIN LI, CIS, HOSEI UNIVERSITY
26. Save to mux2x32.vwf
Verilog HDL – p.27/76YAMIN LI, CIS, HOSEI UNIVERSITY
27. Click on Start, then OK
Verilog HDL – p.28/76YAMIN LI, CIS, HOSEI UNIVERSITY
28. Click on Report
Verilog HDL – p.29/76YAMIN LI, CIS, HOSEI UNIVERSITY
29. Edit - Zoom. Check if it is what you expected
Verilog HDL – p.30/76YAMIN LI, CIS, HOSEI UNIVERSITY
30. In the next project, click on��!(N)
Verilog HDL – p.31/76YAMIN LI, CIS, HOSEI UNIVERSITY
aluc[1:0]
a[31:0]
b[31:0]
s[31:0]
ALU
?
aluc[1:0]0 0: s = a AND b0 1: s = a OR b1 0: s = a ADD b1 1: s = a SUB b
ALU: Arithmetic Logical Unit
Verilog HDL – p.32/76YAMIN LI, CIS, HOSEI UNIVERSITY
a[31:0]b[31:0]
aluc[1:0]
s[31:0]
aluc[0]
aluc[1]
aluc[1:0]0 0 AND0 1 OR1 0 ADD1 1 SUB
a[31:0]b[31:0]sub
s[31:0]
addsub32
a0[31:0]a1[31:0]s
y[31:0]
mux2x32
a0[31:0]a1[31:0]s
y[31:0]
mux2x32
module
input
output
mux2x32: if (s==0) y = a0; else y =a1;
addsub32: if (sub==1) s = a− b; else s = a + b;
Verilog HDL – p.33/76YAMIN LI, CIS, HOSEI UNIVERSITY
module mux2x32 (a0,a1,s,y);
input [31:0] a0,a1; // a0,a1: 32-bitinput s; // s: 1-bit
output [31:0] y; // y: 32-bit
assign y = s ? a1 : a0; // like C
endmodule
Verilog HDL – p.34/76YAMIN LI, CIS, HOSEI UNIVERSITY
module addsub32 (a,b,sub,s);
input [31:0] a,b;input sub;
output [31:0] s;
assign s = sub ? a - b : a + b;
endmodule
Verilog HDL – p.35/76YAMIN LI, CIS, HOSEI UNIVERSITY
module alu1 (a,b,aluc,s);
input [31:0] a,b;
input [1:0] aluc;
output [31:0] s;
wire [31:0] d_and = a & b; // AND
wire [31:0] d_or = a | b; // OR
wire [31:0] d_ao,d_as; // 32-bit wires
// use other modules:
mux2x32 mx_ao (d_and,d_or,aluc[0],d_ao);
addsub32 as (a,b,aluc[0],d_as);
mux2x32 mx_la (d_ao,d_as,aluc[1],s);
endmodule
Verilog HDL – p.36/76YAMIN LI, CIS, HOSEI UNIVERSITY
Verilog HDL – p.37/76YAMIN LI, CIS, HOSEI UNIVERSITY
module alu2 (a,b,aluc,s);input [31:0] a,b;input [1:0] aluc;output [31:0] s;
assign s = operate(a,b,aluc);
function [31:0] operate; // functioninput [31:0] x,y;input [1:0] c;case (c)
2’b00: operate = x & y;2’b01: operate = x | y;2’b10: operate = x + y;2’b11: operate = x - y;
endcaseendfunction
endmodule
Verilog HDL – p.38/76YAMIN LI, CIS, HOSEI UNIVERSITY
Verilog HDL – p.39/76YAMIN LI, CIS, HOSEI UNIVERSITY
module alu3 (a,b,aluc,s);input [31:0] a,b;input [1:0] aluc;output [31:0] s;
reg [31:0] s; // s will be a net (wire)// although reg is used, the following// code will generate a combinational// circuit, because all cases of aluc// were considered.
always @ (a or b or aluc) begin // eventif (aluc == 2’b00) s = a & b;else if (aluc == 2’b01) s = a | b;else if (aluc == 2’b10) s = a + b;else s = a - b;
endendmodule
Verilog HDL – p.40/76YAMIN LI, CIS, HOSEI UNIVERSITY
module alu4 (a,b,aluc,s);input [31:0] a,b;input [1:0] aluc;output [31:0] s;
reg [31:0] s;
always @ (a or b or aluc) begin // eventcase (aluc)
2’b00: s = a & b;2’b01: s = a | b;2’b10: s = a + b;2’b11: s = a - b;
endcaseend
endmodule
Verilog HDL – p.41/76YAMIN LI, CIS, HOSEI UNIVERSITY
module dff32 (d,clk,clrn,q);input [31:0] d;input clk,clrn;output [31:0] q;reg [31:0] q;always @ (negedge clrn or posedge clk)if (clrn == 0) begin
q <= 0;end else begin
q <= d;end
endmodule
d[31:0]clkclrn
q[31:0]
dff32
Verilog HDL – p.42/76YAMIN LI, CIS, HOSEI UNIVERSITY
module dffe32 (d,clk,clrn,e,q);input [31:0] d;input clk,clrn,e;output [31:0] q;reg [31:0] q;always @ (negedge clrn or posedge clk)if (clrn == 0) begin
q <= 0;end else begin
if (e == 1) q <= d;end
endmodule
d[31:0]clkclrn q[31:0]
dffe32
e
Verilog HDL – p.43/76YAMIN LI, CIS, HOSEI UNIVERSITY
Type Symbol Performance
∼ 1’s complement (NOT)& Bitwise AND
Bitwise | Bitwise OR∧ Bitwise XOR∧∼ or ∼∧ Bitwise XNOR
Examples:wire [31:0] a,b;wire [31:0] c = a & b;wire [31:0] d = a ˆ b;
Verilog HDL – p.44/76YAMIN LI, CIS, HOSEI UNIVERSITY
Type Symbol Performance
! Logical NOTLogical && Logical AND
|| Logical OR
Examples:wire [31:0] a,b,c,d;wire equ_both = (a==b) && (c==d);wire equ_any = (a==b) || (c==d);
Verilog HDL – p.45/76YAMIN LI, CIS, HOSEI UNIVERSITY
Type Symbol Performance
& Reduction AND∼& Reduction NAND| Reduction OR
Reduction∼| Reduction NOR∧ Reduction XOR∼∧ or ∧∼ Reduction XNOR
Examples:wire [31:0] s;wire s_is_zero = ˜|s;wire s_is_m1 = &s;
Verilog HDL – p.46/76YAMIN LI, CIS, HOSEI UNIVERSITY
Type Symbol Performance
+ Addition− Subtraction− 2’s complement
Arithmetic ∗ Multiplication/ Division% Remainder∗∗ exponent
Examples:wire [31:0] a,b;wire [31:0] c = a + b;
Verilog HDL – p.47/76YAMIN LI, CIS, HOSEI UNIVERSITY
Type Symbol Performance
>> Logical right shift<< Logical left shift
Shift>>> Arithmetic right shift<<< Arithmetic left shift
Examples:wire [31:0] d;wire [4:0] sa;wire [31:0] sll = d << sa;wire [31:0] srl = d >> sa;wire [31:0] sra = $signed(d) >>> sa; $
Verilog HDL – p.48/76YAMIN LI, CIS, HOSEI UNIVERSITY
Type Symbol Performance
Replication {{ }} ReplicationConcatenation { , } ConcatenationConditional ? : Conditional
Examples:wire [31:0] b,inst;wire [15:0] imm16 = inst[15:0];wire [15:0] se16 = {16{imm[15]}};wire [31:0] simm = {se16,imm16};wire [31:0] alu_b = is_imm? simm : b;
Verilog HDL – p.49/76YAMIN LI, CIS, HOSEI UNIVERSITY
Type Symbol Performance
> Greater than< Less than>= Greater than or equal to
Relational<= Less than or equal to== Logical equality (bit-value
1’bX is removed from com-parison)
Examples:wire [31:0] a,b;if (a == b) ...
Verilog HDL – p.50/76YAMIN LI, CIS, HOSEI UNIVERSITY
Type Symbol Performance
! = Logical inequality (bit-value 1’bX is removedfrom comparison)
Relational=== 4-state logical equality
(bit-value 1’bX is taken asliteral)
! == 4-state logical inequality(bit-value 1’bX is taken asliteral)
Examples:if (a != b) ...
Verilog HDL – p.51/76YAMIN LI, CIS, HOSEI UNIVERSITY
Symbol Value
0 zero, low, false
1 one, high, true
z or Z high impedance, floating
x or X unknown, uninitialized, contention
Example:
casex (intr)
4’b1xxx: vec = 2’h3;
4’b01xx: vec = 2’h2;
4’b001x: vec = 2’h1;
4’b0001: vec = 2’h0;
default: vec = 2’hx;
endcase
Verilog HDL – p.52/76YAMIN LI, CIS, HOSEI UNIVERSITY
1. Structural style (ì!dy)
2. Dataflow style (���¬Ä�dy)
3. Behavioral style (X�dy)
Verilog HDL – p.53/76YAMIN LI, CIS, HOSEI UNIVERSITY
Example: Full Adder (Ó`¦H) Design with 3 styles
input a, b;input ci; // carry in (YX$bGXê+)output s; // sum (�)output co; // carry out (êXQGXê+)
ab
+ cico s
Verilog HDL – p.54/76YAMIN LI, CIS, HOSEI UNIVERSITY
a b ci co s �¸Ê�
0 0 0 0 0 0 + 0 + 0 = 0 0
0 0 1 0 1 0 + 0 + 1 = 0 1
0 1 0 0 1 0 + 1 + 0 = 0 1
0 1 1 1 0 0 + 1 + 1 = 1 0
1 0 0 0 1 1 + 0 + 0 = 0 1
1 0 1 1 0 1 + 0 + 1 = 1 0
1 1 0 1 0 1 + 1 + 0 = 1 0
1 1 1 1 1 1 + 1 + 1 = 1 1
s = a ⊕ b ⊕ ci;co = a·b + b·ci + ci·a;
a
co
sbci
ab
ci
co:
0
1
00
01
11
10
1
11 1
Verilog HDL – p.55/76YAMIN LI, CIS, HOSEI UNIVERSITY
1. ì!dymodule fa_structural (a,b,ci,s,co);
input a,b,ci;output s,co;wire ab,bc,ca;xor (s,a,b,ci); // s: output of xorand (ab,a,b); // ab: output of andand (bc,b,ci); // bc: output of andand (ca,ci,a); // ca: output of andor (co,ab,bc,ca);// co: output of or
endmodule
Verilog HDL – p.56/76YAMIN LI, CIS, HOSEI UNIVERSITY
2. ���¬Ä�dymodule fa_dataflow (a,b,ci,s,co);
input a,b,ci;output s,co;assign s = a ˆ b ˆ ci;assign co = a&b | b&ci | ci&a;
endmodule
Verilog HDL – p.57/76YAMIN LI, CIS, HOSEI UNIVERSITY
3. X�dymodule fa_behavioral (a,b,ci,s,co);
input a,b,ci;output s,co;assign {co,s} = a + b + ci;
endmodule
Verilog HDL – p.58/76YAMIN LI, CIS, HOSEI UNIVERSITY
Q: Write 3-8 decoder Verilog HDL codes in 3 styles
Input Outpute a[2:0] d[7:0]1 0 0 0 0 0 0 0 0 0 0 11 0 0 1 0 0 0 0 0 0 1 01 0 1 0 0 0 0 0 0 1 0 01 0 1 1 0 0 0 0 1 0 0 01 1 0 0 0 0 0 1 0 0 0 01 1 0 1 0 0 1 0 0 0 0 01 1 1 0 0 1 0 0 0 0 0 01 1 1 1 1 0 0 0 0 0 0 00 x x x 0 0 0 0 0 0 0 0
Verilog HDL – p.59/76YAMIN LI, CIS, HOSEI UNIVERSITY
d[31:0]eclk
q[31:0]
d[31:0]eclk
q[31:0]
d[31:0]eclk
q[31:0]
dffe32
dffe32
dffe32
a00[31:0]a01[31:0]...a31[31:0]s[4:0]
y[31:0]
mux32x32
a00[31:0]a01[31:0]...a31[31:0]s[4:0]
y[31:0]
mux32x32
a[4:0] d0
d1
d31e
...
dec5e
rna[4:0]
d[31:0]
wn[4:0]
we
clk
rnb[4:0]
qa[31:0]
qb[31:0]
r1
...
r31
MIPS CPU Register File 32 X 32 bits
Read port
Read port
Write port
gndr0 = 0
Verilog HDL – p.60/76YAMIN LI, CIS, HOSEI UNIVERSITY
module regfile (rna,rnb,d,wn,we,clk,clrn,qa,qb);input [4:0] rna,rnb,wn;input [31:0] d;input we,clk,clrn;output [31:0] qa,qb;reg [31:0] register [1:31]; // r1 - r31
assign qa = (rna == 0)? 0 : register[rna]; // readassign qb = (rnb == 0)? 0 : register[rnb]; // read
always @(posedge clk or negedge clrn) beginif (clrn == 0) begin // reset
integer i;for (i=1; i<32; i=i+1)
register[i] <= 0;end else begin
if ((wn != 0) && (we == 1)) // writeregister[wn] <= d;
endend
endmodule
Verilog HDL – p.61/76YAMIN LI, CIS, HOSEI UNIVERSITY
Write data to each register and read from it
Verilog HDL – p.62/76YAMIN LI, CIS, HOSEI UNIVERSITY
Example:
s0 s1
s2
s3
x=1
x=0
Verilog HDL – p.63/76YAMIN LI, CIS, HOSEI UNIVERSITY
module fsm (x,clock,resetn,state);input x,clock,resetn; // x==1: 013013, else 012012output reg [1:0] state;reg [1:0] next_state; // will be a netparameter [1:0] s0 = 2’b00, s1 = 2’b01,
s2 = 2’b10, s3 = 2’b11;always @* begin // combinational circuit here
case (state)s0: next_state = s1;s1: next_state = x? s3 : s2;default: next_state = s0; //combinational
endcaseendalways @ (posedge clock or negedge resetn) begin
if (resetn == 0) beginstate <= s0;
end else beginstate <= next_state;
endend
endmodule
Verilog HDL – p.64/76YAMIN LI, CIS, HOSEI UNIVERSITY
Verilog HDL – p.65/76YAMIN LI, CIS, HOSEI UNIVERSITY
Order of blocking statements matters
Order of non-blocking statements doesn’t matter
Example: Assume a = 1; b = 2; c = 3; d = 4; e = 5;Blocking assignment Non-blocking assignment
ex1 ex2 ex3 ex4
e = a + b; b = d + e; e <= a + b; b <= d + e;b = d + e; e = a + b; b <= d + e; e <= a + b;
e = 3; b = 9; e = 3; b = 9;b = 7; e = 10; b = 9; e = 3;
Verilog HDL – p.66/76YAMIN LI, CIS, HOSEI UNIVERSITY
4-bit counter design in
1. Verilog HDL
2. VHDL
3. AHDL
Verilog HDL – p.67/76YAMIN LI, CIS, HOSEI UNIVERSITY
module time_counter_verilog (enable, clk, my_counter);input enable, clk;output [3:0] my_counter;reg [3:0] my_counter;always @ (posedge clk) begin
if (enable)my_counter = my_counter + 4’h1;
endendmodule
Verilog HDL – p.68/76YAMIN LI, CIS, HOSEI UNIVERSITY
LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY time_counter_vhdl IS
PORT (clk : IN STD_LOGIC;enable : IN STD_LOGIC;my_counter : OUT INTEGER RANGE 0 TO 15
);END time_counter_vhdl;ARCHITECTURE a_cnt OF time_counter_vhdl ISBEGIN
PROCESS (clk)VARIABLE cnt : INTEGER RANGE 0 TO 15;
BEGINIF (clk’EVENT AND clk = ’1’) THEN
IF enable = ’1’ THENcnt := cnt + 1;
END IF;END IF;my_counter <= cnt;
END PROCESS;END a_cnt;
Verilog HDL – p.69/76YAMIN LI, CIS, HOSEI UNIVERSITY
Verilog HDL – p.70/76YAMIN LI, CIS, HOSEI UNIVERSITY
SUBDESIGN time_counter_ahdl (enable, clk : INPUT;my_counter[3..0] : OUTPUT;
)VARIABLE
counter[3..0] : DFF;BEGIN
counter[].clk = clk;my_counter[] = counter[].q;
IF enable THENcounter[] = counter[] + 1;
ELSEcounter[] = counter[];
END IF;END;
Verilog HDL – p.71/76YAMIN LI, CIS, HOSEI UNIVERSITY
Verilog HDL – p.72/76YAMIN LI, CIS, HOSEI UNIVERSITY
Design a 32-bit 4-to-1 multiplexer (mux4x32)module mux4x32(a0,a1,a2,a3,s,y);
input [31:0] a0,a1,a2,a3;input [1:0] s;output [31:0] y;
function [31:0] select;input [31:0] a0,a1,a2,a3;input [1:0] s;case (s)
2’b00: select = a0;2’b01: select = a1;2’b10: select = a2;2’b11: select = a3;
endcaseendfunction
assign y=select(a0,a1,a2,a3,s);endmodule
Do the functional simulation with Quartus II
Verilog HDL – p.73/76YAMIN LI, CIS, HOSEI UNIVERSITY
Design a 32-bit D Flip Flop with Enable (dffe32.v)module dffe32 (d,clk,clrn,e,q);
input [31:0] d;input clk,clrn,e;output [31:0] q;
reg [31:0] q;always @ (negedge clrn or posedge clk)
if (clrn == 0) beginq <= 0;
end else beginif (e == 1) q <= d;
endendmodule
Do the functional simulation with Quartus II
Verilog HDL – p.74/76YAMIN LI, CIS, HOSEI UNIVERSITY
Write 3-8 decoder Verilog HDL codes in 3 styles
Input Outpute a[2:0] d[7:0]1 0 0 0 0 0 0 0 0 0 0 11 0 0 1 0 0 0 0 0 0 1 01 0 1 0 0 0 0 0 0 1 0 01 0 1 1 0 0 0 0 1 0 0 01 1 0 0 0 0 0 1 0 0 0 01 1 0 1 0 0 1 0 0 0 0 01 1 1 0 0 1 0 0 0 0 0 01 1 1 1 1 0 0 0 0 0 0 00 x x x 0 0 0 0 0 0 0 0
Do the functional simulation with Quartus II
Verilog HDL – p.75/76YAMIN LI, CIS, HOSEI UNIVERSITY
Verilog HDL – p.76/76YAMIN LI, CIS, HOSEI UNIVERSITY