XTP196 - KC705 MIG Design Creation with Vivado · 2020. 10. 3. · Generate MIG Example Design ....
Transcript of XTP196 - KC705 MIG Design Creation with Vivado · 2020. 10. 3. · Generate MIG Example Design ....
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October 2012
KC705 MIG Design Creation with Vivado
XTP196
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© Copyright 2012 Xilinx, Inc. All Rights Reserved. XILINX, the Xilinx logo, the Brand Window and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. NOTICE OF DISCLAIMER: The information disclosed to you hereunder (the “Information”) is provided “AS-IS” with no warranty of any kind, express or implied. Xilinx does not assume any liability arising from your use of the Information. You are responsible for obtaining any rights you may require for your use of this Information. Xilinx reserves the right to make changes, at any time, to the Information without notice and at its sole discretion. Xilinx assumes no obligation to correct any errors contained in the Information or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE INFORMATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS.
Revision History
Date Version Description 10/23/12 2.0 Recompiled for 2012.3. Added AR52368.
07/25/12 1.0 Regenerated for 14.2. Added Vivado Flow. Added AR50886.
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Overview KC705 Board KC705 Setup Generate MIG Example Design Modifications to Example Design Compile Example Design Run MIG Example Design References
Note: This presentation applies to the KC705
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Xilinx KC705 Board
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Vivado Software Requirements Xilinx Vivado 2012.3 software
Note: Presentation applies to the KC705
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ChipScope Pro Software Requirement Xilinx ChipScope Pro 14.3 software
Note: Presentation applies to the KC705
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Generate MIG Example Design Open Vivado
Start → All Programs → Xilinx Design Tools → Vivado 2012.3 → Vivado Select Create New Project
Note: Presentation applies to the KC705
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Generate MIG Example Design Click Next
Note: Presentation applies to the KC705
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Set the Project name and location to kc705_mig_vivado and C:\ – Check Create Project Subdirectory
Generate MIG Example Design
Note: Presentation applies to the KC705
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Generate MIG Example Design Select RTL Project – Select Do not specify sources at this time
Note: Presentation applies to the KC705
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Generate MIG Example Design Select the KC705 Board
Note: Presentation applies to the KC705
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Generate MIG Example Design Click Finish
Note: Presentation applies to the KC705
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Generate MIG Example Design Click on IP Catalog
Note: Presentation applies to the KC705
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Generate MIG Example Design Select MIG 7 Series under Memory Interface Generators
Note: Presentation applies to the KC705
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Generate MIG Example Design Right click on MIG 7 Series Version 1.7a – Select Customize IP
Note: Presentation applies to the KC705
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Generate MIG Example Design Leave this page as is – Click Next
Note: Presentation applies to the KC705
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Generate MIG Example Design Leave this page as is – Click Next
Note: Presentation applies to the KC705
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Generate MIG Example Design Leave this page as is – Click Next
Note: Presentation applies to the KC705
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Generate MIG Example Design Select Memory Type – DDR3 SDRAM – Click Next
Note: Presentation applies to the KC705
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Generate MIG Example Design Select – Clock Period: 1250 ps – Type: SODIMMs – Part: MT8JTF12864HZ-1G6 – Data Mask: Checked – Click Next
Note: Presentation applies to the KC705
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Generate MIG Example Design Select: – Input Clock Period: 5000 ps – RTT: RZQ/6 – Click Next
Note: Presentation applies to the KC705
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Generate MIG Example Design Select – Reference Clock: Use
System Clock – Debug: ON – Click Next
Note: Presentation applies to the KC705
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Generate MIG Example Design Select – DCI Cascade: Checked – Click Next
Note: Presentation applies to the KC705
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Generate MIG Example Design Select Fixed Pin Out – Click Next
Note: Presentation applies to the KC705
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Modifications to Example Design Open the KC705 MIG Vivado Design Files (2012.3 C) – Available through http://www.xilinx.com/kc705 – Extract the file, “example_top.ucf” only to C:\kc705_mig_vivado – Contains the constraints needed for KC705 MIG design – This zip file will be needed later in the presentation
Note: Presentation applies to the KC705
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Generate MIG Example Design Select ReadUCF – Open the file:
example_top.ucf
Note: Presentation applies to the KC705
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Generate MIG Example Design Once it finishes reading in the UCF, click Validate – Click OK
Note: Presentation applies to the KC705
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Generate MIG Example Design The Next button is enabled once the pinout is validated. – Click Next
Note: Presentation applies to the KC705
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Generate MIG Example Design Leave this page as is – Click Next
Note: Presentation applies to the KC705
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Generate MIG Example Design Leave this page as is – Click Next
Note: Presentation applies to the KC705
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Generate MIG Example Design Accept Simulation license, if desired – Otherwise, Decline
license – Click Next
Note: Presentation applies to the KC705
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Generate MIG Example Design Leave this page as is – Click Next
Note: Presentation applies to the KC705
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Generate MIG Example Design Click Generate
Note: Presentation applies to the KC705
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Generate MIG Example Design MIG design appears in Design Sources
Note: Presentation applies to the KC705
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Compile Example Design Right-click on mig_7series_v1_6_0 and select Generate…
Note: Presentation applies to the KC705
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Compile Example Design Select Synthesis as the target to generate
Note: Presentation applies to the KC705
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Compile Example Design Once the Generate step is complete, a check (re)appears on the IP
Note: Presentation applies to the KC705
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Modifications to Example Design Unzip the KC705 MIG Vivado Design Files (2012.3 C) to your C:\kc705_mig_vivado directory – Contains several changes needed to support Kintex-7 devices with MIG
Note: Presentation applies to the KC705
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Modifications to Example Design Modifications to the example design – Added RTL and XDC modifications to drive LEDs – Added DCI Cascade constraints to XDC; for more information on using the DCI
Cascade constraints for 7 Series refer to UG789 – Changed RST_ACT_LOW to “0”; refer to UG586 for more details on using the
RST_ACT_LOW parameter
Note: Presentation applies to the KC705
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Compile Example Design At the Tcl Console enter this command:
cd C:/kc705_mig_vivado/kc705_mig_vivado.srcs/sources_1/ip/mig_7series_v1_7_a_0/mig_7series_v1_7_a_0/example_design/par
Note: Presentation applies to the KC705
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Compile Example Design At the Tcl Console enter this command:
source vivado_gui.tcl This command adds the necessary design files and compiles the ChipScope IP
Note: Presentation applies to the KC705
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Compile Example Design The design files, IP and constraints have been added/generated Click on Generate Bitstream
Note: Presentation applies to the KC705
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Compile Example Design The completed design appears in GUI
Note: Presentation applies to the KC705
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KC705 Setup
Connect a USB Type-A to Micro-B cable to the USB JTAG (Digilent) connector on the KC705 board – Connect this cable to your PC – Power on the KC705 board
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Run MIG Example Design Open ChipScope Pro and select JTAG Chain → Digilent USB Cable… (1) Verify 30 MHz operation and click OK (2)
Note: Presentation applies to the KC705
1
2
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Run MIG Example Design Click OK (1)
Note: Presentation applies to the KC705
1
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Run MIG Example Design Select Device → DEV:0 MyDevice0 (XC7K325T) → Configure… Select <Design Path>\kc705_mig_vivado.runs\impl_1\ example_top.bit
Note: Presentation applies to the KC705
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Run MIG Example Design
After bitstream loads, LED 0 (right most LED) will be lit, and LED1 will be blinking LED 3 will light and stay on – This indicates Calibration has
completed
If an error occurs, LED 0 will go out and LED 2 will light – The “South” button, SW4, is the reset
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Run MIG Example Design Select File → Open Project… Select <Design Path>\ready_for_download\example_top.cpj
Note: Presentation applies to the KC705
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Run MIG Example Design Click on Trigger Setup to view trigger settings
Note: Presentation applies to the KC705
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Run MIG Example Design Click on Waveform; click the Trigger Immediate button (1)
1
Note: Presentation applies to the KC705
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Run MIG Example Design View waveforms Data is valid when dbg_rddata_valid is high
Note: Presentation applies to the KC705
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Run MIG Example Design Zoom in to view data
Note: Presentation applies to the KC705
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Adjust Data Pattern using VIO Console Select VIO Console 3 Set vio_modify_enable to 1
Note: Presentation applies to the KC705
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Adjust Data Pattern using VIO Console Set vio_data_mode_value to “7” for PRBS_DATA
Note: Presentation applies to the KC705
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Run MIG Example Design
Press and release the CPU RESET switch, SW4, after each change to vio_modify_enable or vio_data_mode_value
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Run MIG Example Design Click on Waveform; click the Trigger Immediate button (1) View PRBS data
Note: Presentation applies to the KC705
1
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References
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References Kintex-7 Memory – 7 Series FPGAs Memory Interface Solutions User Guide – UG586
• http://www.xilinx.com/support/documentation/ip_documentation/ mig_7series/v1_7/ug586_7Series_MIS.pdf
ChipScope Pro – ChipScope Pro Software and Cores User Guide
• http://www.xilinx.com/support/documentation/sw_manuals/ xilinx14_3/chipscope_pro_sw_cores_ug029.pdf
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Documentation
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Documentation Kintex-7 – Kintex-7 FPGA Family
• http://www.xilinx.com/products/silicon-devices/fpga/kintex-7/index.htm
KC705 Documentation – Kintex-7 FPGA KC705 Evaluation Kit
• http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm
– KC705 Getting Started Guide • http://www.xilinx.com/support/documentation/boards_and_kits/
ug883_K7_KC705_Eval_Kit.pdf
– KC705 User Guide • http://www.xilinx.com/support/documentation/boards_and_kits/
ug810_KC705_Eval_Bd.pdf
– KC705 Reference Design User Guide • http://www.xilinx.com/support/documentation/boards_and_kits/
ug845_Ref_Design.pdf