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Transcript of Xnor Gates

The University of T Th U i it f Texas at D ll t Dallas

Erik Jonsson School of Engineering and g g Computer Science

Exclusive OR/Exclusive NOR (XOR/XNOR) XOR and XNOR are useful logic functions. Both have two or more inputs. The truth table for two inputs is shown at right. a XOR b = 1 if and only if (iff) a b. a XNOR b = 1 if and only if (iff) a = b. Both may also have many inputs. For >2 inputs, the XOR output is 1 for an odd number of 1 inputs; XNOR has a 1 output for an even number of 1 inputs. Symbols are shown below and to the right right. Like NAND and a a b NOR, XOR and XOR b XNOR are not a b XOR/XNOR Truth Table a b a XOR b a XNOR b 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1

XNOR = ab ab

XNOR1

basic Boolean functions, a b but can be made from AND, OR and NOT. Lecture #6: More Complex Combinational Logic Circuits

XOR = ab ab N. B. Dodge 09/12

The University of T Th U i it f Texas at D ll t Dallas

Erik Jonsson School of Engineering and g g Computer Science

Quick Simplification Review The first technique we studied to simplify a Boolean expression used algebraic techniques. For instance, consider the truth table at right. The minterms shown represent the SOP expression: f abc abc abc The Boolean expression is easily simplifiable i the Boolean id titi using th B l identities: a0 0 0 0 1 1 1 1

b0 0 1 1 0 0 1 1

c0 1 0 1 0 1 0 1

f0 0 0 0 1 0 1 1

f abc abc abc f abc abc abc abc 1 1 f ab( c c ) ac ( b b ) f ab ac The simplified circuit is shown below the truth table table.

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Lecture #6: More Complex Combinational Logic Circuits

N. B. Dodge 09/12

The University of T Th U i it f Texas at D ll t Dallas

Erik Jonsson School of Engineering and g g Computer Science

Quick Simplification Review (2) We W can also plot the minterms on a K-map l l t th i t K and graphically simplify the expression (and the circuit). On the K-map below the three minterms K map below, ( abc , abc , abc) are plotted. The simplified expression derived from the two prime implicants is the same as that using algebraic simplification. a0 0 0 0 1 1 1 1

b0 0 1 1 0 0 1 1

c0 1 0 1 0 1 0 1

f0 0 0 0 1 0 1 1

bc bc bc bc

a a3

000 0 100 4

001 1

011 3 111 7

010 2

1

101 5

1

110 6

1

Identical circuit solution using K-map method:

f ab ac N. B. Dodge 09/12

Lecture #6: More Complex Combinational Logic Circuits

The University of T Th U i it f Texas at D ll t Dallas

Erik Jonsson School of Engineering and g g Computer Science

Exercise 1 Lets do L t d another simplification exercise before moving on. th i lifi ti i b f i Consider this spec: The function f of three variables, x, y, and z, is 1 when x and y are both 1 or when x and z are both 1. Find the p , p p , p SOP expression, the simplified expression, and the simplified circuit. Use the K-map on the next slide to perform the same simplification.x0 0 0 0 1 1 1 1 4

y0 0 1 1 0 0 1 1

z0 1 0 1 0 1 0

f

1 Lecture #6: More Complex Combinational Logic Circuits

0 0 0 0 0 1 1 1

N. B. Dodge 09/12

The University of T Th U i it f Texas at D ll t Dallas

Erik Jonsson School of Engineering and g g Computer Science

K-Map Solution

y z yz yz yz x x000 0 100 4 00 001 1 101 5 0 011 3 111 7 0 0 010 2 110 6

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Lecture #6: More Complex Combinational Logic Circuits

N. B. Dodge 09/12

The University of T Th U i it f Texas at D ll t Dallas

Erik Jonsson School of Engineering and g g Computer Science

Decoders An n-to-2n decoder is a combinational logic circuit that has n inputs and up to 2n outputs. That is, it can have 2n outputs, but it may have less. Each output of a decoder will normally be true (i.e., go to logic 1) for only (i e one combination of the n inputs. Consider the case of an n = 2 decoder. The decoder will have 2 inputs and up to 2n = 22 = 4 outputs. p p Assume that the decoder has the maximum possible number of outputs (4). Then the truth table for the 2-input decoder will show that for each combination of y and x (00, 01, 10, 11), one of the outputs will go high (logic 1) (l i 1). Let us call the inputs y and x and the outputs a, b, c, and d (here, x is the more significant bit). Then let us define a = 1 for x = 0, y = 0; b = 1 for x = 0 and y = 1; c = 1 for x = 1 and y = 0 and d = 1 for x = 1 and y = 1 0, 1.Lecture #6: More Complex Combinational Logic Circuits N. B. Dodge 09/12

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The University of T Th U i it f Texas at D ll t Dallas

Erik Jonsson School of Engineering and g g Computer Science

Decoders (2) The truth tables for a-d in our 2-to-4 decoder are: x y * a b c d 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1 Using the truth tables above, we can define a-d in terms of x and y.

a xy b xy c xy d xy Note that we put x first because we regard the xy pair as a number, with x the more significant bit. 7 Lecture #6: More Complex Combinational Logic Circuits N. B. Dodge 09/12

Boolean expressions for a, b, c, and d in terms of x and y.

The University of T Th U i it f Texas at D ll t Dallas

Erik Jonsson School of Engineering and g g Computer Science

Decoders (3) Remembering that a x y, b xy, c x y, and xy : If we consider xy a binary number with x the th MSB and y th LSB th a-d represent a d the LSB, then d t x true condition for each of the four possible y binary numbers that x and y can represent. Thus we say that each output a-d has an address, which is a unique combination of the two bits in the binary number yx:

a b c d

For xy 00, a 1; for xy 01, b 1; for xy 10, c 1; for xy 11, d 1. Based on the logic expressions above, we can draw the d d circuit as shown at right. d h decoder i i h i hLecture #6: More Complex Combinational Logic Circuits

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N. B. Dodge 09/12

The University of T Th U i it f Texas at D ll t Dallas

Erik Jonsson School of Engineering and g g Computer Science

Decoders (4) In the I th same way, a d d with 3 i decoder ith inputs t may have up to 23 = 8 outputs, and each output will have a unique address that x represents one of the eight p p g possible combinations of the three inputs. Such a circuit is shown to the right. y In the same way, a 4-input decoder could have up to 24 = 16 outputs each of which z outputs, is a unique combination of the inputs. Etc., for 5, 6, 7 Two Notes: Any n-input decoder can have up to 2n outputs, but it may have less. In general, each output for an n-input decoder is created by a single n-input AND gate. Its inputs are the n decoder inputs, some of which may be inverted.

3-input, 3 input eightoutput decoder

a b c d e f g h

x y z

g N. B. Dodge 09/12

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Lecture #6: More Complex Combinational Logic Circuits

The University of T Th U i it f Texas at D ll t Dallas

Erik Jonsson School of Engineering and g g Computer Science

Definition of a Multiplexer

A multiplexer is a combinational logic circuit that has up to 2n inputs, an n-bit address, and one output. The multiplexer connects one of the inputs to the output, depending on the value of the n-bit address. The n bit address is decoded, just as we have studied in the last n-bit five slides. Thus the multiplexer uses a decoder and a selector circuit (which we will see in a subsequent s de) to tie o e o its inputs to its w subseque slide) o e one of s pu s o s output. The multiplexer is usually symbolized by the abbreviation MUX as the symbol for its function. yLecture #6: More Complex Combinational Logic Circuits N. B. Dodge 09/12

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The University of T Th U i it f Texas at D ll t Dallas

Erik Jonsson School of Engineering and g g Computer Science

Multiplexer: An Input to Output Selector

The truth table for a multiplexer is shown below. Assume a 4-input MUX, with inputs labeled a, b, c, d. 4 input Then there must be two address lines, x (MSB) and y (LSB). The output is denoted as f.

x 0 0 1 111

y 0 1 0 1

f a b c d N. B. Dodge 09/12

Lecture #6: More Complex Combinational Logic Circuits

The University of T Th U i it f Texas at D ll t Dallas

Erik Jonsson School of Engineering and g g Computer Science

Components of a Multiplexera b c d y x Selector* Note that the multiplexer has a 1-bit output.

f Output*

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Decoder The multiplexer is shown above, with the various parts of the circuit labeled.Lecture #6: More Complex Combinational Logic Circuits N. B. Dodge 09/12

The University of T Th U i it f Texas at D ll t Dallas

Erik Jonsson School of Engineering and g g Computer Science

Differences in Decoder and Multiplexer

Decoder: A decoder has n inputs, which are called the address. A decoder has up to 2n outputs ( t ca have t at many, maximum; but it decode as (it can ave that a y, a u ; t might have less). Each output line is true (or 1) for a specific combinations of the input lines, called the address.

Multiplexer: A multiplexer has two sets of inputs: n address lines (just like the decoder) and as many as 2n inputs, one of which is selected by each address for output (it may have less inputs). A multiplexer has only one output. The output is the value of the input selected by the address.

Thus we see that a decoder makes up a part of a multiplexer.Lecture #6: More Complex Combinational Logic Circuits

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N. B. Dodge 09/12

The University of T Th U i it f Texas at D ll t Dallas

Erik Jonsson School of Engineering and g g Computer Science

Exercise 2