2001TitleAbstractKeywordsSubjectAuthorsAffiliationVolNopp_startpp_endYearCurrent Status and Prospects of FET-type Ferroelectric MemoriesCurrent status and prospects of FETtype FeRAMs (ferroelectric random access memories) are reviewed. First, it is described that the most important issue for realizing FET-type FeRAMs is to improve the data retention characteristics of ferroelectric-gate FETs. Then, necessary conditions to prolong the retention time are discussed from viewpoints of materials, device structure, and circuit configuration. Finally, recent experimental results related to the FET-type memories are introduced, which include optimization of a buffer layer that is inserted between the ferroelectric film and a Sisubstrate, development of a new ferroelectric film with a small remnant polarization value, proposal and fabrication of a 1T2C-type memory cell with good retention characteristics, and so on.Ferroelectric, FeRAM, ferroelectricgate FET, data retention, SrBi2Ta2O9, (Bi,La)4Ti3O12.Fabrication ProcessHiroshi IshiwaraManuscript received February 10, 2001; revised March 12, 2001.Frontier Collaborative Research Center, Tokyo Institute of Technology, 4259 Nagatsuda, Midoriku, Yokohama, 226-8503, Japan.(e-mail : ishiwara@pi.titech.ac.jp)111142001A Technique for Analyzing LSI Failures Using Wafer-level Emission Analysis SystemCurrent leakage is the major failure mode of semiconductor device characteristic failures. Conventionally, failures such as short circuit breaksand gate breakdowns have been analyzed and the detected causes have been reflected in the fabrication process. By using a wafer-level emission-leakage failure analysis method (in-line QC), we analyzed leakage mode failure, which is the major failure detected during the probe inspection process for LSIs, typically DRAMs and CMOS logic LSIs. We have thus developed a new technique that copes with the critical structural failures and random failures that directly affect probe yields.Emission microscope, standby current failure, hot carrier injection mechanism, inverted confoca-laser microscope.Fabrication ProcessYasuhisa Higuchi, Yasumasa Kawaguchi, and Tatsumi SakazumeManuscript received February 10, 2001; revised March 12, 2001.Device Development Center, Hitachi Ltd. 16-3 Shinmachi 6-chomeOme-shi, Tokyo, 198-8512, Japan.(email: y-higu@ddc.hitachi.co.jp)1115192001A SDR/DDR 4Gb DRAM with 0.11 m DRAM TechnologyA 1.8V 650 mm2 4Gb DRAM having 0.10 m2 cell size has been successfully developed using 0.11 m DRAM technology. Considering manufactur-ability, we have focused on developing patterning technology using KrF lithography that makes 0.11 m DRAM technology possible. Furthermore,we developed novel DRAM technologies, which will have strong influence on the future DRAM integration. These are novel oxide gap-filling, W-bitline with stud contact for borderless metal contact, line-type storage node self-aligned contact (SAC), mechanically stable metal-insulator-silicon (MIS) capacitor and CVD Al process for metal interconnections. In addition, 80 nm array transistor and sub-80 nm memory cell contact are also developed for high functional yield as well as chip performance. Many issues which large sized chip often faces are solved by novel design approaches such as skew minimizing technique, gain control pre-sensing scheme and bit line calibration scheme.DRAM, Process integration, KrF lithography, MIS Capacitor, self-aligned contact.DevicesKinam KimManuscript received February 10, 2001; revised March 12, 2001.The anthor is with Technology Development, Memory Device Business, Samsung Electronics Co., San #24, Nongseo-Lee, Kiheung-Eup, Yongin-City, Kyungki-Do, Korea.(e-mail : kkne414@samsong.co.kr)1120302001W Polymetal Gate Technology for Giga Bit DRAMW polymetal gate technology for giga bit DRAM are presented. Key module processes for polymetal gate are studied in detail. W/WNx/polysiliconadopted for a word line of 256Mbit DRAM has good gate oxide integrity and junction leakage characteristics through full integration, which is comparable to those of conventional WSix/Polysilicon gate process. These results undoubtedly show that W/WNx/poly-silicon is the strongest candidate as a word line for Giga bit DRAM.semiconductor, DRAM, process integration, metal gate process, reliability.DevicesJong Wan Jung, Sang Beom Han, and Kyungho LeeManuscript received February 10, 2001; revised March 12, 2001.J. Jung and S. Han are with Hyundai Electronics Industries Co.,Ltd., 1 Hangjung-dong, Chungju, 361-725, Korea. (e-mail:jwanjung @hei.co.kr)K. Lee is with Hongik University, Chochiwon, 339-701, Korea.1131392001Characteristics of Si Nano-Crystal MemoryWe have developed a repeatable process of forming uniform, small-size and high-density selfassembled Si nano-crystals. The Si nano-crystalswere fabricated in a conventional LPCVD (low pressure chemical vapor deposition) reactor at 620 oC for 15 sec. The nano-crystals were spherical shaped with about 4.5 nm in diameter and density of 51011/cm2. More uniform dots were fabricated on nitride film than on oxide film. To take advantage of the abovementioned characteristics of nitride film while keeping the high interface quality between the tunneling dielectrics and the Si substrate, nitrideoxide tunneling dielectrics is proposed in n-channel device. For the first time, the single electron effect at room temperature, which shows a saturation of threshold voltage in a range of gate voltages with a periodicity of VGS 1.7 V, corresponding to single and multiple electron storage is reported. The feasibility of p-channel nano-crystal memory with thin oxide in direct tunneling regime is demonstrated. The programming mechanisms of p-channel nano-crystal memory were investigated by charge separation technique. For small gate programming voltage, hole tunneling component from inversion layer is dominant. However, valence band electron tunneling component from the valence band in the nano-crystal becomes dominant for large gate voltage. Finally, the comparison of retention between programmed holes and electrons shows that holes have longer retention time.Nano-crystal, coulomb blockade, direct tunnelling, quantum dot, EEPROM.DevicesKwangseok Han, Ilgweon Kim, and Hyungcheol ShinManuscript received February 10, 2001; revised March 12, 2001.K. Han and H. Shin are with the Integrated Systems Laboratory,Korea Advanced Institute of Science and Technology, 373-1, Kusongdong, Yusong-gu, Taejon, 305-701, Korea.(e-mail: hcshin@ee.kaist.ac.kr).I. Kim is now with the Hyundai Microelectronics, Hungdoek-gu, Chungju, 361-725, Korea.1140492001High-Speed Signaling in SDARM Bus Interface Channels : ReviewThree kinds of high-speed signaling methods for synchronous DRAM (SDRAM) bus interface channels (PC-133, Direct-Rambus, and SSTL-2) were analyzed in terms of the timing budget and the physical transmission characteristics. To analyze the SDRAM bus interface channels, loss mechanisms and the effective characteristic impedance method were reviewed and the ABCD matrix method was proposed as an analytic and yet accurate method. SPICE simulations were done to get the AC responses and the eye patterns of the three SDRAM bus interface channels for performancecomparisons. Recent progress and future trend for SDRAM bus interface standards were reviewed.SDRAM bus interface channel, highspeed signaling, PC-133, Direct-Rambus, SSTL-2CircuitsHong June Park, Young Soo Sohn, Jin Seok Park, Seung Jun Bae, and Seok Woo ChoiManuscript received February on 10, 2001; revised on March 12,2001. The authors are with Dept. Electrical and Computer Engineering,Pohang University of Science and Technology (POSTECH), PohangKyungbuk, 790-784, Korea (e-mail: hjpark@postech.ac.kr).1150692001RF MEMS Devices for Wireless ApplicationsIn this paper, the recent progress of RF MEMS research for wireless/mobile communications is reviewed. The RF MEMS components reviewed in this paper include RF MEMS switches, tunable capacitors, high Q inductors, and thin film bulk acoustic resonators (TFBARs) to become core components for constructing miniaturized on chip RF transceiver with multi-band and multi-mode operation. Specific applications are also discussed for each of these components with emphasis on for miniaturization, integration, and performance enhancement of existing and future wireless transceiver developments.RF MEMS switches, tunable capacitors, high Q inductors, TFBARs, wireless applications.MEMSJae Y. Park, Jong U. Bu, and Joong W. LeeManuscript received February 10, 2001; revised March 12, 2001.J. Park, J. Bu, and J. Lee are with the Materials and Devices Laboratory, LG Electronics Institute of Technology,16 Woomyeon-Dong, Seocho-Gu, Seoul, 137-724, Korea.(e-mail: jpark41@LG-Elite.com), (e-mail: jwlee@LG-Elite.com).1170832001Electromagnetic Micro x-y Stage for Probe-Based Data StorageAn electromagnetic micro x-y stage for probe-based data storage (PDS) has been fabricated. The x-y stage consists of a silicon body inside which planar copper coils are embedded, a glass substrate bonded to the silicon body, and eight permanent magnets. The dimensions of flexures and copper coils were determined to yield 100 m in x and y directions under 50 mA of supplied current and to have 440 Hz of natural frequency. For the application to PDS devices, electromagnetic stage should have flat top surface for the prevention of its interference with multi-probe array, and have coils with low resistance for low power consumption. In order to satisfy these design criteria, conducting planar copper coils have been electroplated within silicon trenches which have high aspect ratio (5 m in width and 30 m in depth). Silicon flexures with a height of 250 m werefabricated by using inductively coupled plasma reactive ion etching (ICP-RIE). The characteristics of a fabricated electromagnetic stage were measured by using laser doppler vibrometer (LDV) and dynamic signal analyzer (DSA). The DC gain was 0.16 m/mA and the maximum displacement was 42 m at a current of 180 mA. The measured natural frequency of the lowest mode was 325 Hz. Compared with the designed values, the lower natural frequency and DC gain of the fabricated device are due to the reversetapered ICP-RIE process and the incomplete assembly of the upper-sided permanent magnets for LDV measurements.Probe-based data storage, micro x-y stage, electromagnetic force, copper coil, electroplating.MEMSJae-joon Choi, Hongsik Park, Kyu Yong Kim, and Jong Up JeonManuscript received February 10, 2001; revised March 12, 2001.J.-J. Choi, H. Park, K. Y. Kim, and J. U. Jeon are with the MEMS Lab., Samsung Advanced Institute of Technology, San 14-1, Nongseori, Kihung-eup, Yongin-si, Kyonggi 449-712, Korea.(e-mail: jeon@sait.samsung.co.kr)1184932001Effect of Hydrogen Treatment on Electrical Properties of Hafnium Oxide for Gate Dielectric ApplicationHafnium oxide thin films for gate dielectric were deposited at 300 on p-type Si (100) substrates by plasma enhanced chemical vapor deposition (PECVD) and annealed in O2 and N2 ambient at various temperatures. The effect of hydrogen treatment in 4% H2 at 350 for 30 min on the electrical properties of HfO2 for gate dielectric was investigated. The flat-band voltage shifts of HfO2 capacitors annealed in O2 ambient are larger than those in N2 ambient because samples annealed in high oxygen partial pressure produces the effective negative charges in films. The oxygen loss in HfO2 films was expected in forming gas annealed samples and decreased the excessive oxygen contents in films as-deposited and annealed in O2 or N2 ambient. The CET of films after hydrogen forming gas anneal almost did not vary compared with that before hydrogen gas anneal. Hysteresis of HfO2 films abruptly decreased by hydrogen forming gas anneal because hysteresis in C-V characteristics depends on the bulk effect rather than HfO2/Si interface. The lower trap densities of films annealed in O2 ambient than those in N2 were due to the composition of interfacial layer becoming closer to SiO2 with increasing oxygen partial pressure. Hydrogen forming gas anneal at 350 for samples annealed at various temperatures in O2 and N2 ambient plays critical role in decreasing interface trap densities at the Si/SiO2 interface. However, effect of forming gas anneal was almost disappeared for samples annealed at high temperature (about 800) in O2 or N2 ambient.Gate dielectrics, HfO2, PECVD, hydrogen annealing, MOSFET.Fabrication ProcessKyu-Jeong Choi, Woong-Chul Shin, and Soon-Gil YoonManuscript received June 4, 2001; revised June 22, 2001.Department of Materials Engineering, Chungnam National University,Daeduk Science Town, 305-764, Taejon, Korea(e-mail: sgyoon@cnu.ac.kr).12951022001On the Gate Oxide Scaling of Sub-100nm CMOS TransistorsGate oxide scaling for sub-100 CMOS devices has been studied. Issues on the gate oxide scaling are reviewed, which are boron penetration, reliability, and direct tunneling leakage currents. Reliability of Sub-2.0 oxides and the device performance degradation due to boron penetration are investigated. Especially, the effect of gate leakage currents on the transistor characteristics is studied. As a result, it is proposed that thinner oxides than previous expectations may be usable as scaling proceeds. Based on the gate oxide thickness optimization process we have established, high performance CMOS transistors of Lgate=70 and Tox=1.4 were fabricated, which showed excellent current drives of 860/ (NMOS) and 350/ (PMOS) at Ioff=10/ and Vdd=1.2V, and CV/I of 1.60ps (NMOS) and 3.32ps (PMOS).Gate oxide, CMOS, scaling, gate leakage, boron penetrationDevicesSeungheon Song, Jihye Yi, Woosik Kim, Kazuyuki Fujihara, Ho-Kyu Kang, Joo-Tae Moon, and Moon-Yong LeeManuscript received June 10, 2001; revised June 25, 2001.The authors are with Samsung Electronics Co., San #24, Nongseo-lee, kiheung- Eup, Yongin-city, Kyungki-Do, Korea.(e-mail : Shsong1@Samsung.co.kr) Tel : +82-31-209-3878121031102001Fabrication and Characterization of 0.2m InAlAs/InGaAs Metamorphic HEMT's with Inverse Step-Graded InAlAs Buffer on GaAs SubstrateMetamorphic InAlAs/InGaAs HEMT are successfully demonstrated, exhibiting several advantages over conventional P-HEMT on GaAs and LM-HEMT on InP substrate. The strain-relaxed metamorphic structure is grown by MBE on the GaAs substrate with the inverse-step graded InAlAs metamorphic buffer. The device with 40% indium content shows the better characteristics than the device with 53% indium content. The fabricated metamorphic HEMT with 0.2m T-gate and 40% indium content shows the excellent DC and microwave characteristics of Vth=-0.65V, gm,max=620 mS/mm, fT=120GHz and fmax=210GHz.GaAs, HEMT, InGaAs, metamorphic, M-HEMT, PowerDevicesDae-Hyun Kim, Sung-Won Kim, Seong-Chul Hong, Seung-Won Paek, Jae-Hak Lee, Ki-Woong Chung, and Kwang-Seok SeoManuscript received June 10, 2001; revised June 25, 2001.The authors are with School of Electrical Engineering & Computer Science, Seoul National University San 56-1, Shinlim-dong, Kwanak-gu, Seoul, 151-742, Korea(e-mail : vtsrc3@hanmail.net) Tel : +82-2-880-5451121111152001POPeye : A System Analysis Simulator for DRAM Performance EvaluationWe implemented POPeye (Probe of Performance + eye), a system analysis simulator to evaluate DRAM performance in a personal computer environment. When running any real-life application programs such as Microsoft Office and Paint Shop Pro on Windows OS, POPeye simulates detailed transactions between a CPU and a memory system. Using this tool, we comparatively analyzed the performance of a DDR-SDRAM, a D-RDRAM, and a DDR-FCRAM.popeye, simulator, DRAM, Performance, WindowsCircuitsKangmin Lee, Chi-Weon Yoon, Ramchan Woo, Jeong-Hun Kook, Yon-Kyun Im, and Hoi-Jun YooManuscript received May 28, 2001; revised June 23, 2001.Detp. of Electvical Engineering, kaist 373-1 kusong-dong, Yusong-gu, Taejon, 305-701, Korea.(e-mail : kangmin@eeinfo.kaist.ac.kr)121161242001A Word Line Ramping Technique to Suppress the Program Disturbance of NAND Flash MemoryWhen the program voltage is applied to a word line, a part of the boosted channel charge in inhibited bit lines is lost due to the coupling between the string select line (SSL) and the adjacent word line. This phenomenon causes the program disturbance in the cells connected to the inhibited bit lines. This program disturbance becomes more serious, as the word line pitch is decreased. To reduce the word line coupling, the rising edge of the word-line voltage waveform was changed from a pulse step into a ramp waveform with a controlled slope. The word-line ramping circuit was composed of a timer, a decoder, a 8 b D/A converter, a comparator, and a high voltage switch pump (HVSP). The ramping voltage was generated by using a stepping waveform. The rising time and the stepping number of the word-line voltage for programming were set to 5- and 8, respectively,. The ramping circuit was used in a 512Mb NAND flash memory fabricated with a 0.15-m CMOS technology, reducing the SSL coupling voltage from 1.4V into a value below 0.4V.NAND Flash memory, Word Line Ramping Circuit, Program Disturbance, SSL Coupling, Word Line SlopeCircuitsJin-Wook Lee, Yeong-Taek Lee, Taehee Cho, Seungjae Lee, Dong-Hwan Kim, Wook-Ghee, Hahn, Young-Ho Lim, and Kang-Deog SuhManuscript received May 28, 2001; revised June 23, 2001.Jin-Wook Lee NVM Team, Memory Division, Semiconductor Business Samsung Electronics CO., LTD.. San #24 Nongseo-Ri, Kiheung-Eup, Yongin-City Kyunggi-Do 449-711, Korea.(e-mail : pomb@samsung.co.kr) Tel : +82-31-209-4460, Fax : +82-31-209-4505121251312001Uniformity Improvement of Micromirror Array for Reliable Working Performance as an Optical Modulator in the Maskless Photolithography SystemWe considered the uniformity of fabricated micromirror arrays by characterizing the fabrication process and calculating the appropriate driving voltages of micromirrors used as virtual photomask in maskless photolithography. The uniformity of the micromirror array in terms of driving voltage and optical characteristics is adversely affected by factors, such as the air gap between the bottom electrode and the mirror plate, the spring shape and the deformation of the mirror plate or torsion spring. The thickness deviation of the photoresist sacrificial layer, the misalignment between mirror plate and bottom electrode, the aluminum deposition condition used to produce the spring and the mirror plate, and initial mirror deflection were identified as key factors. Their importance lies in the fact that they are related to air gap deviations under the mirror plate, asymmetric driving voltages in left and right mirror directions, and the deformation of the Al spring or mirror plate after removal of the sacrificial layer. The plasma ashing conditions used for removing the sacrificial layer also contributed to the deformation of the mirror plate and spring. Driving voltages were calculated for the pixel operation of the micromirror array, and the non-uniform characteristics of fabricated micromirrors were taken into consideration to improve driving performance reliability.Micromirror array, uniformity improvement, mirror operation, maskless photolithography applications.MEMSKook-Nyung Lee and Yong-Kweon KimManuscript received February 10, 2001; revised March 12, 2001.School of Electrical Engineering & Computer Science, Seoul National University, San 56-1, Shinlim-dong, Kwanak-gu, Seoul, 151-742, Korea(e-mail : plummy@chollian.net) Tel : +2-888-5027, Fax : +2-873-9953121321392001Integration Process and Reliability for SrBi2 Ta2O9-based Ferroelectric MemoriesHighly reliable packaged 64kbit fe-rroelectric memories with 0.8 m CMOS ensuring ten-year retention and imprint at 125 oC have been successfully developed. These superior reliabilities have resulted from steady integration schemes free from the degradation, due to layer stress and attacks of process impurities. The resent results of research and development for ferroelectric memories at Hynix Semiconductor Inc. are summarized in this invited paper.thermal stress, moisture, hydro-gen, reliability, FeRAM, imprint, retention, ferroelec-tric, 1T/1C, 2T/2CFabrication ProcessB. Yang, S. S. Lee, Y. M. Kang, K. H. Noh, S. K. Hong, S. K. Hong, S. H. Oh., E. Y. Kang, S. W. Lee, J. G. Kim, C. W. Shu, J. Y. Seong, C. G. Lee, N. S. Kang, and Y. J. ParkManuscript received June 10, 2001; revised June 25, 2001.The authors are with Samsung Electronics Co., San #24, Nongseo-lee, kiheung- Eup, Yongin-city, Kyungki-Do, Korea.(e-mail : Shsong1@Samsung.co.kr) Tel : +82-2-209-3878131411572001Trapping and Detrapping of Transport Carriers in Silicon Dioxide Under Optically Assisted Electron InjectionBased on uniform hot carrier injection (optically assisted electron injection) across the Si-SiO2 interface into the gate insulator of n-channel IGFETs, the threshold voltage shifts associated with electron injection of 1.251016 e/cm2 between 0.5 and 7 MV/cm were found to decrease from positive to negative values, indicating both a decrease in trap cross section (Eox 1.5 MV/cm) and the generation of FPC (Eox 5 MV/cm). It was also found that FNC and large cross section NETs were generated for Eox 5 MV/cm. Continuous, uniform low-field (1MV/cm) electron injection up to 1019 e/cm2 is accompanied by a monatomic increase in threshold voltage. It was found that the data could be modeled more effectively by assuming that most of the threshold voltage shift could be ascribed to generated bulk defects which are generated and filled, or more likely, generated in a charged state. The injection method and conditions used in terms of injection fluence, injection density, and temperature, can have a dramatic impact on what is measured, and may have important implications on accelerated lifetime measurements.ionizing radiation, optically assisted electron injection, FPC, FNC, NHTs, NETsDevicesHongseog KiManuscript received August 27, 2001; revised September 3, 2001.Division of Information communication Engineering Paichai University Daejeon, Korea.(e-mail : khsau@mail.paichai.ac.kr) Tel : +82-2-209-3878131581662001Circuit Techniques for Low-Power Data Drivers of TFT-LCDsA stepwise driving method was used for reducing the AC power consumption in a TFT-LCD. The AC power takes the largest portion of the total power consumption of a TFT-LCD. Experimental results confirmed that the AC power saving efficiency reached up to 75% when a 5-stepwise driving with each step time of 2sec was applied to a 14.1 inch-diagonal XGA TFT-LCD. The second largest component of power consumption called the DC power comes from the quiescent currents in Op-amps. A simple and efficient architecture was proposed in this work to reduce this DC power consumption: Half of the Op-amps have the 5V-supplies, and the rest half have the 10V-supplies, and two Op-amps are shared by adjacent two channels. Measurements of test circuits showed that this simple method could reduce over 40% of the DC power consumption..Low-power, Stepwise charging, TFT-LCD, Data driverCircuitsByong-Deok Choi and Oh-Kyong KwonManuscript received August 31, 2001; revised Septerber 11, 2001.Hanyang. University, Division of Electrical and Computer Engineering 17 Hangdang-Dong, Seongdong-Gu, Seoul 133-791, Korea. (e-mail : okown7@chollian.net) Tel : +82-2-2290-0359 Fax : +82-2-2297-7701131671812001A High Performance Solenoid-Type MEMS InductorA solenoid-type MEMS inductor with a quality factor over 10 at 2 GHz has been developed using an electroplating technique. The integrated spiral inductor has a low Q factor due to substrate loss and skin effects. It also occupies a large area compared to the solenoid-type inductor. The direction of flux of the solenoid-type inductor is parallel to the substrate, which can lower the substrate loss and other interference with integrated passive components. To estimate the characteristics of the proposed inductor over a high frequency range, the 3D FEM (Finite Element Method) simulation is used by using the HFSS at the Ansoft corporation. The electroplated solenoid-type inductor is fabricated on a glass substrate step by step by using photolit-hography and copper electroplating. The fabrication process to improve the quality factor of the inductor is also developed. The achieved inductance varies within a range from 0.5 nH to 2.8 nH, and the maximum Q factor is over 10.solenoid, inductor, electroplating, MEMs, integrationMEMSSeonho Seok, Chul Nam, Wonseo Choi, and Kukjin ChnmManuscript received August 27, 2001; revised September 7, 2001.School of Electrical Engineering Seoul National University(e-mail : ssh@mintlab.snu.ac.kr)Tel : +82-2-880-5449 Fax : 82-287-6575131821882001A High Density MIM Capacitor in a Standard CMOS ProcessA simple metal-insulator-metal (MIM) capacitor in a standard 0.25 m digital CMOS process is described. Using all six interconnect layers, this capacitor exploits both the lateral and vertical electrical fields to increase the capacitance density (capacitance per unit area). Compared to a conventional parallel plate capacitor in the four upper metal layers, this capacitor achieves lower parasitic substrate capacitance, and improves the capacitance density by a factor of 4. Measurements and an extracted model for the capacitor are also presented. Calculations, model and measurements agree very well.Capacitors, MIM devices, Device modeling, Integrated circuit modeling, CMOS integrated circuits.DevicesChristian Rye IversenManuscript received August 27, 2001 ; revised September 3, 2001.Aalborg University Niels Jernes Vej 12, DK-9220 Aalborg, DENMARK. (e-mail :cri@kom.auc.dk) Tel : +45-9635-8679 Fax : +45-9815-6740131891922001Analog Delay Locked Loop with Wide Locking VangeFor wide locking range, an analog delay locked loop (DLL) was designed with the selective phase inversion scheme and the variable number of delay elements. The number of delay elements was determined adaptively depending on the clock cycle time. During the analog fine locking stage, a self-initializing 3-state phase detector was used to avoid the initial state problem associated with the conven-tional 3-state phase detector. With these schemes, the locking range of analog DLL was increased by four times compared to the conventional scheme accor-ding to the simulation results.Delay locked loop, wide locking rangeCircuitsChangsik YooManuscript received Stember1, 2001; revised Stember 25, 2001.DRAM. Design 3, Samsung Electronics, Nong-Seo-Ri 24, Kiheung, Yong-ln, Kyong-Ki-Do, 449-711, Korea.(e-mail : csyoo@ieee.org)Tel : +82-31-209-2927 Fax : +82-31-209-6154131931962001Mechanisms of Cl2 Molecules Dissociation in a Gas Discharge Plasma in Mixtures with Ar, O2, N2The influence of argon, oxygen, and nitrogen admixtures on the dissociation of Cl2 molecules in a glow discharge low-temperature plasma under the constant pressure conditions was investigated. For Cl2/Ar and Cl2/O2 mixtures, the concentration of chlorine atoms was observed to be a practically constant at argon or oxygen concentrations up to 50%. This invariability is a most probably explained by relative increase in rate of Cl2 direct electron impact dissociation due to the changes in electrophysical parameters of plasma such as EEDF, electron drift rate and mean energy. For all the considered mixtures, the contribution of stepwise dissociation involving active species from gas additives (metastable atoms and molecules, vibrationally excited molecules) was found to be negligible.Chlorine, Dissociation, Electron impact, rate constantFabrication ProcessA. M. Efremov and Kwang-Ho KwonManuscript received August 12, 2001; revised September 7, 2001.Department of Electonics, Hanseo University, 360 Daegok-Ri Haemi-Myun Chung-Nam 356-820 Korea(E-mail: amefremov@mail.ru) Tel: +7-0932-329194141972012001Electrical and Chemical Properties of ultra thin RT-MOCVD Deposited Ti-doped Ta2O5In Recent results suggested that doping T2O5 with a small amount of TiO2 using standard ceramic processing techniques can increase the dielectric constant of Ta2O5 significantly. In this paper, this concept is studied using RTCVD (Rapid Thermal Chemical Vapor Deposition). Ti-doped Ta2O5 films are deposited using TaC12H30O5N, C8H24N4Ti, and O2 on both Si and NH3-nitrided Si substrates. An NH3-based interface layer at the Si surface is used to prevent interfacial oxidation during the CVD process and post deposition annealing is performed in H2/O2 ambient to improve film quality and reduce leakage current. A sputtered TiN layer is used as a diffusion barrier between the Al gate electrode and the TaTixOy dielectric. XPS analyses confirm the formation of a (T2O5)1-x(TiO2)x composite oxide. A high quality TaTixOy gate stack with EOT (Equivalent Oxide Thickness) of 7 and leakage current Jg=0.5/cm2 @ Vg=-1.0V has been achieved. We have also succeeded in forming a TaTixOy composite oxide by rapid thermal oxidation of the as-deposited CVD TaTi films. The electrical properties and Jg-EOT characteristics of these composite oxides are remarkably similar to that of RTCVD Ta2O5 is not affected by the addition of TiO2.High K gate dielectric, Metal gate, CMOS Fabrication processFabrication ProcessS. J. Lee, H. F. Luan, A. Mao, T. S. Jeon, C. H. Lee, Y. Senzaki, D. Roberts, and D.L. KwongManuscript received August 12, 2001; revised September7, 2001.Microelectronics Research Center, Department of Electrical and Computer Engineering, The University of Texas, Austin, TX 78712, USA. SCHUMACHER, CALSBAD, CA 92009, USA 10100 Burnet Road, MER 2.604 Bldg., Austin TX78758, USA (e-mail :sungjoo@mail.utexas.edu)Tel : +1-512-471-4759142022082001Frequency-Dependent Line Capacitance and Conductance Calculations of On-ChipInterconnects on Silicon Substrate Using Fourier Cosine Series ApproachIn this paper a method for analysis and modeling of coplanar transmission interconnect lines that are placed on top of silicon-silicon oxide substrates is presented. The potential function is expressed by series expansions in terms of solutions of the Laplace equation for each homogeneous region of layered structure. The expansion coefficients of different series are related to each other and to potentials applied to the conductors via boundary conditions. In the plane of conductors, boundary conditions are satisfied at Nd discrete points with Nd being equal to the number of terms in the series expansions. The resulting system of inhomogeneous linear equations is solved by matrix inversion. No iterations are required. A discussion of the calculated line admittance parameters as function of width of conductors, thickness of the layers, and frequency is given. The interconnect capacitance and conductance per unit length results are given and compared with those obtained using full wave solutions, and good agreement have been obtained in all the cases treatedInterconnects, Doplanar strip line, Fourier series approach, silicon substrate, point matching procedureDevicesH. Ymeri, B. Nauwelaers, S Vandenberghe, L. Maex, D. De Roest, and M. StucchiManuscript received September 11, 2001; revised November 6, 2001.H. Ymeir, B. Nauwelaers, and S. Vandenberghe are with Kathoolieke Universiteit Leuven, Deoartment of Electrical Engneering(ESAT, Div, ESAT-TEEMIC, Kasteelpark Arenberg 10, B-3001 Leuven-Heverlee, Belgium.(email : hasan.ymeri@esat.kuleuven.ac.be)K. Maex, D. De Roest, and M. Stucchi are with IMEC, Leuren, Belgium142092152001Antifuse Circuits and Their Applications to Post-Package of DRAMSSeveral methods for improving device yields and characteristics have been studied by IC manufacturers, as the options for programming components become diversified through the introduction of novel processes. Especially, the sequential repair steps on wafer level and package level are essentially required in DRAMs to improve the yield. Several repair methods for DRAMs are reviewed in this paper. They include the optical methods (electrical-fuse, ONO-antifuse). These methods can also be categorized into the wafer-level(on wafer) and the package-level(post-package) repair methods. Although the wafer-level laser-fuse repair method is the most widely used up to now, the package-level antifuse repair method is becoming an essential auxiliary technique for its advantage in terms of cost and design efficiency. The advantages of the package-level antifuse method are discussed in this paper with the measured data of manufactured devices. With devices based on several processes, it was verified that the antifuse repair method can improve the net yield by more than 2%~3%. Finally, as an illustration of the usefulness of the package-level antifuse repair method, the repair method was applied to the replica delay circuit of DLL to get the decrease of clock skew from 55ps to 9ps.High K gate dielectric, Metal gate, CMOS Fabrication processCircuitsJae-Kyung Wee, Jeong-Hoon Kook, Se-Jun Kim, Sang-Hoon Hong, and Jin-Hong AhnManuscript received November 8, 2001; revised December 4, 2001.Advanced Design Technology team, Memory R&D, Hynix Semiconductor Inc., San 136-1 ami-ri, Bubal-eub, Ichon-si, Kyoungki-do, 467-701, Korea.(e-mail : jaekyung.wee@hynix.com) Tel : +82-31-639-1774142162312001A Photosensitive Glass Chip for DNA Purification o Nucleic Acid Probe AssayA new DNA purification chip is proposed and fabricated for the sample preparation of Nucleic Acid(NA)probe assay. The proposed DNA purification chip is fabricated using photosensitive glass substrate and polydimethylsiloxane (PDMS) cover fixture. We have successfully captured and eluted the DNA using the fabricated photosensitive glass chip. The fabricated DNA purification chip showed a binding capacity of 15ng/cm2 and a minimum extractable input concentration of 100copies/200uL. The proposed DNA purification chip can be applied for low-cost, disposable sample preparation of NA probe assays.photosensitive glass, DNA, purification, sample preparation, bio-MEMSMEMSJoon-Ho Kim, Byung-Gyun Kim, Jun-Bo Yoon and Euisik YoonManuscript received August 12, 2001; revised September 7, 2001.Department of Electrical Engneering and Computer Science(Division of E.E), Korea advanced Institue of Science and Technology(KAIST) 373-1, Guseong-dong, Yuseong-gu, Daejeon, 305-701, Republic of Korea (e-mail :mythos@iml.kaist.ac.kr) Tel : +82-42-869-5462142322382001Micro-Imaging Techniques for Evaluation of Plastic Microfluidic ChipThe Fluorescence-Activated Cell Sorter(FACS) is a well-established instrument used for identifying, enumerating, classifying and sorting cells by their physical and optical characteristics. For a miniaturized FACS device, a disposable plastic microchip has been developed which has a hydrodynamic focusing chamber using soft lithography. As the characteristics of the spatially confined sample stream have an effect on sample throughput, detection efficiency, and the accuracy of cell sorting, systematic fluid dynamic studies are required. Flow visualization is conducted with a laser scanning confocal microscopy (LSCM), and three dimensional flow structure of the focused sample stream is reconstructed from 2D slices acquired at 1um intervals in depth. It was observed that the flow structure in the focusing chamber is skewed by unsymmetrical velocity profile arising from trapezoidal cross section of the microscopic flow structure, Confocal Micro-PIV system has been developed to evaluate the accelerated flow field in the focusing chamber. This study proposes a method which defines the depth of the measurement volume using a detection pinhole. The trajectories of red blood cells(RBCs) and their interactions with surrounding flow field in the squeezed sample stream are evaluated to find optimal shape of the focusing chamber and fluid manipulation scheme for stable cell transporting, efficient detection, and sortingFACS, microfluidics, microchip, soft lithography, hydrodynamic focusingMEMSJung Kyung Kim, Hyunwoo Bang, Yongku Lee, Chanil Chung, Jung Yul Yoo, Sang Sik Yang, Jin Seung Kim, Sekwang Park, Jun Keun ChangManuscript received August 12, 2001; revised September 7, 2001.J. K. Kim are with Biomedlab Co.H. Bang, Y. Lee, and with J. Y. Yoo are with School of Mechanical and Aerospace Engineering, Seoul National University.C. Chung is with Digital Bio Technology Co.S. S. Yang is with School of Electronics Engineering, Ajou University.J. S. Kim is with School of Science and Technology, Chonbuk National University.S. Park is with School of Electronics and Electrical Engineering, Kyungpook National University.K. Chun, and J. K. Chang are with School of Electrical Engineering and Computer Science, seoul National University.(e-mail : jkchang@amed.snu.ac.kr) Tel : +2-880-1766142392472001Adjustable-Performance, Single-Ended Input Double-Balanced MixerA noble single-ended input, double-balanced mixer topology is proposed. The mixer incorporates the common-source amplifier input stage with inductive degeneration for impedance matching. The analysis based on simulations shows that the overall performance of the mixer is excellent and is adjustable by varying the input transistor size to give best characteristics for the given linearity specificationsRF, Mixer, CMOS, Noise FigureCircuitsJin-Yong Choi, Kyung-Ho Lee, and Sang-Gug LeeManuscript received November 5, 2001; revised November 27, 2001.J. Choi and K lee are with School of Electrical, Electronics, and Computer Engineering, Hongik University, Jochiwon, Yongi Gun, Chungnam, 339-701, Korea.(e-mail : jychoi@wow.hongik.ac.kr) Tel : +82-41-860-2548S. Lee is with School of Engineering, Information and Communications University, 58-4, Hwaam-dong, Yusong-gu, Daejon, 305-348, Korea.142482522001

2002TitleAbstractKeywordsSubjectAuthorsAffiliationVolNopp_startpp_endYearAccurate Formulas for Frequency-Dependent Resistance and Inductance per Unit Lenth of On-Chip Interconnects on Lossy Silicon SubstrateA new closed-form expressions to calculate frequency-dependent distributed inductance and the associated distributed series resistance of single interconnect on a lossy silicon substrate (CMOS technology) are presented. The proposed analytic model for series impedance is based on a self-consistent field method and the vector magnetic potential equation. It is shown that the calculated frequency-dependent distributed inductance and the associated resistance are in good agreement with the results obtained from rigorous full wave solutions and CAD-oriented equivalent-circuit modeling approachOn-chip interconnects, MIS microstrip, self-consistent method, quasi-magnetostatic procedure, skin effect.DevicesH.Ymeri, B.Nauwelaers, K.Maex, D. De Roest, S. Vandenberghe, and M. StucchiManuscript received January 2, 2002; revised March 7, 2002.H. Ymeri, B. Nauwelaers, and S. Vandenberghe are with Katholieke Universiteit Leuven, Department of Electrical Engineering(ESAT), Div. ESATTELEMIC, Kasteelpark Arenberg 10, B-3001 Leuven-Heverlee, Belgium. (e-mail : hasan.ymeri@esat.kuleuvan.ac.be)K. Maex, D. De Roest, and M. Stucchi are with The Interuniversity Microelectronics Center(IMEC), Kapeldreef 75, B-3001 Leuven, Belgium21162002Single-ended Differential RF Circuit Topologies Utilizing Complementary MOS DevicesSingle-ended differential RF circuit topologies fully utilizing complementary characteristics of both NMOS and PMOS are proposed, which have inherent advantage of both single-ended and differential circuits. Using this concept, we propose a CCPP (Complementary CMOS parallel push-pull) amplifier which has single-ended input/output with differential amplifying characteristics, leading to more than 30 dB improvement on IIP2. In addition, complementary resistive mixer is also proposed, which provides not only differential IF outputs from single-ended RF input, but much better linearity as well as isolation characteristics. Experimental results using 0.35 m CMOS process show that, compared with conventional NMOS resistive mixer, the proposed mixer shows 15 dB better LO-to-IF isolation, 4.6 dB better IIP2, and 4.5 dB better IIP3 performances.Single-ended, differential, RF, comple-mentary, MOSCircuitsBonkee Kim, Ilku Nam, and Kwyro LeeManuscript received January 30, 2002; revised March 25, 2002.RF Products, System LSI business, Semiconductor, Samsung Electronics, Suwon P.O.Box 105, Kyunggi do, Korea.Department of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology, 373-1, Kusong dong, Yusong ku, Taejon, 305-701, Republic of Korea.(e-mail : bonkee71@yahoo.co.kr) Tel : +82-42 869 5462 Fax : +82 42 869 8530217182002A Simple and Analytical Design 'Approach for Input Power Matched On-chip CMOS LNAA simple and analytical design approach for input power matched CMOS RF LNA circuits and their scaling for lower power consumption, is introduced. In spite of the simplicity of our expressions, it gives excellent agreement with numerical simulation results using commercial CAD tools for several circuit examples performed at 2.4GHz using 0.18m CMOS technology. These simple and analytical results are extremely useful in that they can provide enough insights not only for designing any CMOS LNA circuits, but also for characterizing and diagnosing them whether being prototyped or manufactured.Low Noise Amplifier, Low Power CMOS RF Amplifier, Noise Figure, Input Power Matching, Source Degeneration.CircuitsTae Wook Kim and Kwyro LeeManuscript received January 12, 2002; revised March 7, 2002.Dept. of EECS and MICROS Research Center KAIST 373-1, Kusong, Yusong, Daejon, 305-701, Republic of Korea(e-mail : krlee@ee.kaist.ac.kr) Tel : +82-42 869 343321192920022.45GHz CMOS Up-conversion Mixer and LO Buffer DesignA 2.45GHz double-balanced modified Gilbert-type CMOS up-conversion mixer design is introduced, where the PMOS current-reuse bleeding technique is demonstrated to be efficient in improving conversion gain, linearity, and noise performance. An LO buffer is included in the mixer design to perform single-ended to differential conversion of the LO signal on chip. Simulation results of the design based on careful modeling of all active and passive components are examined to explain in detail about the characteristic improvement and degradation provided by the proposed design. Two kinds of chips were fabricated using a standard 0.35m CMOS process, one of which is the mixer chip without the LO buffer and the other is the one with it. The measured characteristics of the fabricated chips are quite excellent in terms of conversion gain, linearity, and noise, and they are in close match to the simulation results, which demonstrates the adequacy of the modeling approach based on the macro models for all the active and passive devices used in the design. Above all the benefits provided by the current-reuse bleeding technique, the improvement in noise performance seems most valuable.mixer, CMOS, bleeding, reuse, bufferCircuitsJin-Young Choi, Sang-Gug Lee, Seok-Bong Hyun, Kyung-Hwan Park, and Seong-Su ParkManuscript received January 16, 2002; revised March 12, 2002.*School of Electrical, Electronics, and Computer Engineering, Hongik University, Jochiwon, Yongi Gun, Chungnam, 339-701, Korea**School of Engineering, Information and Communications University, 58-4, Hwaam-dong, Yusong-gu, Daejon, 305-348, Korea***ETRI-Microelectronics Technology Laboratory, 161 Gajong-dong, Yusong-gu, Daejon, 305-600, Korea(e-mail : jychoi@www.hongik.ac.kr) Tel : +82-41-860-25482130402002Fractional-N Frequency Synthesizer with a 1-bit Hig-Order Interpolative Modulator for 3G Mobile Phone ApplicationThis paper presents a 18-mW, 2.5-GHz fractional-N frequency synthesizer with 1-bit 4th-order interpolative delta-sigma () modulator to suppress fractional spurious tones while reducing in-band phase noise. A fractional-N frequency synthesizer with a quadruple prescaler has been designed and implemented in a 0.5-m 15-GHz ft BiCMOS. Synthesizing 2.1 GHz with less than 200 Hz resolution, it exhibits an in-band phase noise of less than 85 dBc/Hz at 1 kHz offset frequency with a reference spur of 85 dBc and no fractional spurs. The synthesizer also shows phase noise of 139 dBc/Hz at an offset frequency of 1.2 MHz from a 2.1GHz center frequency.phase-locked loop, fractional-N, frequency synthesizer, fractional spurs, reference spurs, phase noise, delta-sigma modulator, pulse swallow technique.CircuitsByeong-Ha ParkManuscript received January 7, 2002; revised March 7, 2002.RF Project, System-LSI, Device Solution Network, Business, Samsung Electronics, Suwon P.O. Box 105, Kyunggi-Do, 440-600, Korea(email : byeongha@samsung.co.kr)2141482002Monolithically Integrable RF MEMS PassivesThis paper presents high performanceMEMS passives using fully CMOS compatible,monolithically integrable 3-D RF MEMS processesfor RF and microwave applications. The 3-D RFMEMS technology has been developed andinvestigated as a viable technological option, whichcan break the limit of the conventional IC technology.We have demonstrated the versatility of thetechnology by fabricating various 3-D thick-metalmicrostructures for RF and microwave applications,such as spiral/solenoid inductors, transformers, andtransmission lines, with a vertical dimension of up to100 m. To the best of our knowledge, we report thatwe are the first to construct a fully integrated VCOwith MEMS inductors, which has achieved a lowphase noise of 124 dBc/Hz at 300 kHz offset from acenter frequency of 1 GHz.RF MEMS, surface micromachining, inductor, transformer, transmission line, VCO.MEMSEun-Chul Park, Yun-Seok Choi, Jun-Bo Yoon, and Euisik YoonManuscript received January 12, 2002; revised March 7, 2002.Department of Electrical Engineering and Computer Science(Division of Electrical Engineering) Korea Advanced Institute of Science and Technology 373-1, Guseong-dong, Yuseong-gu, Daejeon 305-701, Republic of Korea(e-mail : ecpark@iml.kaist.ac.kr) Tel : +82-42-869-5462 Fax : +82-42-869-85302149552002Spiral Inductor Design for Quality FactorA closed form expression for the quality factor of the spiral inductor, methodologically, is presented as a function of the inductance (Lind), metal-line width (W), spacing (S), inner and the diameter (Di). For a given inductance, the dependences of quality factor on W, S, and Di are analyzed, and suggested the design optimization guidelines.spiral inductors, silicon, RF Ics, quality factor.CircuitsSang-Gug Lee and Sin-Cheol KimManuscript received January 2, 2002; revised March 5, 2002.S. C. Kim is with Information and Communications University, P.O. Box 77, Yuseong, Daejeon 305-600, P. O. Korea.(e-mail : sglee@icu.ac.kr)S. G. Lee is with Hanb Elec & Tele, 270-1, Seohyun-dong, Boondang-gu, Seongnam, Gyonggi, 463-824, Korea2156582002A self-Consistent Semi-Analytical Model For AlGaAs/InGaAs PMHEMTsA semi-analytical model based on exact numerical analysis of the 2DEG channel in pseudo-morphic HEMT (PMHEMT) is presented. The exactness of the model stems from solving both Schrodingers wave equation and Poissons equation simultaneously and self-consistently. The analytical modeling of the device terminal characteristics in relation to the charge control model has allowed a best fit with the geometrical and structural parameters of the device. The numerically obtained data for the charge control of the channel are best fitted to analytical expressions which render the problem analytical. The obtained good agreement between experimental and modeled current/voltage characteristics and small signal parameters has confirmed the validity of the model over a wide range of biasing voltages. The model has been used to compare both the performance and characteristics of a PMHEMT with a competetive HEMT. The comparison between the two devices has been made in terms of 2DEG density, transfer characteristics, transconductance, gate capacitance and unity current gain cut-off frequency. The results show that PMHEMT outperforms the conventional HEMT in all considered parameters.Interconnects, Doplanar strip line, Fourier series approach, silicon substrate, point matching procedure.DevicesM. Abdel Aziz, M. El-Bannal, and M. El-SayedManuscript received February 25, 2002; revised March 12, 2002.Department Faculty of Engineering Alexandria University .(e-mail : mbanna@dataxprs.com.eg) Tel : +203-549-81082159692002A New Basic Element for Neural Logic Functions and Capability in Circuit ApplicationsThis paper describes a new basic element which shows a synaptic operation for neural logic applications and shows function feasibility. A key device for the logic operation is the insulated-gate pn-junction device on SOI substrates. The basic element allows an interface quite compatible to that of conventional CMOS circuits and MOS circuits.SOI, gated-pn junction, neural logic, synaptic operationDevicesYasuhisa OmuraManuscript received Novermber 7, 2001; revised March 12, 2002.Dept. of Electronics, Faculty of Engineering, Kansai University, 3-3-35, Yamate-cho, Suita, Osaka 564-8680 Japan(e-mail : omuray@ipcku.kansai-u.ac.jp)Tel : +81 6-6368-0825 Fax : +81 6-6388-88432170812002Particular aspects of drivers for VCSELs operating at multi-Gb/s data ratesIt is demonstrated that the conventional current-pulse laser drivers are not adequate in driving VCSELs operating at multi-Gb/s speeds. Simulation results, including the bonding parasitics, show that high-performance VCSELs are more efficiently driven using voltage-pulse mode of operation. The optical output power is almost doubled in the voltage-mode of operation, while the total electrical power consumption of the transmitter decreases by 20%.Optical interconnections, Laser drivers, Vertical-Cavity Surface-Emitting Lasers (VCSELs)DevicesEfstathios D. Kyriakis-Bitzaros, Stavros G. Katsafouros, and George HalkiasManuscript received February 25, 2002; revised March 12, 2002.Inst. Of Microelectronics, NCSR Demokritos P.O.Box 60228, Athens 153 10, Greece(e-mail :mpitz@imel.demokritos.gr) Tel : +30/1-650-32312182862002A Method for Measurement of Limiting Intrinsic Non-Uniformity Due ot Process in CCD-Multiplexers for Focal Plane ArraysWe present a simple experimental method for determination of limiting intrinsic fixed-pattern non-uniformity (NU) due to fabrication process in two-dimensional CCD multiplexers (MUXs) that are used for hybrid focal plane arrays. Here, this is done by determining separately the two NUs viz. that are VT dependent and VT independent. From these measurements, process dependent NU can be extracted. It is argued that VT dependent NU can be eliminated by designing novel input circuits whereas VT independent NU, primarily, dependent on process control and material variations may be reduced but cannot be eliminated completely and hence limits the FPA performance eventually.Interconnects, Doplanar strip line, Fourier series approach, silicon substrate, point matching procedure.DevicesR. K. Bhan and R. S. SaxenaManuscript received January 2, 2002; revised March 12, 2001.Dr. R. K. Bhan Scientist-E Soild State Physics Laboratory, Lucknow Rod, Delhi-110054.(e-mail : bhan/sspl@ssplnet.org)2187922002Fabrication and Characteristics of Lateral Type Field Emitter ArraysWe have proposed and fabricated two lateral type field emission diodes, poly-Si emitter by utilizing the local oxidation of silicon (LOCOS) and GaN emitter using metal organic chemical vapor deposition (MOCVD) process. The fabricated poly-Si diode exhibited excellent electrical characteristics such as a very low turn-on voltage of 2 V and a high emission current of 300 /tip at the anode-to-cathode voltage of 25 V. These superior field emission characteristics was speculated as a result of strong surface modification inducing a quasi-negative electron affinity and the increase of emitting sites due to local sharp protrusions by an appropriate activation treatment. In respect, two kinds of procedures were proposed for the fabrication of the lateral type GaN emitter: a selective etching method with electron cyclotron resonance-reactive ion etching (ECR-RIE) or a simple selective growth by utilizing Si3N4 film as a masking layer. The fabricated device using the ECR-RIE exhibited electrical characteristics such as a turn-on voltage of 35 V for 7 m gap and an emission current of ~ 580 nA/10tips at anode-to-cathode voltage of 100 V. These new field emission characteristics of GaN tips are believed to be due to a low electron affinity as well as the shorter inter-electrode distance. Compared to lateral type GaN field emission diode using ECR-RIE, re-grown GaN emitters shows sharper shape tips and shorter inter-electrode distance.Field emission, lateral type, LOCOS, Poly-Si emitter, GaN emitter.Fabrication ProcessJae-Hoon Lee, Ki-Rock Kwon, Myoung-Bok Lee, Sung-Ho Hahm, Kyu-Man Choi, and Jung-Hee LeeManuscript received January 2, 2002; revised June 12, 2002.School of Electronic and Electrical Engineering, Kyungpook National University, Daegu, 702-701, Korea.E-mail : jlee@ee.knu.ac.kr Tel : +82-53-950-6555Kyu-Man Choi is with reseach Institute of Electronic and Telecommunication Technologies, Kwandong University, Kangwon, 215-800, Korea.22931012002Fabrication of Micro-inductor and Capacior For RF MEMS ApplicationsIn this paper, we present the fabrication of tunable capacitors and 3-dimensional inductors. This work was related to fabricated 3-dimensionaldevice for need of micro device in developing new intelligence age. This device was fabricated by electroplating used electroplating PR and highvacuum evaporation of metal. Fabricated microinductor is consisted of air-bridge on electroplating rod and electroplated core. Micro-capacitor is consisted of thin metal membrane and electroplated core. Electroplating material is used Cu metal solvent. Air-gap between metal-layers function as almost perfect isolation layer. The most advantage of our micro-inductor and micro-capacitor compared to present device is a possibility that can fabricate on RF MEMS(microelectro-mechanical systems) application with high performance and various function. In this paper, we present the fabrication of tunable capacitors and 3-dimensional inductors. This work was related to fabricated 3-dimensional device for need of micro-device in developing new intelligence age. This device was fabricated by electroplating used electroplating PR and high-vacuum evaporation ofmetal. Fabricated micro-inductor is consisted of airbridge on electroplating rod and electroplated core. Micro-capacitor is consisted of thin metal membrane and electroplated core. Electroplating material is used Cu metal solvent. Air-gap between metal-layers function as almost perfect isolation layer. The most advantage of our micro-inductor and micro-capacitor compared to present device is a possibility that can fabricate on RF MEMS application with high performance and various functions.RF MEMS, Inductor, Capacitor.DevicesBek-Hee Cho, Jae-Ho Lee, Young-Ho Bae, Chan-Sub Cho, and Jong-Hyun LeeManuscript received January 2, 2002; revised June 12, 2002.Young Ho Bae are with School of Electronic Engineering, Uiduk University(e-mail : cbh@palgong.knu.ac.kr)Chan Sub Cho are with School of Electronic and Electrical Engineerig, Sangju National UniversitySchool of Electrical Engineering and Computer Science, Kyungpook National University221021102002FeRAM Technology for System on a ChipThe ferroelectric RAM (FeRAM) has a great advantage for a system on a chip (SOC) and mobile product memory, since FeRAM not only supports non-volatility but also delivers a fast memory access similar to that of DRAM and SRAM. This work develops at three levels: 1) low voltage operation with boost voltage control of bitline and plateline, 2) reducing bitline capacitance with multiple divided sub cell array, and 3) increasing chip performance with write operation sharing both active and precharge time period. The key techniques are implemented on the proposed hierarchy bitline scheme with proposed hybrid-bitline and high voltage boost control. The test chip and simulation results show the performance of sub-1.5 voltage operation with single step pumping voltage and self-boost control in a cell array block of 1024 (64 x 16) rows and 64 columns.Ferroelectric memory, non-volittle memory, micro controller system, boost scheme.DevicesHee-Bok Kang, Dong-Yun Jeong, Jae-Hyoung Lim, Sang-Hyun Oh, Seaung-Suk LeeSuk-Kyoung Hong, Sung-Sik Kim, Young-Jin Park, and Jin-Young ChungManuscript received January 2, 2002; revised June 12 5, 2002.hee-Bok Kang et al. are developing the design and process technologies of FeRAM at the Memory R&D Center in Hynix Semiconductor lnc.Email : kanghb@hynix.com Tel : 82-42-270-4527Fax : 82-43-270-40752211112420026-18 GHz MMIC Drive and Power AmplifiersThis paper presents MMIC drive and power amplifiers covering 6-18 GHz. For simple wideband impedance matching and less sensitivity to fabrication variation, modified distributed topologies are employed in the both amplifiers. Cascade amplifiers with a self-biasing circuit through feedback resistors are used as unit gain blocks in the drive amplifier, resulting in high gain, high stability, and compact chip size. Self impedance matching and high-pass, low-pass impedance matching networks are used in the power amplifier. In measured results, the drive amplifier showed good return losses (S11 , S22 < -10.5 dB), gain flatness (S21= 16 0.6 dB), and P1dB > 22 dBm over 6-18 GHz. The power amplifier showed P1dB > 28.8 dBm and Psat 30.0 dBm with good small signal characteristics (S11 < -10 dB, S22 < -6 dB, and S21= 18.5 1.25 dB) over 6-18 GHz.6-18 GHz MMIC amplifier, wideband amplifier, distributed amplifier.CircuitsHong-Teuk Kim, Moon-Suk Jeon, Ki-Woong Chung, and Youngwoo KwonManuscript received January 2, 2002; revised June 12, 2002.Kim and Kwon are with School of Electrical Engineering, SeoulNational University, Seoul 151-742, Korea(e-mail : htkim@snu.ac.kr, ykwon@snu.ac.kr)Jeon and Chung are with WAVICA Co., Ltd., Telson Venture B/D,943-3, Dogok-dong, Gangnam-gu, Seoul, 135-270, Korea.221251312002SOC Bus Transaction Verification Using AMBA Protocol CheckerThis paper presents an ARM-based SOC bus transaction verification IP and the usage experiences in SOC designs. The verification IP is an AMBA AHB protocol checker, which captures legal AHB transactions in FSM-style signal sequence checking routines. This checker can be considered as a reusable verification IP since it does not change unless the bus protocol changes. Our AHB protocol checker is designed to be scalable to any number of AHB masters and reusable for various AMBA-based SOC designs. The keys to the scalability and the reusability are Object-Oriented Programming (OOP), virtual port, and bind operation. This paper describes how OOP, virtual port, and bind features are used to implement AHB protocol checker. Using the AHB protocol checker, an AHB simulation monitor is constructed. The monitor checks the legal bus arbitration and detects the first cycle of an AHB transaction. Then it calls AHB protocol checker to check the expected AHB signal sequences. We integrate the AHB bus monitor into Verilogsimulation environment to replace time-consuming visual waveform inspection, and it allows us to find design bugs quickly. This paper also discusses AMBA AHB bus transaction coverage metrics and AHB transaction coverage analysis. Test programs for five AHB masters of an SOC, four channel DMAs and a host interface unit are executed and transaction coverage for DMA verification is collected during simulation. These coverage results can be used to determine the weak point of test programs in terms of the number of bus transactions occurred and guide to improvethe quality of the test programs. Also, the coverage results can be used to obtain bus utilization statistics since the bus cycles occupied by each AHB master can be obtained.SOC Verification, AERA, Bus transaction coverage.CircuitsKab Joo Lee, Si Hyun Kim, and Hyo Seon HwangManuscript received January 2, 2002; revised June 12, 2002.Kab Joo Lee is with system LSI Divison Samsung Electronics Co., Ltd. San #24 Nongseo-Ri, Kiheung-Eup, Yongin-City, Kyunggi-Do, South Korea(E-mail: flyingv@samsung.co.kr)221321402002An Investigation of the Effect of Schotky Barrier-Height Enhancement Layer on MSMPD Dynamic CharacteristicsThe effect of the wide-bandgap Schottky barrier enhancement cap layer on the performance of metal-semiconductor-metal photodetectors (MSMPDs) is presented. Judged by the dc characteristics, no considerable increase in recombination loss of carriers is resulted by the incorporation of the cap layer. However, about 45 % of the detection efficiency is lost for the cap-layered MSMPDs even with a graded layer incorporated under pulse operation, and it was found to be due mainly to the capturing and slow release of the photocarriers at the heterointerface. The loss mechanism of the pulse detection efficiency is believed to be responsible for the intersymbol interference and the increased biterror-rate (BER) observed in MSMPDs when used with a high bit rate pseudo-random-bit-stream (PRBS) data pattern.MSMPD, responsivity, Schottky barrier, heterojunction, efficiency.DevicesJong-Wook SeoManuscript received January 2, 2002; revised April 8, 2002.Jong Wook Seo School of Electronic and Electrical Engineering, Hongik University 72-1, Sangsu-dong, Mapo-gu, Seoul 121-791, Korea.(jwseo@wow.hongik.ac.kr)221411462002A RF Frong-End CMOS Transceiver for 2GHz Dual-Band ApplicationsThis paper describes RF front-end transceiver chipset for the dual-mode operation of PCS-Korea and IMT-2000. The transceiver chipset has been implemented in a 0.25m single-poly fivemetal CMOS technology. The receiver IC consists of a LNA and a down-mixer, and the transmitter ICintegrates an up-mixer. Measurements show that the transceiver chipset covers the wide RF range from 1.8GHz for PCS-Korea to 2.1GHz for IMT-2000. The LNA has 2.8~3.1dB NF, 14~13dB gain and 5~4dBm IIP3. The down mixer has 15.5~16.0dB NF, 15~13dB power conversion gain and 2~0dBm IIP3. The up mixer has 0~-2dB power conversion gain and 6~3dBm OIP3. With a single 3.0V power supply, the LNA, down-mixer, and up-mixer consume 6mA, 30mA, and 25mA, respectively.RF CMOS IC, Wireless Front-end, Dual-band Transceiver, PCS, IMT-2000.CircuitsYong-Sik Youn, Nam-Soo Kim, Jae-Hong Chang, Young-Jae Lee, and Hyun-Kyu YuManuscript received February 22, 2002; revised April 30, 2002.Y- S. Youn, N.-S Kim, J. H Chang, and H. K Yu are withElectronics and Telectommunications Research Institute(ETRI), 161 Gajeong-Dong, Yuseong-Gu, Daejeon, 303-350, Korea.(E-mail: ysyoun@etri.re.kr) (E-mail: hkyu@etri.re.kr)Y. J. Lee is with Hynix semiconductor, Hungdoek-gu, Cheongju, 361-725, Korea. (E-mail: youngjae.lee@hynix.com)221471552002A New EEPROM with Side Floating Gates Having Different Work Function from Control GateA new flash EEPROM device with ploy-Si control gate and ploy-Si floating side gate was fabricated and characterized. The ploy-Si gate is formed on both sides of the poly-Si gate, and controls the underneath channel conductivity depending on the number of electron in it. The cell was programmed by hot-carrier-injection at the drain extension, and erased by direct tunneling. The proposed EEPROM cell can be scaled down to 50nm or less. Shown were measured programming and erasing characteristics. The channel resistance with the write operation was increased by at least 3 times.EEPROM, flash memory, MDSFET, hot carrier injection, direct tunneling.DevicesYoungjoon Ahn, Sangyeon Han, Hoon Kim, Jongho Lee, and Hyungcheol ShinManuscript received January 22, 2002; revised August 16 Y. Ahn, S. Han, H. Kim, and H. Shin are with Department of Electrical Engineering and Computer Science, KAIST 373-1 Kusong-dong, Yusong-gu, Taejon, 305-701, KoreaE-mail : nanom@mail.kaist.ac.kr J. Lee is with School of Electrical Engineering Wonkwang University231571632002Aspects of Hard Breakdown Characteristics in a 2.2-nm-thick SiO2 filmThis paper mainly discusses the hard breakdown of 2.2-nm-thick films. It is shown that the hard breakdown event of a 2.2-nm-thich films greatly depends on the applied electric field. It is strongly suggested that the local weak spots created by applying a low initial stress to a 2.2-nm-thick film resist the onset of hard breakdown. In other words, it is anticipated that the stored electrostatic energy is fast dissipated by trap-assisted tunneling in 2.2-nm-thick film. Consequently, it is strongly suggested that 2.2-nm-thick films are intrinsically quite robust.silicon oxide, hard breakdown, stress-induced leakage current, immunutyDevicesKenji Komiya and Yasuhisa OmuraManuscript received August 29, 2002; revised September 23, 2002. High-Technology Research Center and Graduate School of Electronics, Kansai University, 3-3-35, Yamate-cho, Suita 564-8680, Japan E-mail : omuray@ipcku.kansai-a.ac.jp Tel : +81 6-6368-0825231641692002Field Effect Transistor of Vertically Stacked, Self-assembled InAs Quantum Dots with Nonvolatile MemoryThe epilayer of vertically stacked, self-assembled InAs Quantum Dots (QDs)was grown by MBE with solid sources in non-cracking K-cells, and the sample was fabricated to a FET structure using a conventional technology. The device characteristics and performance were studied. At 77K and room temperature, the threshold voltage shift values are 0.75V and 0.35V, which are caused by the trapping and detrapping of electrons in the quantum dots. Discharging and charging curves form the part of a hysteresis loop to exhibit memory function. The electrical injection of confined electrons in QDs products the threshold voltage shift and memory function with persistent electron trapping, which shows the potential use for a room temperature application.Field-effecttransistor, self-assembled quantumdots, Molecularbeamepitaxy, Nonvolatile MemoryDevicesShuwei Li,Kazuto Koike, and Mitsuaki YanoManuscript received June 22, 2002; revised September 11, 2002. Changchun Institute of Optics, Fine Mechanics and Physics. Chinese Academy of Sciences, No.1 Yan-an Road, Changchun 130021, P.R.China E-mail : snmocvd@public.cc.jl. Tel : 0431-5937537, Fax : 0431-5955378 New Materials Research Center, Osaka Institute of Technology, Asahi-ku Ohmiya, Osaka 535-8585, Japan231701722002A Novel Sensing Circuit for 2T-2MTJ MRAM Applicable to High Speed Synchronous OperationWe propose a novel sensing circuit for 2T-2MTJ MRAM that can be used for high speed synchronous operation. Proposed bit-line sense amplifier detects small voltage difference in bit-lines and develops it into rail-to-rail swing while maintaining small voltage difference on TMR cells. It is small enough to fit into each column that the whole data array on selected word line are activated as in DRAMs for high-speed read-out by changing column addresses only. We designed a 256Kb read-only MRAM in a 0.35um logic technology to verify the new sensing scheme. Simulation result shows a 25ns RAS access time and a cycle time shorter than 10ns.MRAM, Sensing, TMR, 2T-2MTJ, page mode, synchronous operation, MR ratioCircuitsEun-Jung Jang, Jung-Hwa Lee, Seungjun Lee ,and Ji-hyun KimManuscript received July 1, 2002; revised September 10, 2002. Department of Information Electornics Engineering Ewha Womans University E-mail : slee@ewha.ac.kr231731792002Ta/TaNx Metal Gate Electrodes for Advanced CMOS DevicesIn this paper, the electrical properties of PVD Ta and TaN, gate electrodes on and their thermal stabilities are investigated. The results show that the work functions of gate electrode are modified by the amount of N, which is controlled by the flow rate of during reactive sputtering process. The theramal stability of Ta and with RTO-grown gate dielectrics is examined by changes in equivalent oxide thickness (EOT), flat-band voltage(), and leakage current after post-metallization anneal at high temperature in ambient. For a Ta gate electrode, the observed decrease in EOT and leakage current is due to the formation of a Ta-incorporated high-K layer during the high temperature annealing. Less charge in EOT and leakage current is observed for gate electrode. It is also shown that the frequency CV curves are improved significantly by a post-metallization anneal.Metal gate electrode, Gate stack engnieering, CMOS Fabrication proess.DevicesS. J. Lee and D. L. KwongManuscript received July 12, 2002; revised September 11, 2002. Micrielectronics Research Center, Department of Electrical and Computer Engineering, The University of Texas, Austin, TX 78712, USA E-mail : sungjoo@aist.go.jp Tel : 81-298-49-1641231801842002MRAM Technology for High Density Memory ApplicationMRAM(magnetic random access memory) is a promising candidate for a universal memory with non-volatile, fast operation speed and low power consumption. The simplest architecture of MRAM cell is a combination of MTJ(magnetic tunnel junction) ad a data storage part and MOS transistor as a data selection part. This article will review the general development status of MRAM and discuss the issues. The key issues of MRAM and discuss the issues. The key issues of MRAM and discuss the issues. The key issues of MRAM technology ad a future memory candidate are resistance control and low current operation for small enough device size. Switching issues are controllable with a choice of appropriate shape and fine patterning process. The control of fabrication is rather important to realize and actual memory device for MRAM technology.MRAM, MTJ, TMR, non-volatile memoryDevicesChang-Shuk Kim, In-Woo Jang, Kye-Nam Lee, Seaung-Suk Lee, Sung-Hyung Park, Gun-Sook Park, Geun Do Ban, and Young-Jin ParkManuscript received August 19, 2002; revised September 25, 2002. Chang-Shuk Kim et al. are developing the process and device technologies of MRAM at the Memory R&D Center in Hynix Semiconductor Inc. E-mail : changshuk.kim@hynix.com Tel : 82-31-630-2811 Fax : 82-31-630-2847231851962002Technology of MRAM(Magneto-resistive Random Access Memory) Using MTJ(Magnetic Tunnel Junction) CellDRAM,SRAM, and FLASH memory are three major memory devices currently used in most electronic applications. But, they have very distinct attributs, therefore, each memory could be used only for limited applications. MRAM(Magneto-resistive Random Access Memory) is a promising candidate for a universal memory that meets all application needs with non-vilatile, fast operational speed, and low power consumption. The simplest architecture of MRAM cell is a series of MTJ (Magnetic Tunnek Junction) as a data storage part and MOS transistor as a data selection part. To be a commercially competitive memory device, scalability is an omportant factor as well. This paper is testing the actual electrical parameters and the scaling factors to limit MRAM technology in the seniconductor based memory device by an actual integration of MRAM core cell. Electrical tuning of MOS/MTJ, and control of resistance are important factors for data sensing, and control of magnetic switching for data writing.MRAM(Magneto-resistive Random Access Memory), GMR(Giant Magneto-resistance), MTJ(Magnetic Tunnel Junction).DevicesWanjun Park, I-Hun Song, Sangjin Park , and Teawan KimManuscript received August 19.2002; revised September 24, 2002. SAMSUNG Advanced Institute of Technology, MD Lab, Nong-Suh Li San 14-1, Ki-Heung Eup, Yong-In Si, Kyung-Gi Do, Korea. E-mail : wanjun@sait.samsung.co.kr Tel : 82-31-280-9394 Fax : 82-31-280-9308231972042002Metal-Organic Chemical Vapor Deposition of Pb(ZrxTi1-x)O3 Thin Films for High-Density Ferroelectric Random Access Memory ApplicationThe growth characteristics of metal-organic chemical vapor deposition (MOCVD) Pb()(PZT) thin films were investigated for the application of high-density ferroelectric random access memories (FRAM) devices beyond 64Mbit density. The supply control of Pb precursor plays the most critical role in order to achieve a reliable process for PZT thin film deposition. We have monitored the changes in the microstructure and electrical properties of films on increasing the Pb precursor supply into the reaction chamber. Under optimized conditions, capacitor shows well-saturated hysteresis loops with a remanent polarization (Pr) of ~28 and coercive voltage of 0.8V at 2.5V. Other issues such as step coverge, compositional uniformity and low temperature deposition was discussed in viewpoint of actual device application.PZT, MOCVD, Ir, FeRAM, ferroelectric, thin film, capacitor, COB, hysteresis loop, liquid deliveryDevicesJune Key Lee, June-Mo Ku, Chung-Rae Cho, Yong Kyun Lee, Sangmin Shin, and Youngsoo ParkManuscript received August 19, 2002; revised September 24, 2002. Materials & Devices Laboratory, Samsung Advanced Institute of Technology, Suwon 440-600, Korea E-mail : jklee@sait.samsung.co.kr232052122002Device Characterization and Fabrication issues for Ferroelectric Gate Field Effect Transistor DeviceMetal-Ferroloctric- Insulator- Silicon(MFIS) structred field effect transistor (FET) device was fabricated and characterized. Important issues to realize ferroelectric gate filed effect transistor device were summarized in three sections.The choice of interlayar dielectric was made in the consideration of device functionality and chemical reaction between ferroelectric materials and silicon surface during fabrication process. Also, various ferroelect thin film materials were taken into account to meet desired memory window and process compatibility. Finally, MFIS structured FET device was fabricated and important characteristics were discussed. For feasible integration of current device as random access memory array cell schemes were also suggested.SBT, sol-gel, FRAM, ferreolectric, thin film, capacitor, gate dielectric, hysteresis loop, TEMDevicesByoung?Gon Yu, In-Kyu You, Won-Jae Lee, Sang-Ouk Ryu, Kwi-Dong Kim, Sung-Min Yoon, Seong-Mok Cho, Nam-Yeal Lee, and Woong-Chul ShinManuscript received August 19, 2002; revised September 24, 2002. Basic Research Lab.,Electronics and Telecommunications Research Institute(ETRI),161 Kajong-dong, Yusong, Daejon 305-600, Korea E-mail : bgyu@etri.re.kr * Current address: Research Center for Electronic Ceramics(RCEC), Deparkment of Advanced Materials Engineering, Dong-Eui University San 24, Gaya-dong, Busanjin-Gu, Busan 614-714, Korea232132252002Virtual ground monitoring for high fault coverage of linear analog circuitsThis paper explains a technique to improve the fault coverage of oscillation-test [1-5] for linear analog circuits. The transient behavior of the virtual ground is monitored during oscillation to extract information of the circuit. The limitation of the oscillation-test is analyzed, and an efficient signature analysis technique is proposed to maximize the fault coverage. The experimental result proves that the parametric fault coverage can be significantly increased by the proposed technique.analog circuits, mixed-signal circuits, built-in self test (BIST), oscillation-test, signature analysisCircuitsJeongjin RohManuscript received August 5, 2002; revised September 16, 2002.Affiliation of authors: Hanyang University, Electrical Engineering and Computer ScienceAddress: 1271 Sa-dong, Ansan, Kyungki-doE-mail: jroh@hanyang.ac.kr Tel: +82 31-400-5168232262322002Optimum Design of the Interdigitated CB StructureSome measures are provided for the optimum design of specific on-resistance Ron and breakdown-voltage VB of interdigitated CB (Composite Buffer) MOSFET, including introducing opposite type impurity into the P region near the N+ contact, separating P region from N region with an oxide film, and a groove in the N region near the P+ contact. The new relationship between the Ron and VB, which proved by numerical device simulation, are more exact and minute than the qualitative results before.interdigitated, Composite Buffer (CB) structure, specific on-resistance, breakdown voltageDevicesYang Hong-qiang and Chen Xing-biManuscript received June 2, 2002; revised September 5, 2002.Authors are with Institute of Micro-Electronics and Solid-Electronics, University of Electronic Science and Technology of China, Chengdu, China, 610054.E-mail: hqyango503@yahoo.com232332362002A New Type of High Bandwidth RF MEMS Switch - Toggle SwitchA new type of RF MEMS switch for low voltage actuation, high broadband application and high power capability is presented. Mechanical andelectromagnetic simulations of this new RF MEMS switch type are shown and the fabrication process and measurement results are given. The switching element consists of a cantilever which is fixed by a suspension spring to the ground of the coplanar line. The closing voltage is 16V. The switches exhibit low insertion loss (22dB@30GHz).N/AMEMSBernd Schauwecker, Karl M. Strohm, Winfried Simon, Jan Mehner, and Johann-Friedrich LuyManuscript received November 16, 2002; revised December 14, 2002.Bernd. Schauwecker, Karl M. Strohm, and Johann-Friedrich Luy are with DaimlerChrysler Research CenterUlm, Wilhelm-Runge-Stae 11, 89081 Ulm, GermanyE-mail : Bernd.Schauwecker@daimlerchrysler.com)Winfried Simon is with IMST GmbH, Carl-Friedrich-Gau-Strae 2,47475 Kamp-Lintfort, GermanyJan Mehner is with FEM-ware GmbH, Hauptstrae 130, 09221Neukirchen, Germany242372452002Piezoelectric PZT Cantilever Array Integrated with Piezoresistor for High Speed Operation and Calibration of Atomic Force MicroscopyTwo kinds of PZT cantilevers integrated with a piezoresistor have been newly designed, fabricated, and characterized for high speed AFM. Infirst cantilever, a piezoresistor is used to sense atomic force acting on tip, while in second cantilever, a piezoresistor is integrated to calibrate hysteresis and creep phenomena of the PZT cantilever. The fabricated PZT cantilevers provide high tip displacement of 0.55m/V and high resonantfrequency of 73 kHz. A new cantilever structure has been designed to prevent electrical coupling between sensor and PZT actuator and the proposed cantilever shows 5 times lower coupling voltage than that of the previous cantilever. The fabricated PZT cantilever shows a crisp scanned image at 1mm/sec, while the conventional piezo-tube scanner shows blurred image even at 180m/sec. The non-linear properties of the PZT actuator are also well calibrated using the piezoresistive sensor for calibration.Atomic force microscopy, PZT cantilever, electrical coupling, high speed, piezoresistor, tipMEMSHyo-Jin Nam, Young-Sik Kim, Seong-Moon Cho, Caroline Sunyong Lee, Jong-Uk Bu, and Jae-Wan HongManuscript received November 8, 2002; revised December 12, 2002.H. J. Nam, Y. S. Kim, S. M. Cho, C. S. Lee, and J. U. Bu are withMicrosystem Group, LG Electronics Institute of Technology, Seoul, KoreaJ. W. Hong is with School of Physics, Seoul National University, Seoul, KoreaEmail : hyojnam@lge.com Tel : 82-2-526-4587Fax : 82-2-3461-3508242462522002A Study on the Passive Microvalve Applicable to Drainage Device for GlaucomaThis paper reports the design, modeling, fabrication and measurement of passive microvalves, which are applicable to glaucoma implants. Theproposed microvalves were designed using fluidic theory. The microvalves consisted of microchannels and chambers. The microchannels had a constant fluidic resistance generating a pressure difference. Six kinds of microvalves were designed using fluidic equations for laminar flow and fabricated to examine the influences of chamber size, channel length and the shape of channel cross section. The pressure difference between the designed microvalve and the fabricated microvalve was measured to be less than 4%.MEMS, Micro fluidics, Glaucoma, Passive, MicrovavleMEMSTae Seok Sim and Yong-Kweon KimManuscript received November 13, 2002; revised December 12, 2002.School of Electrical Engineering and Computer Science, Seoul National University2425325820023D Lithography using X-ray Exposure Devices Integrated with Electrostatic and Electrothermal ActuatorsWe present a novel 3D fabrication method with single X-ray process utilizing an X-ray mask in which a micro-actuator is integrated. An X-rayabsorber is electroplated on the shuttle mass driven by the integrated micro-actuator during deep X-ray exposures. 3D microstructures are revealed by development kinetics and modulated in-depth dose distribution in resist, usually PMMA. Fabrication of X-ray masks with integrated electrothermal xy-stage and electrostatic actuator is presented along with discussions on PMMA development characteristics. Both devices use 20-m-thick overhanging single crystal Si as a structural material and fabricated using deep reactive ion etching of silicon-on-insulator wafer, phosphorous diffusion, gold electroplating, and bulk micromachining process. In electrostatic devices, 10-m-thick gold absorber on 1mm1mm Si shuttle mass is supported by 10-m-wide, 1-mm-long suspension beams and oscillated by comb electrodes during X-ray exposures. In electrothermal devices, gold absorber on 1.42 mm diameter shuttle mass is oscillated in x and y directions sequentially by thermal expansion caused by joule heating of the corresponding bent beam actuators. The fundamental frequency and amplitude of the electrostatic devices are around 3.6 kHz and 20m, respectively, for a dc bias of 100 V and an ac bias of 20 VP-P (peak-peak). Displacements in x and y directions of the electrothermal devices are both around 20 m at 742 mW input power. S-shaped and conical shaped PMMA microstructures are demonstrated through X-ray experiments with the fabricated devices.3D Deep X-ray lithography, electrostatic actuator, LIGA, thermal actuator, xy stage.Fabrication ProcessKwang-Cheol Lee and Seung S. LeeManuscript received November 15, 2002; revised December 12, 2002.K. C. Lee, S. S. Lee are with Department of Mechanical Engineering, Pohang University of Science and TechnologyEmail : kclee@postech.ac.kr Tel : +82-54-279-8210Fax : +82-54-279-5899242592672002The Active Dissolved Wafer Process (ADWP) for Integrating Single Crystal Si MEMS with CMOS CircuitsThis paper presents a fabrication technology for the integration of single crystal Si microstructures with on-chip circuitry. It is a dissolved wafer technique that combines an electrochemical etch-stop for the protection of circuitry withan impurity-based etch-stop for the microstructures,both of which are defined in an n-epi layer on a ptype Si wafer. A CMOS op. amp. has been integrated with p++ Si accelerometers using this process. It has a gain of 68 dB and an output swing within 0.2 V of its power supplies, unaffected by the wafer dissolution. The accelerometers have 3 m thick suspension beams and 15 m thick proof masses. The structural and electrical integrity of the fabricated devices demonstrates the success of the fabrication process. A variety of lead transfer methods are shown, and process details are discussed.N/AFabrication ProcessKarl J. Ma, Yogesh B. Gianchandani, and Khalil NajafiManuscript received November 15, 2002; revised December 12, 2002.Karl J. Ma and Khalil Najafi are with Center for Integrated Sensors and Circuits University of Michigan Ann Arbor, Michigan 48109, USAYogesh B. Gianchandani is with Corresponding author: EECSBldg., 1301 Beal Ave., Univ. of Michigan, Ann Arbor, MI 48109-2122.E-mail: Yogesh@umich.edu Tel: 734 615 6407Fax: 734 763 9324242682772002Fabrication Uncertainty and Noise Issues in High-Precision MEMS Actuators and SensorWe present technical issues involved in the development of actuators and sensors for applications to high-precision Micro Electro Mechanical System (MEMS). The technical issues include fabrication uncertainty and noise disturbance, causing major difficulties for MEMS to achieve highprecision actuation and detection functions. Fornano-precision actuators, we solve the fabrication instability and electrical noise problems using digital actuators coupled with nonlinear mechanical modulators. For the high-precision capacitive sensors, we present a branched finger electrodes using highamplitude anti-phase sensing signals. We also demonstrate the potential applications of the nanoactuators and nanodetectors to high-precision positioning MEMS.MEMS, Actuators, Sensors, Fabrication uncertainty, Noise instability, High-precision MEMS, Digital actuation, Nonlinear modulation, Branched-finger electrodes, high-amplitude signalsMEMSYoung-Ho Cho, Won Chul Lee, and Ki-Ho HanManuscript received November 15, 2002; revised December 12, 2002.Digital Nanolocomotion Center, Korea Advanced Institute of Science and Technology373-1 Guseong-dong, Yuseong-gu, Daejeon 305-701, Republic of KoreaE-mail : dnc@kaist.ac.kr Tel : +82-42-869-8691Fax : +82-42-869-8690242782872002A 32 by 32 Electroplated Metallic Micromirror ArrayThis paper presents the design, fabrication and characterization of a 32 by 32 electroplated micromirror array on a glass, a low cost substrate.Approaches taken in this work for the fabrication of micromachined mirror arrays include a line addressing scheme, a seamless array design for highfill factor, planarization techniques of polymeric interlayers, a high yield methodology for the removal of sacrificial polymeric interlayers, and lowtemperature and chemically safe fabrication techniques. The micromirror is fabricated by aluminum and the size of a single micromirror is 200m 200 m. Static deflection test of the micromirror has been carried out and pull-in voltage of 44 V and releasing voltage of 30V was found.micromirror array, finite element modeling, electrostatic, electroplating, sacrificial layerFabrication ProcessJeong-Bong LeeManuscript received November 16, 2002; revised December 12, 2002.Erik Jonsson School of Engineering and Computer Science, University of Texas at Dallas2601 N. Floyd Rd., Richardson, Texas 70803-0688E-mail: jblee@utdallas.edu Tel : (972) 883-2893242882942002Solenoid Type 3-D Passives(Inductors and Trans formers) For Advanced Mobile Telecommuni-cation SystemsIn this paper, solenoid-type 3-D passives (inductors and transformers) have been designed, fabricated, and characterized by using electroplating techniques, wire bonding techniques, multi-layer thick photoresist, and low temperature processes which are compatible with semiconductor circuitry fabrication. Two different fabrication approaches are performed to develop the solenoid-type 3-D passives and relationship of performance characteristics and geometry is also deeply investigated such as windings, cross-sectional area of core, spacing between windings, and turn ratio. Fully integrated inductor has a quality factor of 31 at 6 GHz, an inductance of 2.7 nH, and a self resonant frequency of 15.8 GHz. Bonded wire inductor has a quality factor of 120, an inductance of 20 nH, and a self resonant frequency of 8 GHz. Integrated transformers with turn ratios of 1:1 and n:1 have the minimum insertion loss of about 0.6 dB and the wide bandwidth of a few GHz.3-D passives, inductors, transformers, mobile telecommunications, coupling, multilayer thick photoresist processes, electroplating, wire bonding, low temperature processesCircuitsJae Y. Park and Jong U. BuManuscript received November 15, 2002; revised December 12, 2002.Microsystem Group LG Electronics Institute of Technology16 Woomyeon-Dong, Seocho-Gu, Seoul, 137-724, KoreaEmail : jpark41@LG-Elite.com Tel : +82-2-526-4550Fax : : +82-2-3461-3508242953012002

2003TitleAbstractKeywordsSubjectAuthorsAffiliationVolNopp_startpp_endYearAnalysis of Electrical Properties of Ti/Pt/Au Schottky Contacts on (n)GaAs Formed by Electron Beam Deposition and RF SputteringThis paper describes a study on the abnormal behavior of the electrical characteristics of the (n)GaAs/Ti/Pt/Au Schottky contacts prepared by the two techniques of electron beam deposition and rf sputtering and after an annealing treatment. The samples were characterized by I-V and C-Vmeasurements carried out over the temperature range of 150 350 K both in the as prepared state and after a 300 C, 30 min. anneal step. The variation of ideality factor with forward bias, the variation of ideality factor and barrier height with temperature and the difference between the capacitance barrier and current barrier show the presence of a thin interfacial oxide layer along with barrier height inhomogenieties at the metal/semiconductor interface. This barrier height inhomogeneity model also explains the lower barrier height for the sputtered samples to be due to the presence of low barrier height patches produced because of high plasma energy. After the annealing step the contacts prepared by electron beam have the highest typical current barrier height of 0.85 eV and capacitance barrier height of 0.86 eV whereas those prepared by sputtering (at the highest power studied) have the lowest typical current barrier height of 0.67 eV and capacitance barrier height of 0.78 eV.Schottky contact, MESFET, Barrier height inhomogeneity, temperature variationFabrication processB K Sehgal, V R Balakrishnan, R Gulati, and S P TewariManuscript received February 13, 2003; revised March 4, 2003.B K Sehgal, V R Balakrishnan and R Gulati are with Solid StatePhysics Laboratory, Lucknow Road, Delhi 110054, IndiaSP Tewari in place of Department of Physics, University of Delhi, Delhi 110007, IndiaE-mail : bk_sehgal/sspl@ssplnet.org311122003Progress in Novel Oxides for Gate Dielectrics and Surface Passivation of GaN/AlGaN Heterostructure Field Effect TransistorsBoth MgO and Sc2O3 are shown to provide low interface state densities (in the 1011 eV-1 cm -2 range) on n-and p-GaN, making them useful for gate dielectrics for metal-oxide semiconductor(MOS) devices and also as surface passivation layers to mitigate current collapse in GaN/AlGaN high electron mobility transistors(HEMTs). Clear evidence of inversion has been demonstrated in gate-controlled MOS p-GaN diodes using both types of oxide. Charg