Xilinx DS629, 3GPP RACH Preambe Detector v1 · 3GPP RACH Preamble Detector v1.0 DS629 August 8,...

IntroductionThe 3GPP RACH Preamble Detector core provides anoptimal solution for implementing RACH detection ina 3GPP uplink. The core includes all of the logicrequired for scramble-code generation, correlation andpreamble detection. The RACH Preamble Detectorcombines an optimal core and a flexible wrapperdesign, allowing custom implementation of detectionalgorithms and easy integration with a DSP or micro-processor.

Features• Device families supported: Virtex™-4, Virtex-5,

Spartan™-3A DSP

• Scalable solution for femto-cells up to macro-cells

• Algorithm Features

- Compact, scalable correlation unit

- Streamed correlation calculations, allowing minimal hardware use for femto and pico applications

- Coherent and non-coherent result generation in parallel with correlation.

- Sorted and filtered PDP results

• Design scales with following parameters to minimize resource utilization, based on:

- Search window size

- Coherent accumulation window size

- Number of antenna

- Oversample rate

- Quantization

• Easy integration to microprocessor/DSP via OCP-compatible interfaces

- Pipelined read of RACH results for improved performance

• For use with Xilinx CORE Generator™ software v9.2i or later

System OverviewFigure 1 shows a typical use of the 3GPP RACHPreamble Detector core. The core is designed to act as aco-processor attached to a microprocessor or DSPacross a system bus. The open core protocol (OCP)interfaces allow easy adaptation to other bus protocols.

During operation, the RACH runs on every antenna onevery slot. The processor can configure the RACH coreover the OCP-compatible bus to determine the size ofthe cell being processed and the nature of the algorithmused to combine the RACH correlation data to form adecision. The antenna data stream can come directlyfrom a radio interface, but could also be streamed viaDMA across the system bus.

At the end of each slot, the RACH core produces apower delay profile (PDP) for each of the possibleRACH preambles. These PDPs can then be read by theDSP. The core also produces an AICH recommendationbased on the PDPs. This recommendation can be usedby the processor, or it can interpret the PDPs to form itsown decision. The PDPs are also required to initializethe searcher (see the 3GPP Searcher v1.0 data sheet,DS628).

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3GPP RACH PreambleDetector v1.0

DS629 August 8, 2007 0 0 Product Specification

Figure Top x-ref 1

Figure 1: Typical Application

AntennaData

DSP Processor

System Bus

3GPP RACHCore

RACHConfigurations

RACHResults

xmp002_01_062007

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© 2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.

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3GPP RACH Preamble Detector v1.0

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Background

RACH Detection

The 3GPP RACH Preamble Detector is used to detect a RACH preamble transmission from userequipment (UE). The RACH transmission from the UE is one of 16 possible preambles, consisting of256 repetitions of one of the Hadamard code sequences listed in Table 1.

Each preamble of 4096 chips long is transmitted from the UE after scrambling, using the scramblingcode assigned to the PRACH channel. The base station (BS) receives the antenna data, where it isdescrambled by the RACH preamble detector and correlated against the preamble sequences.Detection is achieved when a peak is found in the correlation results exceeding a detection threshold.

Figure 2 illustrates a simple radio channel environment. In this environment, the received RACHpreamble is offset by the channel delays associated with each path. The offset is determined by theround trip time from the BS to the UE. Figure 3 shows the effect of path delays on the transmittedpreamble. When a signal appears at the BS, it is delayed relative to the start of the slot by a delay equalto twice the path delay to the UE. In the RACH, the amount of this delay becomes the search window.To correlate for the full RACH preamble, the RACH has to perform a correlation over 4096 samples,beginning at every sample within the search window, and compare the result against the 16 possiblepreamble sequences. The RACH preamble detection is, therefore, performed over a period of the searchwindow + 4096 chips.

Table 1: Hadamard Code

Preamble Signature

Value of n

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

P0(n) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

P1(n) 1 –1 1 –1 1 –1 1 –1 1 –1 1 –1 1 –1 1 –1

P2(n) 1 1 –1 –1 1 1 –1 –1 1 1 –1 –1 1 1 –1 –1

P3(n) 1 –1 –1 1 1 –1 –1 1 1 –1 –1 1 1 –1 –1 1

P4(n) 1 1 1 1 –1 –1 –1 –1 1 1 1 1 –1 –1 –1 –1

P5(n) 1 –1 1 –1 –1 1 –1 1 1 –1 1 –1 –1 1 –1 1

P6(n) 1 1 –1 –1 –1 –1 1 1 1 1 –1 –1 –1 –1 1 1

P7(n) 1 –1 –1 1 –1 1 1 –1 1 –1 –1 1 –1 1 1 –1

P8(n) 1 1 1 1 1 1 1 1 –1 –1 –1 –1 –1 –1 –1 –1

P9(n) 1 –1 1 –1 1 –1 1 –1 –1 1 –1 1 –1 1 –1 1

P10(n) 1 1 –1 –1 1 1 –1 –1 –1 –1 1 1 –1 –1 1 1

P11(n) 1 –1 –1 1 1 –1 –1 1 –1 1 1 –1 –1 1 1 –1

P12(n) 1 1 1 1 –1 –1 –1 –1 –1 –1 –1 –1 1 1 1 1

P13(n) 1 –1 1 –1 –1 1 –1 1 –1 1 –1 1 1 –1 1 –1

P14(n) 1 1 –1 –1 –1 –1 1 1 –1 –1 1 1 1 1 –1 –1

P15(n) 1 –1 –1 1 –1 1 1 –1 –1 1 1 –1 1 –1 –1 1

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According to the 3GPP W-CDMA specification, section 6 of the 3GPP specification TS25.214 V6.11.0Physical Layer Procedures (FDD) (Release 6)), the RACH must respond to a detected preamble with anAICH response. Failure to receive a response causes the UE to increase its transmission power andresend the RACH preamble.

Figure Top x-ref 2

Figure 2: Simple Radio Channel Environment

Figure Top x-ref 3

Figure 3: Transmitted Preamble Delay

BS

UE

Path 1

Path 4

Path 2

Path 3

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Path Delay

Search Window

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Transmitted Sequence at

Chip Rate

Recevied Data at

Sample Rate

1.5 Access Slots = 7680 Chips

1 Access Slot = 5120 Chips

4096 Chips

(4096 + Window) Chips

Path Delay

AICHResponse Time

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The received RACH preamble is generally subjected to multipath delays and has multiple correlationpeaks in the received stream (Figure 4), producing a power delay profile (PDP). The RACH has toidentify each of these individual peaks and pass the power and delay information associated with eachto the Searcher, providing the Searcher with an initial estimate of the channel in which it is trying totrack transmitted data.

System Operation

Overview

The RACH consists of two parts: a RACH core, available through CORE Generator software, and areference design incorporating the RACH core into a post-processing algorithm for the correlationresults produced by the core. The RACH reference design is delivered as VHDL source code along withthe RACH core.

The RACH 's overall structure is illustrated in Figure 5, showing the VHDL source files comprising thereference design, and the RACH core generated by the CORE Generator software.

The RACH core performs the correlations operation on the received antenna data. The core is designedto process these correlations in the most efficient manner possible.

The RACH reference design’s role is to reduce the load on the DSP by filtering and sorting the resultsfrom the core. The reference design is also responsible for calculating the non-coherent and coherentpower in the RACH correlation results. Furthermore, the reference design produces an AICH recom-mendation for the processor to use in determining the next AICH signal to send.

The further role of the RACH reference design is to act as a bridge between the RACH core and the DSP.Therefore, the reference design uses OCP-compatible interfaces for connecting with the system bus.

The user can edit the reference design source code to change the system bus the RACH uses to connectto the DSP. It is also possible to change the AICH decision algorithm and allow the possibility of imple-menting a proprietary selection algorithm.

Figure Top x-ref 4

Figure 4: Simple Radio Channel Power Delay Profile

Delay

Power

Path 1

Path 2 Path 3

Path 4

Window Delay Search Window

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RACH Reference Design

The RACH reference design is supplied as unencrypted VHDL files, allowing the user to implementproprietary versions of the RACH detection algorithm. The supplies, standard reference design takesthe raw correlation results from the RACH core and compares them to a finger threshold to determineif the correlation peak is large enough to be considered as a matching finger. Matching fingers are thensorted on a per preamble basis, along with the offset associated with them.

The sorted fingers are then combined to generate a figure for the total power contained in eachpreamble. This power estimate is then compared to an AICH detection threshold to determine if thepreamble contains enough power to be considered as being a detected preamble. Detected preamblesare then indicated to the DSP. The DSP also has access to the n largest fingers for each preamble via theOCP RACH Result (RR) interface. This access allows the processor to access the size of each finger andits offset. The offset can then be used to set up the searcher.

Figure Top x-ref 5

Figure 5: RACH Inner and Outer Core Structure

rach_3gpp_config_regs.vhd

rach_3gpp_ocp_result_rd.vhd

rach_3gpp_sorter.vhd

rach_3gpp_preamble_sort.vhd

rach_3gpp_non_coh_add.vhd

rach_3gpp_non_coh_ram.vhd

Bypass if c_min_coh_win_len = 256

RACH Preamble Detector Core

RACH Config

Interface

AntennaInterface

RACH Result Interface

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rach_3gpp_aich.vhd

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The VHDL blocks provided for the reference design are listed in Table 2 and shown in Figure 5.

The interface to the RACH reference design is shown in Figure 6. Connection to the reference design isachieved using OCP-compatible interfaces. The reference VHDL can be edited to implement alter-native bus architectures.

When the RACH reference design is generated via CORE Generator software, the parameters whichapply to the reference design are created as a package of constants and are included in the referencedesign. Adjusting the parameters requires the core to be regenerated.

Port Descriptions

The 3GPP RACH Preamble Detector is designed to be used as co-processor to a general purposeprocessor or DSP. OCP-compatible interfaces are used to provide a consistent interface adaptable tomany system bus types (refer to Register and Memory Maps for details on data transferred across theOCP data and address signals).

Table 2: Reference Design Blocks

Block Description

rach_3gpp_ref_v1_0_main.vhd Top-level reference design.

rach_3gpp_sorter.vhd Implements the sorting of all of the results from the RACH core.

rach_3gpp_preamble_sort.vhdPerforms RACH result sorting for each preamble. One instance is used per preamble. This block is instantiated from within rach_3gpp_sorter.vhd.

rach_3gpp_non_coh_add.vhd:

Implements non-coherent accumulation of the coherent sub-windows generated by the RACH core. If the RACH core is selected without non-coherent accumulation enabled, this block is not necessary. This block incorporates the I2 + Q2 calculation.

rach_3gpp_non_coh_ram.vhdRAM required to store the partial non-coherent results during non-coherent accumulation.

rach_3gpp_power_calc.vhd Performs the I2 + Q2 calculation for the power calculation.

rach_3gpp_aich.vhd Implements the AICH recommendation.

rach_3gpp_ocp_result_rd.vhd Decodes the OCP reads of the RACH results.

rach_3gpp_config_regs.vhd Decodes the OCP writes of the RACH configuration registers

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Port Diagrams

Figure 6 shows the top-level interface to the reference design (fields within the OCP port are shown inbrackets).

Port Descriptions and Definitions

Clocks and Reset

Table 3 lists the clock and reset for the 3GPP RACH Preamble Detector core.

Figure Top x-ref 6

Figure 6: 3GPP RACH Preamble Detector Reference Ports

Table 3: Clock and Reset(1)

Port Name I/O Width Description

CLK I 1 Chip Rate Processing Clock. Used to synchronize all OCP-compatible interfaces

CE I 1 Clock Enable (optional). Clock Enable halts all internal clocks when asserted.(2)

RESET I 1 Reset Active High Synchronous Reset.(3)

Notes: 1. Clock and Reset is common to all blocks.2. CE is not defined in OCP specification. Asserting CE during OCP accesses could lead to the block not

complying with OCP specification. 3. OCP reset is specified as being active Low. Active High reset is adopted to be compatible with other LogiCORE

modules. Place an inverter before reset if using OCP reset signal.

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CLK

CE

MRESET

RC_MCMD

RC_MADDR

RC_MDATA

RC_SCMDACCEPT

RC_SINTERRUPT

A_MCMD

A_MDATA

A_MDATAINFO

A_SCMDACCEPT

A_SINTERRUPT

3GPPRACH

PreambleDetector

ReferenceDesign

RR_MCMD

RR_MADDR

RR_SDATA

RR_SDATAINFO

RR_SRESP

RR_SCMDACCEPT

RR_SINTERRUPT

Hos

t Con

figur

atio

nO

CP

Inte

rfac

eA

nten

na In

terf

ace

Host R

esultO

CP

Interface

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RACH Configuration Interface

The core OCP interface port definitions are listed Table 4.

Antenna Data Interface

Table 5 defines the antenna data OCP interface ports for the core.

Table 4: RACH Configuration OCP Interface Ports(1)


RC_MCMD I 3 OCP Master Command. Only supports the following commands:

0xb000: Idle 0xb001: Write

RC_ADDR I 4 OCP Master Address.(2)

RC_MDATA I 32 OCP Master Data.(2)

RC_SCMDACCEPT O 1 OCP Slave Command Accept. Indicates Slave has accept command from master.

RC_SINTERRUPT O 2 OCP Slave Interrupt. Bit 0 indicates that core is ready for another configuration to be written.

Notes: 1. OCP Interface for writing RACH configuration registers.2. See "Antenna Interface Register Map" on page 15.

Table 5: Antenna Data OCP Interface Ports(1)


A_MCMD I 1 OCP Master Command. Only supports the following commands:

0xb000: Idle0xb001: Write

A_MDATA I 16 Antenna Data. Consists of I/Q data components.(2)

A_MDATAINFO I 1 OCP Master Data Info. Bit 0 is set when sample data is synchronized to global sync signal. Only set for data on antenna 0.

A_SCMDACCEPT O 1 OCP Slave Command Accept. Indicates Slave has accept command from master.

A_SINTERRUPT O 1 OCP Slave Interrupt. Indicates that slave is expecting sample synchronized to global sync signal. Cleared when data written with A_MDATAINFO[0] is set.

Notes: 1. Antenna data is time-interleaved on the interface.2. See "Antenna Interface Register Map" on page 15.

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RACH Results Interface

Table 6 defines the RACH results OCP interface ports.

RACH Core

Internal to the RACH Preamble Detector is the RACH core. The RACH is a CORE Generator coreimplementing the scrambling-code generation, correlation, and preamble detection. This core is config-urable using a subset of the parameters listed in Generation and Customization. Variation of theparameters controls the size of the search window that the core is designed to process and the numberof sub-windows which the correlation can be broken down into, allowing for non-coherent accumu-lation across the window (see Coherent and Non-Coherent Processing for details on non-coherentprocessing). Changes to this core can only be achieved by adjusting the parameters in the COREGenerator GUI.

The architecture of this core is based on a fully streamed correlation of the incoming antenna data. Thisarchitecture is ideally suited to femto- and pico-cell RACH implementations, as it minimizes theamount of hardware resources required to perform the RACH detection.

Preamble detection is achieved using a fully streamed fast-Hadamard transform (FHT). The FHT is theoptimal method of decoding the RACH correlation into the original RACH preambles. To enablenon-coherent accumulation, the FHT can access the correlation results throughout the correlationwindow. Thus, a set of preamble results can be produced for a sub-window. These correlation resultscan be accumulated externally to the core to produce a non-coherent accumulation. This non-coherentaccumulation takes place within the reference design.

The RACH core is based on an implementation for a single antenna with an oversample rate of twosamples per chip. This combination provides the optimal use of hardware within the core. To achievehigher oversample rates and additional antennas, multiple instances of the RACH core are instantiated

Table 6: RACH Results OCP Interface Ports


RR_MCMD I 3 OCP Master Command. Valid commands are:

0b000: Idle0b010: Read

RR_MADDR I 23 OCP Master Address.(1)

RR_SDATA O 18 OCP Data.(1)

RR_SDATAINFO O 1 OCP Data Information. Bit 0 indicates that saturation has occurred.

RR_SRESP O 2 OCP Slave Response. Valid values are:

0b00: null response 0b01: data valid response

RR_SCMDACCEPT O 1 OCP Command Accept.

RR_SINTERRUPT O 1 OCP Slave Interrupt. Indicates Completion of a RACH search and results can be read from results memory. Cleared by reading memory.

Note:1. See "RACH Results Memory Map" on page 15.

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inside the RACH reference design. Using separate instances per antenna enables the user to alter thealgorithm used to combine the antenna results to form a RACH detection decision.

Coherent and Non-Coherent Processing

There are two modes of correlation:

• Coherent. For coherent processing, all of the repetitions of the preamble are added across the full 4096 bits prior to decoding with the FHT and calculating the magnitude. Coherent processing is the simplest method to implement since the partial result just accumulates until all the bits are seen.

• Non-coherent: For non-coherent processing, the 4096-bit preamble is split into equally sized windows (size selected by the DSP). Each of these windows is coherently summed, and the magnitude of the results taken. These magnitudes are then summed to produce the final power density spectrum. This method uses the same hardware as coherent detection. However, after each coherence window is completed, the partial result stored is reset, and the FHT is applied to the correlation results in that window. The magnitudes of each preamble produced at the end of the window is stored and accumulated in RAM following the FHT. After all the windows are correlated, the threshold is compared against the non-coherent results stored in the RAM.

Port Descriptions

The RACH core produced by CORE Generator software has the interface shown in Figure 7.Knowledge of the interface is only required if the user is intending to edit the outer reference design. Ifthe standard RACH detection algorithm is used, the interface to this core is made via that referencewrapper.

Core Port Diagram

Figure Top x-ref 7

Figure 7: 3GPP RACH Preamble Detector Core Ports Diagram

scramble_code_init

coherence_win_len

CLK

antenna_data_I

sample_write

antenna_data_Q

sample_accept

fht_data_out_q

fht_data_out_i

fht_data_out_valid

fht_data_out_sync

last_fht_running

MRESET

CE

slot_sync

3GPP RACH Preamble

DetectorCore

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Result Interface

Returns the correlation resultsfrom the RACH

Configuration Interface

Config values driven byregisters in the reference design

Antenna Interface

I/Q Data Suppliedfrom the Antenna

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Core Port Names and Descriptions

Table 7: Core Port Names and Descriptions


CLK I 1 Chip Rate Processing Clock. Same as Reference Design Clock.

CE I 1Clock Enable (optional). Clock Enable halts all internal clocks when asserted.(2)

Sclr I 1 Reset Active High Synchronous Reset.(3)

Scramble_code_init I 25Scramble Code initialization: Connects to the register in the reference design configuration interface to pass the scramble code initialization to the RACH core.

Coherence_win_len I 9

Coherence Window Length: Connects to the Coherence Window Length register in the RACH reference design to pass the dynamically selected coherent window length to the RACH core. The value passed to the core is 1/16th of the value in the reference register.

Sample_write I 1Sample Write Strobe: Indicates new antenna data samples. Equivalent to A_mcmd in the reference design.

Antenna_data_q I 4-8Antenna Data input: Antenna sample for Q-channel. Extracted from Antenna OCP interface in the reference interface.

Antenna_data_i I 4-8Antenna Data input: Antenna sample for I-channel. Extracted from Antenna OCP interface in the reference interface.

Slot_sync I 1Slot Synchronization: Indicates the start of a RACH slot and initiates RACH processing.

Sample_accept O 1Sample Accept: Acknowledgement of antenna sample. Used to generate the A_SCMDACCEPT signal in the reference design’s OCP interface.

Fht_data_out_valid O 1FHT Data Valid: Indicates that the RACH core is outputting a valid PDP. The RACH core produces an unfiltered PDP.

Fht_data_out_sync O 1FHT Data Sync: Indicates that the RACH core is outputting the first preamble result of a PDP.

Fht_data_out_q O 16-20FHT Data Q: The Q-channel output of the RACH core. I2 + Q2 combination of the PDP is performed in the RACH reference design.

Fht_data_out_i O 16-20FHT Data I: The I-channel output of the RACH core. I2 + Q2 combination of the PDP is performed in the RACH reference design.

Last_fht_running O 1

Last PDP Output: Indicates that the PDP being output is the final one for the current search window. Used by the reference design during non-coherent processing to complete non-coherent processing.

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Generation and CustomizationThe 3GPP RACH Preamble Detector can be generated and parameterized through the customizeoption in the CORE Generator software.

XCO Parameters

Table 8: XCO Parameters

XCO Parameter Values Description

Clock_Enable true, falsetrue = component has CE pinfalse = component does not have CE pin

Oversample_Rate 1, 2, 4Number of samples per chip in antenna data stream. The number of samples per chip times the search window size is restricted to a maximum of 1024.

Antennae 1 ...16Number of Antennae. Must be smaller or equal to number of clocks per sample, for example, Clock_Rate divided by Oversample_Rate.

Quantization 4 … 8 Number of bits used to represent samples.

Maximum_Search_Window_Size

1-512Sets the maximum number of chips over which a RACH search can be performed. Effectively sets the operating radius for the cell. Targeted at pico and femto applications.

Clock_Rate 32 … 128 Number of clock cycles available to process one chip.

Minimum_Coherent_Window_Size

32, 64, 128, 256, 512, 1024, 2048,

4096

Sets the number of chips involved in the coherent portion of a non-coherent summation. Selecting 4096 chips generates a fully coherent correlator.

Number_of_Results_Per_Preamble

1-32Selects the number of sorted peaks which are available at the results interface for the DSP.

Power_Shift0-18

Determines the output power scaling of the RACH PDP fingers.

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Register and Memory Maps

RACH Configuration Interface Map

The RACH core is controlled by a configuration interface. The RC_MADDR input is used to access theconfiguration registers via the OCP-compatible interface. The interface register map is defined inTable 9.

r

Table 9: RACH Configuration Register Map

Address Description

0x00RACH Search Window Length Register. Defines the dynamic length of the search window used in the RACH.

0x04RACH Coherence Window Length Register. Defines the Length the coherent window uses in non-coherent operation.

0x08RACH Scrambling Code Register. Configures scrambling code used in the RACH receiver.

0x0CRACH Preamble Mask Register. Register to mask out certain Preamble results from the AICH recommendation.

0x10AICH Threshold Register. Configures Threshold which must be passed to qualify for recommendation for an AICH.

0x14Finger Threshold Register. Configures Threshold which must be passed to count as a finger, and hence contribute to the AICH.

Table 10: RACH Window Length Register (RC_MADDR = 0x00)

Range Field Description

31:10 RSVD Reserved. Set to 0.

9:0 SEARCH_WIN

Search Window Length. This field dynamically controls the number of chips the RACH search is performed over and is restricted to between 1 and the Maximum_Search_Window_Size XCO parameter.

Table 11: RACH Coherence Window Length Register (RC_MADDR = 0x04)



12:0 COH_WIN

Coherence Window Length. This field dynamically controls the number of chips combined in the coherent portion of a non-coherent search. Valid values are 32, 64, 128, 256, 512, 1024, 2048, 4096. This value must be greater than the minimum defined in the Minimum_Coherent_Window_Size XCO parameter. 4096 indicates a fully coherent operation.

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Table 12: RACH Scrambling Code Register (RC_MADDR = 0x08)



24:0 SCRAM_CODEScrambling Code. Defines the 25-bit scrambling code initialization value used to generate the de-scrambling code internally.

Table 13: RACH Preamble Mask Register (RC_MADDR = 0x0C)

range field Description


15:0 PRMBL_MSKPreamble Mask. 15-bit register defining valid preambles in the sector. Only enabled preambles are considered for AICH recommendation.

Table 14: RACH AICH Threshold Register (RC_ADDR = 0x10)



15:0 AICH_THRSH

AICH Threshold. Defines the power which a RACH PDP must contain in order to be considered for an AICH recommendation. The total power is the sum of all the fingers in the PDP. If the PDP is larger than this threshold, the preamble is marked as detected.

Table 15: RACH Finger Threshold Register (RC_ADDR = 0x14)

range Field Description


15:0 FNGR_THRSH

FNGR Threshold. Defines the power which a finger must have to be included in the RACH PDP. Only fingers exceeding this threshold are included in the total power calculation to determine AICH.

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Antenna Interface Register Map

RACH Results Memory Map

The fingers comprising the RACH PDPs generated by the core are filtered and sorted in the referencedesign. The set of largest fingers are stored in the RACH result memory, where the number of fingers ineach set is determined by the XCO parameter, Number_of_Results_Per_Preamble. This memory can beaccessed via the RACH result interface, giving the processor access to the data used in forming theAICH recommendation.

Table 16: Antenna Data (A_MDATA[15:0])


15 8 QDATAQ Component of Sample(1). Valid values are –2Quantization to +2Quantization-1–1.

7 0 IDATAI Component of Sample(1). Valid values are –2Quantization to +2Quantization-1–1.

Note:1. I and Q antenna data is written in parallel to the RACH.

Table 17: RACH Results Address: RR_MADDR[10:0](1)

Range Field Width Description

10 7 PREAMBLE 4RACH Preamble Identifier. Specifies which of the 16 Preambles the results are being requested for.

6 2 DLY 10

RACH Finger Identifier. Specifies which Preamble finger is being requested. Fingers are sorted in descending order, with the largest finger appearing at address 0x00.

1 0WORD

ALLIGNMENT2 OCP Word Alignment. Bits set to 0.

Note:1. Address space is configured for the maximum number of fingers per preamble. Unused bits for smaller designs

should be set to 0.

Table 18: RACH Results Data: RR_MDATA[25:0](1)

Range Field Width Description

25 10 POWER 16Power of Result Finger. Maximum value is determined by the power-shift XCO parameter, which also determines saturation value for power calculation.

9 0 DLY 10Delay Offset of Result. Maximum value is Maximum_Search_Window_Size × Oversample_Rate –1 up to a maximum of 1023.

Notes: 1. Returns power and delay for each finger in a given PDP.

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Timing DiagramsThe 3GPP RACH Preamble Detector uses OCP-v2.0-compatible interfaces for each of the main inter-faces, allowing the interfaces to be easily adapted to a variety of bus protocols.

RACH Reference Timing

The Reference design has three OCP-compatible ports. The timing diagrams for these ports are shownin Figure 8 through Figure 14.

RACH Configuration Interface Timing

The RACH configuration interface is a write-only, OCP-compatible interface used to write to the RACHcontrol registers. These registers can be updated at any time. However, the change only takes effect atthe start of the next slot on antenna 0. The registers are written with configuration data as specified inthe register map (see "RACH Configuration Interface Map" on page 13).

Figure 8 shows the timing when updating a control register value in the RACH.

Antenna Interface Timing

The antenna interface is a write-only, OCP-compatible interface. Data is written as a block starting withthe smallest number antenna, repeating every sample period (Figure 9). The signal A_SCMDACCEPTindicates when antenna data is expected.

The timing is dependent on a number of the core parameters. The number of antennas specifies thelength of the burst transferred. The sample period is determined by the core's clock rate divided by theoversample rate. In this example (Figure 9), the number of antennas is 4, the clock rate is 20, and theoversample rate is 2, giving a sample period of 10 clock cycles.

Figure Top x-ref 8

Figure 8: RACH Configuration Timing

Figure Top x-ref 9

Figure 9: Antenna Interface Basic Transfer

IDLE WR WR WR WR WR WR WR WR IDLEIDLE IDLE

0X00 0X04 0X08 0X0C 0X00 0X04 0X08 0X0C

CLK

RC_MCMD

RC_MADDR

RC_MDATA

RC_SCMDACCEPTds629_07_062607

IDLE WR WR WR WR WR WR WR WR IDLEIDLE

A0 A1 A2 A3 A0 A1 A2 A3

Sample Period

CLK

A_MCMD

A_MDATA

A_SCMDACCEPTds629_08_062607

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The signal A_SCMDACCEPT forces master data transfers to synchronize to the internal processing rate ofthe RACH (Figure 10). If the master writes data to the core early, then A_SCMDACCEPT is not asserteduntil the cycle count reaches the correct value, thus throttling the master data transfer rate.

Figure Top x-ref 11

Figure 10 illustrates the case of the master throttling the core processing rate. In this case, the masterdoes not supply data on the expected clock cycle and the core is stalled. Because processing in the coreis stalled, additional clock cycles are required to meet the real-time processing requirement of the core.

Figure 11 shows the synchronization of the core to the 3GPP framing references. The signalA_MDATAINFO is asserted when writing the first sample of antenna 0 when the frame sync occurs. Thesignal A_SINTERRUPT indicates that the core is expecting the frame synchronization on A_MDATAINFOand occurs at the same time the core is synchronized.

Figure Top x-ref 10

Figure 10: Core Throttling Master Transfer Rate

Figure Top x-ref 12

Figure 11: Antenna Data Frame Synchronization

IDLE WR WRWRWR IDLE

A0 A1 A2 A3

CLK

A_MCMD

A_MDATA

A_SCMDACCEPT

ds629_09_062607

IDLE WR WR WR WR IDLE

A0 A1 A2 A3 A0 A1 A2 A3

WR WR WR WR IDLEA_MCMD

A_MDATA

A_SCMDACCEPT

A_MDATAINFO

A_SINTERRUPTds629_10_062607

CLK

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RACH Results Interface Timing

The RACH results interface is a pipelined read-only, OCP-compatible interface. The signalRR_SINTERRUPT is used to indicate when a RCH detection completes and the results can be read. Thefirst read from the memory clears the interrupt.

The results are read for each PDP using the address specified in the memory map (see "RACH ResultsMemory Map" on page 15). After issuing an OCP read command, there is a three-clock latency fromRR_SCMDACCEPT being asserted to the data valid as indicated via the signal RR_SRESP. See Figure 12.

RACH Core Timing

Antenna Interface Timing

The RACH core has two interfaces that the reference design wraps around. Knowledge of these inter-faces is required when altering the RACH reference design to ensure correct data transfer data to thecore.

Each RACH core is responsible for processing a single antenna’s worth of data. The interface to the coreis similar to the interface for the RACH reference antenna, except that the antenna data is no longer ablock of time-multiplexed antenna data, but rather the demultiplexed data for a single antenna.Furthermore, the write instruction has been reduced to a single bit write flag (Figure 13).

Figure Top x-ref 13

Figure 12: RACH Results Timing

IDLE RD RD RD RD IDLE

A3A2A1A0

D0 D1 D2 D3

VALIDVALIDVALIDVALIDNULL NULLNULL

3 Clock Latency

CLK

RR_SINTERRUPT

RR_MCMD

RR_MADDR

RR_SCMDACCEPT

RR_SRESP

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Figure Top x-ref 15

RACH Results Interface Timing

The RACH core produces a correlation result for each of the 16 possible preambles, for every sample inthe search window, and for both I and Q data channels. This data is streamed out of the RACH(Figure 14) with results appearing for preamble 0 through preamble 15 in a burst of 16 clock cycles. Theblocks of preamble data follow the order: P0, P1, P2 ... Pn, where P0 is the RACH search result startingat sample 0, and where Pn consists of the In result and Qn result.

Figure Top x-ref 14

Figure 13: RACH Core Basic Antenna Data Transfer

Figure Top x-ref 16

Figure 14: RACH Core Results Interface

Sample Period

CLK

SAMPLE_WRITE

ANTENNA_DATA_Q

ANTENNA_DATA_I

SLOT_SYNC

SAMPLE_ACCEPT

ds629_12_062607

P0 P1 P15 P0 P1 P15 P0 P1 P15

CLK

FHT_DATA_OUT

FHT_DATA_OUT_VALID

FHT_DATA_OUT_SYNC

FINAL_FHT_OUTds629_13_062607

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Performance CharacteristicsTable 19 through Table 21 show the performance of the 3GPP RACH Preamble Detector core in terms ofresource usage and maximum achieved operating frequency for different device families. The resourcecount and speed of the core can change depending on the surrounding circuitry of the user design.Therefore, these figures should be taken only as a guide.

The tool settings to achieve these results were as follows and were obtained with ISE™ v9.2i tools:

map -c 1 -ol high

par -ol high

Note: Tool settings can have a significant effect on area use and speed. The Xilinx Xplorer script can be used to find the optimal settings.

Table 19: Spartan3A-DSP Engine Resource Utilization

XCO Parameter Case 1 – Femto Cell Case 2 – Pico Cell

Clock_Enable False False

Minimum_Coherent_Window_Size 4096 512

Maximum_Search_Window_Size 16 128

Quantization 4 4

Utilization

Xilinx device XC3SD3400A XC3SD3400A

Slices(1) 663 1193

LUTs 881 1376

FFs 772 1742

Block RAMs (18k) 1 8

DSP blocks 0 0

Maximum clock frequency(2) 155 145

Notes: 1. Area and maximum clock frequencies are provided as a guide and can vary with new releases of the Xilinx

implementation tools. 2. Maximum clock frequencies are shown in MHz for -4 parts. Clock frequency does not take jitter into account

and should be de-rated by an amount appropriate to the clock source jitter specification.

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Table 20: Virtex-4 Engine Resource Utilization





Quantization 4 4

Utilization

Xilinx device XC4VLX15 XC4VLX15

Slices(1) 417 588

LUTs 507 740

FFs 608 873


DSP blocks 0 0

Maximum clock frequency(2) 283/310 266/310

Notes: 1. Area and maximum clock frequencies are provided as a guide and can vary with new releases of the Xilinx

implementation tools. 2. Maximum clock frequencies are shown in MHz for -10/-12 parts. Clock frequency does not take jitter into

account and should be de-rated by an amount appropriate to the clock source jitter specification.

Table 21: Virtex-5 SP Engine Resource Utilization





Quantization 4 4

Utilization

Xilinx device XC5VLX30 XC5VLX30

LUT/FF Pairs(1) 796 1128

LUTs 532 726

FFs 610 871

Total Block RAMs(3)



DSP blocks 0 0

Maximum clock frequency(1,2) 297/310 251/320

Notes: 1. Area and maximum clock frequencies are provided as a guide. They may vary with new releases of the Xilinx

implementation tools.2. Maximum clock frequencies are shown in MHz for -1/-3 parts. Clock frequency does not take jitter into account

and should be derated by an amount appropriate to the clock-source jitter specification.3. Represents the total number of 36k block RAMs used when map is run. In reality, two 18k block RAM primitives

can usually be packed together, giving an absolute minimum total block RAM usage of block RAMs (36k) + (block RAMs (18k) /2) (rounded up).

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Support Xilinx provides technical support for this LogiCORE product when used as described in the productdocumentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented indevices that are not defined in the documentation, if customized beyond that allowed in the productdocumentation, or if changes are made to any section of the design labeled DO NOT MODIFY.

Ordering InformationThe 3GPP RACH Preamble Detector core is provided under the SignOnce IP Site License and can begenerated using the Xilinx CORE Generator software v9.2i or higher. The CORE Generator software isshipped with Xilinx ISE™ Foundation™ Series Development software.After purchase, the core may be downloaded from the Xilinx IP Center for use with the Xilinx COREGenerator software v9.2i and higher. The Xilinx CORE Generator software is bundled with the ISEFoundation software at no additional charge.

Contact your local Xilinx sales representative for pricing and availability of additional XilinxLogiCORE™ modules and software. Information about additional Xilinx LogiCORE modules isavailable on the Xilinx IP Center.

Revision History

Date Version Revision

08/08/07 1.1 Initial Xilinx release

Discontinued IP


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