X-Architecture Placement Based on Effective Wire Models

Tung-Chieh Chen, Yi-Lin Chuang, and Yao-Wen Chang

Graduate Institute of Electronics EngineeringDepartment of Electrical Engineering

National Taiwan UniversityTaipei, TaiwanMarch 20, 2007

2

Outline

․ Introduction

․ Previous works

․ New wire model – XHPWL

․ Applications Min-cut partitioning placement Analytical placement

․ Conclusion

3

Wiring Dominates Nanometer Design

․ As integrated circuit geometries keep shrinking, interconnect delay has become the dominant factor in determining circuit performance.

Source: Cadence Design System

For 90 nm technology, interconnect

delay will account for75% of the overall delay.

4

Solutions

․ Timing optimization techniques Wire sizing Buffer insertion Gate sizing

․ New IC technologies Copper and low-k dielectrics X-architecture

The The X-architectureX-architecture is a new interconnect is a new interconnect architecture based on the pervasive use of architecture based on the pervasive use of diagonal diagonal routingrouting in chips, and it can shorten interconnect in chips, and it can shorten interconnect length and thus circuit delay. length and thus circuit delay.

X-architecture Manhattan-architecture

L2

L

L

5

Manufacturing the X Architecture

․ X-initiative was created to advance the usage of the X Architecture

by ensuring support for the X Architecture throughout the design and manufacturing cycle.

․ Impacts on EDA tools: Placement and Routing Extraction

6

Placement and Routing for X Architecture

․ Placement Simulated annealing

Chen et al., “Estimation of wirelength reduction forλ-geometry vs. Manhattan placement and routing” (SLIP-2003)

Over-simplified: all cells are of unit size Partitioning placement

Ono, Tilak, and Madden, “Bisection based placement for the X architecture” (ASP-DAC-2007)

X-cutlines does not lead to shorter wirelength

․ Routing Multilevel routing system

Ho et al., “Multilevel full-chip routing for the X-based architecture” (DAC-2005)

Global routing Cao et al., “DraXRouter: global routing in X-architecture with

dynamic resource assignment” (ASP-DAC-2006)

7

․ Teig and Ganley, US Patent 6,848,091

․ Ono, Talik, and Madden, ASP-DAC-2007 Study showed X-cutlines cannot reduce the X wirelength

Partitioning Placement

(a) Manhattan cutlines (b) X cutlines

Shortest X-wirelength

8

Our Contributions

․ Propose a new X-half-perimeter wirelength (XHPWL) model

․ Develop effective x-architecture placers Min-cut partitioning placement

Using generalized net-weighting method Analytical placement

Smoothing XHPWL by log-sum-exp functions

․ Achieve shorter X-routing wirelength than the Manhattan HPWL model for both min-cut partitioning placement and analytical placement.

9

Outline

․ Introduction

․ Previous works

․ New wire model – XHPWL

․ Applications Min-cut partitioning placement Analytical placement

․ Conclusion

10

A

B

Manhattan Bounding Box

D

C

A

B

C

X Bounding Box

D

Half-Perimeter Wirelength (HPWL)

․ Half of the bounding box perimeter length

․ “X bounding box (XBB)” The minimum region enclosing all net terminals bounded by 0,

45, 90, 135 degree lines

XHPWL = ½ XBB perimeter length

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(a) Compute the Manhattan Bounding Box

(b) Remove the Dotted Line Segments

Computing X-Half-Perimeter Wirelength (XHPWL)

(c) Add the Oblique Line Segments

+

–

12

Obtain the Resulting X Bounding Box

The XHPWL Function

XHPWL(e)

We can apply this new model to both min-cut partitioning and analytical placement algorithms.

13

Outline

․ Introduction

․ Previous works

․ New wire model – XHPWL

․ Applications Min-cut partitioning placement Analytical placement

․ Conclusion

14

․ Consider a region to be divided into two subregions.

․ Find the partitioned results with the minimum wirelength Cells are put at the center of the subregion

․ Partition recursively to obtain positions for all cells

Partitioning Placement Problem

c2c1 c2c1

Minimize wirelength(Minimize interconnectBetween subregions)

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Min-Cut Partitioning

․ Do not change cutlines

․ Use net-weighting during min-cut to map partitioning objective to the desired wirelength objective

Selvakkumaran and Karypis proposed to use net-weighting Technical Report, Dept CSE, UMinnesota, 2004

Chen and Chang proposed a compact form to minimize MHPWL ICCAD-2005

Roy and Markov minimizes Manhattan Steiner wirelength ISPD-2006

16

․ Consider a net {v1, v2, …, vm, t1, t2, …, tn} vi: pin in a movable cell

ti: fixed pin

․ c1 (c2) is the center of the subregion 1 (2)

․ Find the following three wirelength values w1 = wirelength( {c1, t1, t2, …, tn} )

w2 = wirelength( {c2, t1, t2, …, tn} )

w12 = wirelength( {c1, c2, t1, t2, …, tn} )

Generalized Net-Weighting

All cells are at the left subregion.wirelength( {c1, t1} ) = w1.

(a)

t1

c2c1

All cells are at the right subregion.wirelength( {c2, t1} ) = w2.

(b)c2c1

t1

Cells are at the both subregions. wirelength( {c1, c2, t1} ) = w12.

(c) c2c1

t1

Region center Fixed terminal Movable cell

The desired wire function

wirelength( )

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Partitioning Graph and Edge Weights

․ Create hypergraph G Two fixed pseudo nodes to present the two subregions Movable nodes to present movable cells

․ Introduce 1 or 2 hyperedges for a net e1: connecting all movable nodes and the fixed pseudo node

corresponding to the subregion that results in a smaller wirelength

e2: connecting all movable nodes

e1 e2

c1 c2

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Relation between Cut-Size and Wirelength

ncut = 0

(d)

e1 e2

ncut = weight(e1) = |w2 – w1| = w2 – w1

(e)e2

e1

ncut = weight(e1) + weight(e2) = |w2 – w1| + (w12 – max(w1, w2)) = w12 – min(w1, w2) = w12 – w1

(f)

e1

e2

Movable nodeFixed pseudo nodePartition

․ Theorem: wirelength = min( w1, w2 ) + ncutsize

All cells are at the left subregion.wirelength( {c1, t1} ) = w1.

(a)

t1

c2c1

All cells are at the right subregion.wirelength( {c2, t1} ) = w2.

(b)c2c1

t1

Cells are at the both subregions. wirelength( {c1, c2, t1} ) = w12.

(c) c2c1

t1

w1 = w1 + 0 w2 = w1 + (w2 – w1) w12 = w1 + (w12 – w1)

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Min-Cut Placement Flow

Create the partitioning graph

Select a bin to be partitioned

Find a min-cut bisection result

Add large sub-partitions into the bin list

Non-empty bin list

Assign net-weights usinggeneralized net-weighting

20

Experiments on Min-Cut Partitioning

․ Platform: AMD Opteron 2.6GHz

․ Min-cut partitioning placer: NTUplace1 (ISPD-2005)

․ Benchmarks: IBM version 2.0 (8 circuits)

․ Three different models (for calculating w1, w2, w12) MHPWL (Manhattan-half-perimeter wirelength) XHPWL (X-half-perimeter wirelength) XStWL (X Steiner wirelength)

․ Use total X Steiner wirelength to evaluate the resulting placement

21

Resulting Wirelengths and CPU times

․ XHPWL: 1% shorter wirelength, 8% CPU penalty

․ XStWL: 5% shorter wirelength, 22% CPU penalty

Min-Cut Partitioning

Total X-Steiner Wirelength (x e8)

CPU Time (sec)

Wire model MHPWL XHPWL XStWL MHPWL XHPWL XStWL

ibm01 0.57 0.57 0.55 33 36 41

ibm02 1.68 1.68 1.60 65 81 98

ibm07 3.56 3.56 3.42 200 206 244

ibm08 3.98 3.98 3.81 239 254 299

ibm09 3.28 3.28 3.12 209 213 227

ibm10 6.24 6.24 5.97 380 382 406

ibm11 4.71 4.71 4.52 304 321 347

ibm12 8.25 8.25 7.98 366 402 452

Average 1.00 0.99 0.95 1.00 1.08 1.22

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X Steiner Wirelength Reductions

․ XHPWL reduces up to about 2% wirelength

․ XStWL reduces up to about 6% wirelength

0.90

0.92

0.94

0.96

0.98

1.00

ibm01 ibm02 ibm07 ibm08 ibm09 ibm10 ibm11 ibm12

Partitioning (MHPWL) Partitioning (XHPWL) Partitioning (XStWL)

0.00

23

Outline

․ Introduction

․ Previous works

․ New wire model – XHPWL

․ Applications Min-cut partitioning placement Analytical placement

․ Conclusion

24

Analytical Placement

․ Minimize W(x) + O(x) Wire forces: dW(x) / dx Spreading forces: dO(x) / dx

Wire forcesMinimize wirelengths

Spreading forcesMinimize overlaps

W(x) wirelength functionO(x) overlap function

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․ Pins on the boundary receive forces to reduce the bounding box size.

A

B

C

Wirelength Forces and the Manhattan Bounding Box

D A

B

C

Wirelength Forces and the X Bounding Box

D

Wire Forces in Analytical Placement

B has a wire force. C and D change their force directions.

26

Smoothing XHPWL

․ The wire function needs to be smooth enough for analytical placement to facilitate the minimizing process

․ XHPWL is not smooth

XHPWL(e)

27

Log-Sum-Exp Function

․ Use the log-sum-exp function to smooth the max-abs function

28

XHPWL-LSE Function

․ The smoothed version of the XHPWL function:

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Wire Forces

․ Forces are given by the gradient of the wire function

Horizontal Vertical

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Minimize: α W + β O

Analytical Placement Flow

Find an initial placement

Move cells

Update α and β

Spreading enough

Find wire forces (dW/dx) and spreading forces (dO/dx)

Cannot further minimizing

31

Experiments on Analytical Placement

․ Platform: AMD Opteron 2.6GHz

․ Analytical placer: NTUplace3 (ICCAD-2006)

․ Benchmarks: IBM version 2.0 (8 circuits)

․ Three different models MHPWL (Manhattan-half-perimeter wirelength) XHPWL (X-half-perimeter wirelength)

․ Use total X Steiner wirelength to evaluate the resulting placement

32

Resulting Wirelengths and CPU times

․ 3% less X-Steiner wirelength on average

․ 15% more CPU time on averageAnalytical Placement

Total X-Steiner Wirelength (x e8)

CPU Time (sec)

Wire model MHPWL XHPWL MHPWL XHPWL

ibm01 0.53 0.52 29 46

ibm02 1.50 1.45 81 84

ibm07 3.35 3.32 350 380

ibm08 3.66 3.57 350 367

ibm09 2.98 2.90 398 386

ibm10 5.81 5.55 538 596

ibm11 4.32 4.16 634 865

ibm12 7.78 7.50 644 648

Average 1.00 0.97 1.00 1.15

33

X Steiner Wirelength Reductions

․ XHPWL can consistently reduce X-Steiner wirelengths.

Up to about 5% reduction

0.90

0.92

0.94

0.96

0.98

1.00

ibm01 ibm02 ibm07 ibm08 ibm09 ibm10 ibm11 ibm12

Analytical (MHPWL) Analytical (XHPWL)

0.00

34

Outline

․ Introduction

․ Previous works

․ New wire model – XHPWL

․ Applications Min-cut partitioning placement Analytical placement

․ Conclusion

35

Summary of Wirelength Reductions

Normalized Steiner Wirelength

Algorithm Min-Cut Partitioning Analytical

Placement

Routing

M-Arch

M-Arch

M-Arch

X-Arch

X-Arch

X-Arch

M-Arch

X-Arch

M-Arch

X-Arch

X-Arch

X-Arch

ibm01 1.00 0.92 0.89 1.00 0.93 0.90

ibm02 1.00 0.93 0.89 1.00 0.93 0.91

ibm07 1.00 0.92 0.88 1.00 0.91 0.88

ibm08 1.00 0.92 0.88 1.00 0.92 0.89

ibm09 1.00 0.92 0.88 1.00 0.92 0.88

ibm10 1.00 0.92 0.88 1.00 0.92 0.89

ibm11 1.00 0.92 0.87 1.00 0.91 0.88

ibm12 1.00 0.92 0.88 1.00 0.92 0.88

Average 1.00 0.92 0.88 1.00 0.92 0.89

․ Using both X placement and X routing can reduce 11% to 12% wirelength on average

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Conclusions

․ The XHPWL model is effective to minimize the X-architecture wirelength

․ The generalized net-weighting method for min-cut partitioning placement can incorporate different wire models.

․ The smoothing XHPWL, XHPWL-LSE, is proposed for analytical placement

․ Using both X placement and X routing can reduce 11% to 12% wirelength on average

With only 8% to 22% CPU time penalty

Thank You!

Resulting Placement: IBM01