Www.kit.edu Directors Prof. Dr.-Ing. K.D. Müller-Glaser Prof. Dr.-Ing. J. Becker Prof. Dr. rer....

www.kit.edu

DirectorsProf. Dr.-Ing. K.D. Müller-Glaser

Prof. Dr.-Ing. J. Becker

Prof. Dr. rer. nat. W. Stork

Institute for Information Processing Technology

Karlsruhe Institute of Technology (KIT)

CONDOR Plenary Berlin

02-03.05.2012

Content

Overview Project StatusMilestones

StatusHard-/Software Library

Fault Tolerance of FPGA Hardware

Demonstrator plansPrototyping Board and ADCs, DACs

Demonstration Scenario

KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH)2 |

© Institute for Information Processing Technology

Content








Milestones



Milestone Milestone Describtion01.04.2010 Q101.05.201001.06.201001.07.2010 Q201.08.201001.09.201001.10.2010 Q301.11.201001.12.201001.01.2011 Q401.02.201101.03.201101.04.2011 Q5 M531 Struktur und Elemente der FPGA - Bibliothek01.05.201101.06.201101.07.2011 Q601.08.201101.09.201101.10.2011 Q7 M511 Entscheidung für Demonstrator - Modulationsformat und Festlegung der notwendigen Anforderungen an Komponenten des Übertragungssystems01.11.2011 M532 Ausfallsicherheit von FPGA - Hardware01.12.201101.01.2012 Q801.02.201201.03.201201.04.2012 Q901.05.201201.06.201201.07.2012 Q1001.08.201201.09.201201.10.2012 Q11 M533 Abschuss der Implementierung der Algorithmen01.11.201201.12.201201.01.2013 Q12 M551 Implementierung der Transceiver01.02.201301.03.2013

Content








Status Hard and Software Library



Component Status

Leon3 – Control System Implemented

AHB Multilayer Matrix Implemented

Modulation ASIP Implemented

FFT ASIP Implemented

iFFT ASIP Implemented

Internal DAC interface Implemented

External DAC interface Implemented

Internal ADC interface Implemented

External ADC interface Implemented

Demodulation ASIP Not Implemented Yet

Synchronisation ASIP Not Implemented Yet

Frequency Offset Correction Not Implemented Yet

Channel Correction ASIP Not Implemented Yet

PRBS Modules Not Implemented Yet

25GS/s Polyphase Halfband Decimator Implemented

Modulation ASIP

Modulation ASIP2 Samples per clock

Software configurable configuration

Unmodulated

Pilot tone

BPSK

QPSK

QAM 16

QAM 64

Software configurable pilot tones

*depends on max. Configuration table and pilot table size



FPGA Type LUT Registers BRAM Max. FrequencyVirtex-6 1986 962 2* 212 MHz

Modulation ASIP

AHB M

aster

Mapping

Map

MU

X

Null

Pilot

Mapping

Map

MU

XNull

Pilot

AHB M

aster

RAM 1DP

RAM 0DP

64 6464

32

32

32

32

6

6

Pilot RAM Configuration

Leon3Leon3

Instructions

Leon3

(i)FFT ASIP

Radix 2 (i)FFT ASIP2 Samples per clock

Max. 4 pipelined Radix 2 operations in a row

Address calculation and Twiddle Factor calculation supports any FFT size



Max. FFT size LUT Registers BRAM DSP Max. Freq.256 5744 4484 15 20 210 MHz

4096 6443 4678 16 20 210 MHz8192 6455 4734 32 20 210 MHz

FFT ASIP

MUX

RAM 0DP

64

32

32 BFStage 2

AHB M

aster

BFStage 1

BFStage 3

BFStage 4

AHB M

aster

BFLast

Stage

64

MUX

64

RAM 1DP

64

Code

Leon3

RAM RAM RAM

Control FSM

DAC/ADC Module

DAC/ADC ModulePrepares data to analogue interfaces

Serialization/Deserialization

Preamble Storage

2ers complement or binary

Clipping/rounding

Cyclic Prefix

Parallelism configurable by generics



DP Block RAM

DP Block RAM

DP Block RAM

DP Block RAM

DP Block RAM

DP Block RAM

DP Block RAM

DP Block RAM

SP

S-A

HB

S

lave

Inte

rfac

eS

PS

-AH

B

Sla

ve In

terf

ace

ClipClipClipClip

Leon3

CODE

Control FSM

Transmitter design for Demonstrator

System Controller (Leon 3)

32bit wide AHB

M

DDR3

IRQ ctrl

UART

Ethernet

S

AHB2APBAPB

S S

S S

JTAG

S

DA

C In

terf

ace

FFT ASIP 00Modulation

ASIP 0FFT ASIP 00

PR

BS

Inte

rfac

e


ASIP 0FFT ASIP 00


ASIP 0FFT ASIP 00


ASIP 0FFT ASIP 1

Ca. 2 Samples per clock per streamPRBS GeneratorGenerates data to be send (8 Samples per clock)

4 parallel data streams1 Modulation ASIP (QAM 16)

2 (i) FFT ASIPs

DAC Module Configured for 4 data streams (8 samples per clock cycle)

Cyclic Prefix about 8 samples (16 samples worst case)

4Gb/s @125MHz FPGA clock

FPGA Type LUT Registers BRAM DSPXC6VHX380T 44 281 9% 59 120 24% 146 19% 164 18%

Receiver Special Components

Digital Down Converterlow pass filter to separate signal of interest

decimation

Synchronizationtime synchronization (results in wrong sample to start FFT with)

frequency synchronization (results in orthogonal frequency problems)

Correctionlocal oscillator frequency offset (LOF offset)

sampling oscillator frequency offset (SOF offset)



Digital Down Converter

4 halfband filter stages

passband: 781,25 MHz

decimation factor: 16



FPGA Type LUT Registers BRAM DSP FrequencyVirtex-6 29424 40654 0 192 200MHz

Synchronisation

Comparing autocorrelation and energy of received signal is used to determine the preamble.

Phase difference of two consecutive, known symbols is used to compensate local frequency offset.



ncoBRAM CORDIC

CORDIC

Phase

BRAM

Σ

BRAM

Σ

BRAM

ncoBRAM CORDIC

CORDIC

Phase

BRAM

Σ

BRAM

Σ

BRAM

Channel Correction

Static version already implementedCorrecting symbols with correction factor calculated by special symbol after preamble

PlannedPilot symbol tracking

Continuous feedback for correction factor



Fault Tolerance

Redundancy enabled byModular design

Multilayer metrix

Spare ASIP instanceASIPs can be tested for functionality by software

When disfunction is detected, ASIP will be replaced by spare ASIP of that type

Broken ASIP might be repaired by reconfiguration (Single Event Upsets)

Partial ReconfigurationNumber of spare ASIPs can be broken down to one by using partial reconfiguration



Fault Tolerance

Redundancy using Partial Rekonfiguration




64bit wide AHB multilayer matrix

DP Block RAM Memory

DP Block RAM Memory

DP Block RAM Memory

DP Block RAM Memory

DP Block RAM Memory

S SS SS SS SS S

32bit wide AHB

Redundant Slot

M

IO Interface 1(e.g. Ethernet)

MASIP 1

(Mapping)

M

AH

B2A

HB

B

rid

ge

M M M M

S

DDR3

IRQ ctrl

UART

Ethernet

S

AHB2APBAPB

S S

S S

JTAGS

code

code

code

codeS S

ASIP 3(iFFT)

M

ASIP 4(iFFT)

code

S

DAC/ADCInterfaces

code

IO Interface 2(e.g. PRBS)

code code

S S S S

M

S S S


64bit wide AHB multilayer matrix

DP Block RAM Memory

DP Block RAM Memory

DP Block RAM Memory

DP Block RAM Memory

DP Block RAM Memory

S SS SS SS SS S

32bit wide AHB

ASIP 1(Mapping)

M

IO Interface 1(e.g. Ethernet)

MASIP 1

(Mapping)

M

AH

B2A

HB

B

rid

ge

M M M M

S

DDR3

IRQ ctrl

UART

Ethernet

S

AHB2APBAPB

S S

S S

JTAGS

code

code

code

code codeS S

ASIP 3(iFFT)

M

ASIP 4(iFFT)

code

S

DAC/ADCInterfaces

code

IO Interface 2(e.g. PRBS)

code code

S S S S

M

S S S

Content








Prototyping Boards

Protyping Boards Estimated availability (October‘12)

2x XC6VHX380T

2x XC6VHX565T

Sockets for Micram Ultra High Speed analogue converters

DAC 25GS/s

DAC 30GS/s

Extension Boards with High Speed analogue converters

DAC (MAX5881, 12-Bit, 4.3Gsps)

ADC (ADC12D1800, 12-Bit, 3.6 GSPS)



Demonstrator



Analogue Test Equipment

(IPQ)

25GS/ clk Digital Down Conversion

25GS/ clk Digital Down Conversion

Receiver 1

Receiver 2

Transceiver 1

Transceiver 2

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