W.Skulski APS April/2003 Eight-Channel Digital Pulse Processor And Universal Trigger Module. Wojtek...

W.Skulski APS April/2003

Eight-Channel

Digital Pulse Processor

And Universal Trigger Module.

Wojtek Skulski, Frank Wolfs

University of Rochester


Outline

•Description of the DDC-8 and DDC-1.

•Response to scintillator pulses.

•Applications.

•PHOBOS @ RHIC.

•SuperBall+DwarfBall.

•Prospects: 32 channels in a single VME slot.


Signal OUT40 MHz * 10 bits

JTAG connector

microprocessor

FPGA

ADC 40 MHz * 10 bits (8 channels)

16 bidirectional TTL lines + 1 in(fast parallel interface to XLM)

Analogsignal IN8 channelswithdigital offsetand gain control

RS-232

Logic connectors NIM 16 lines IN, 8 lines OUT

USB

RAM500 kB

ECL clock IN(optional)


Single channel 12-bit prototype, development and testing

• Input channel for waveform capture, up to 65 Msamples/s.

• Output reconstruction channel for development and diagnostic.

• The channel design to be used for the 12-bit multichannel board.

Signal OUT

JTAG connector

USBprocessor connector

FPGA

Signal IN

ADC 65 MHz * 12 bits

Fast reconstruction DAC 65 MHz * 12 bits

Variablegain amp


ASCNyquist

filter ADCSample

rateprocessor

Waveformmemory

Eventrate

processorSignal frompreamplifier

ClockGain and offset

control

Optional external trigger

analog digital

Legend:ASC = Analog Signal ConditioningADC = Analog to Digital Converter

Trigger

Pulseheightand shape

Individualtrigger


Analogsection

Digitalsection

Correlationprocessor

User-defined16 I/O lines

OR

parallelinterface

Compositeinternaltrigger

Channel 1

Analogsection

Digitalsection

Channel 2

...Analogsection

Digitalsection

Channel 8

Optional external trigger (one of the 16 NIM in lines)

Internal triggersfrom channels 1…8

16*NIM in 8*NIM out

Analogsection

Digitalsection

Channel OUT


# of analog input channels 8.# of analog output channels 1.# of logic inputs NIM 16. # of logic outputs NIM 8.# of in/out lines TTL 16+1.

Fast interfaces USB, parallel.Slow interfaces RS-232, SPI, I2C.Waveform memory 12 sec.Packaging NIM or standalone.

Intermediate scale: SuperBall+DwarfBall.

Medium scale: PHOBOS trigger.Small scale: table-top DPP systems, student research projects, DPP algorithm development.

Eight-channel digital pulse processor DDC-8


Signal from a pocket NIM pulserdigitized with the DDC-8 at 40 Msamples/s * 10 bits

Excellent response to a very fast pulse seen with the “spy channel”

DDC-8: how fast is the response?

tpulse < tsampling.

Digitization made possible

by the Nyquist filter

ffilter = 1/4 fsampling

Latency = 300ns

Input pulse


Response to scintillation pulses

•DDC-8 firmware is under development.

•Results obtained with DDC-1, 48 MHz @ 12 bits.

•Very fast plastic BC-404: tpulse < tsampling.

•NaI(Tl): tpulse > tsampling.

•CsI(Tl): particle identification.

•Phoswich: two-component FAST-SLOW pulses.


ADC trace Sample value

Sample number20.0 30.0 40.0 50.0 60.0

1400.0

1600.0

1800.0

2.0E+3

2200.0

Samples

Signal from a Bicron BC-404 detectordigitized with the 1-channel prototype at 48 Msamples/s * 12 bits

Excellent response to a very fast pulse

1 sample = 20.8 ns 1 sample = 0.2 ns

Tek screen for reference

Fast plastic scintillator, tpulse < tsampling.


Energy spectrumCounts

Filtered energy (arb. units)0.0 100.0 200.0 300.0 400.0 500.0 600.0 700.0 800.0 900.0 1.0E+3

0.0

50.0

100.0

150.0

200.0

250.0

Compton back-scatter

33 keV, Ba X-ray

77 keV, Pb X-ray

0.884 keV/bin

NaI 2" by 2"

662 keV, 137Cs

Energy 1

Signals from a Bicron 2”x2” NaI(Tl) detectordigitized with the 1-channel prototype at 48 Msamples/s * 12 bits

137Cs

Medium-fast scintillator pulses: NaI(Tl)

ADC waveformSample value

Sample number, 20.8 ns/sample400.0 420.0 440.0 460.0 480.0

1.0E+3

1500.0

2.0E+3

Samples NaI(Tl) 2" by 2"


-ray

1 cm3 CsI(Tl) + phototube 1-channel prototype at 48 Msamples/s * 12 bits

-particle

Slow scintillator pulses: CsI(Tl)


Sample number50.0 100.0 150.0 200.0

1900.0

1950.0

2.0E+3

2050.0

2100.0

gamma-ray

Samples


Sample number50.0 100.0 150.0 200.0

2.0E+3

2050.0

2100.0

alpha-particle

Samples


raditional slow-tail representation

1 cm3 CsI(Tl) + phototube

1-channel prototype

at 48 Msamples/s * 12 bits

natTh radioactive source

“tail” window not yet optimized

PID = TAIL / TOTAL

Note energy-independent PID

Particle ID from CsI(Tl) PRELIMINARY


CsI(Tl) crystal

cosmic ray

phototube

teflon

Bicron BC-404FAST

SLOWADC trace Sample value

Sample number0.0 50.0 100.0 150.0 200.0

1700.0

1800.0

1900.0

2.0E+3

2100.0

SLOW

FAST

Samples

Signal from a phoswich detectordigitized with the DDC-1 48 Msamples/s at 12 bits

FAST clearly separated from SLOW

1 sample = 20.8 ns


Applications of the DDC-8

•The combo system DDC-8 and XLM-72.•Online energy and particle ID.

•DwarfBall and SuperBall.•Real-time trigger logic.

•Phobos @ RHIC.

•Standalone table-top 8-channel digitizer.•DPP algorithm development.•Standalone data acquisition and histogramming.•Convenient USB interface.


Nominal Collision Region

• Analog signals: Paddles, Cerenkov, ZDC.• Logic signals from conventional NIM. • 1st level processing: DDC-8.• 2nd level processing: XLM-72.• Accept/reject event within about 1 sec.

• Note: digitization latency = 300ns.

Application: online PHOBOS trigger

Trigger counters, one side.(ZDCs are off picture.)

PHOBOS @ RHIC


Neutron Calorimeter SuperBall.16 m3 organic liquid scintillator.

• Online pulse shape analysis with DDC.

• Charged particle ID with CsI(Tl)/plastic.

• Neutron capture counting and timing.

• 1st level processing: DDC-8.

• 2nd level processing: XLM-72.

Application: SuperBall + DwarfBall

4 charged particle detector DwarfBall/DwarfWall.Plastic+CsI(Tl) phoswich detectors.


8 chanXLM-72

900 MFLOPs4 MB

40,000 gates

DAQ8 chan

8 chan

32 flash ADCs

32*NIM out

8 chan

64*NIM in

On-board monitoring

1.2 million gatesin the FPGAs

On-the-fly datapreprocessing

Four independent parallel interfaces, 100+ MB/s.

VME

Flash ADC front end


Digital interface

DSP 900 MFLOPs

FPGA

2Mb SRAM

2Mb SRAM72 ECL lines(four independent 17-bit connectors + 4 extra bits).

TTL-ECL


Plans

•April ‘03: workshop: DPP in PHOBOS @RHIC.• Work out the details and proposed solutions for PHOBOS.

•Winter ‘03: enhance the system DDC+XLM.• 40+ channels per VME slot.• More channels, 12 bits, etc.• High-resolution spectroscopy.

•Mundane details.• DPP algorithm development for FPGA and embedded micro.• Firmware and embedded software.• User interfaces.

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