WRR ARBITER Characterization Presentation
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Transcript of WRR ARBITER Characterization Presentation
WRR ARBITERCharacterization Presentation
Students: Ofer SobelGuy Marcus
Supervisor: Moshe Porian 16/11/10
Introduction• WRR algorithm arbitrates between clients,
requesting usage of the same resource. • Arbitration is performed considering priority
weights, assigned to each client.
ARBITER
Project Goal
Implementing a WRR ARBITER on an FPGA
• Implementation will be to Altera Cyclone® II 2C35 FPGA located on an Altera DE2 board• A simulation environment for the WRR arbiter to
interact with will also be implemented.
Specifications
• Generic number of clients (1 to 4)• Communication with host via UART protocol• Real-Time configurable arbitration weights• Interaction with switches and LEDs• 60 MHZ system clock (generated from board’s 50MHz
clock)
Project steps
• Determining specifications• Architecture characterization • Conceptual design• VHDL implementation• Verification• Synthesis• Real-Time testing
Top level design
RX
TX
UART_ RECEIVER
UART_ TRANSMITTER
MSG_ DECODER
FIFOREGISTER
BUSMASTER
MSG_ ENCODER
FIFO
ARBITER
REQUESTS
GRANTS
FILT
ER
TICK_GENERATOR
EXT_CLOCK
EXT_RESET
PLL
RESET_BLOCK
SYS_CLK
SYS_RST
CONTROLLER
CRC
CRCWRR ARBITER
HOST
REG
ISTE
R B
US
Communication with host – UART
Start bit = ‘0’ Stop bit = ‘1’Data Parity
Idle state: Constant marking (‘1’). Start bit: 1 bit of spacing (‘0’). Data: 5 to 8 data bits.Parity: optional parity bit of type ‘odd’ or ‘even’.Stop bit: 1 bit of marking (‘1’). Baud rate: 2400, 4800, 9600, 19200, 38400, 57600 or 115200 bits/sec ±3%
Message StructureA packet of data is constructed in the following way
(every block is 1 byte long :)
Start0x00
Type StartAddress Length Data(1) Data(n) CRC
n is determined by ‘Length’ byte
scope for CRC
write: 0x00read: 0x1Freply: 0x07status: 0x18
End0x15
x8+x7+x6+x4+x2+1
RX path – data flow
1. Host sends message via RX line.
RX UART_ RECEIVER MSG_ DECODER
FIFO
REGISTERBUS
MASTER
CRCWRR ARBITER
HOST REG
ISTE
R BU
S
MSG_ENCODER
2. Receiver packs incoming bits (UART protocol). 3. Message-Decoder decodes sequences of bytes (message
protocol). 4. Register-Bus-Master executes message according to type:
Writes data to the Register Bus/ Initiates reply message.
TX path – data flow
TX UART_ TRANSMITTER
REGISTERBUS
MASTER
MSG_ ENCODER
FIFO
Blocks on REG_BUS
CRC
WRR ARBITER
HOST
REG
ISTE
R B
US
MSG_DECODER
1. Register-Bus-Master is signaled to initiate a message.2. Register-Bus-Master loads data to the Message-Encoder and
encoder FIFO.3. Message-Encoder drives the Transmitter with bytes (message
protocol). 4. Transmitter transmits message to the host via the TX line
(UART protocol).
Verification concept
Verification concept (cont.)
Simulation Environment• Simulation using input scripts and output logs • Error/warning tracking• Direct/ Random simulations• Golden model reference• Waves monitoring and recording
GUI Demo
Schedule