Writing Problem and Hypothesis Statements for Engineering Research(23)

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    Writing Problem and Hypothesis

    Statements for Engineering Research(23)/

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    Setting of work proposal: ??

    Work problem:?

    Quantitative specification of problem:?

    Importance of problem:,?

    Project need: ,?

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    Work objective:?

    Methodology to achieve objective

    :?Anticipated results:

    ?

    Contribution to field:?

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    () PNs play an increasingly significant role in fiber to the xnetworks, e.g., fiber to the home (FTTH) and fiber to the building(FTTB). A PON specified by G.983.1 comprises an optical line terminal(OLT) connected to multiple optical network terminals (ONTs) in apoint-to-multi-point network. A PON network is characterized by itsability to share upstream bandwidth between OLT and ONTs. The

    bandwidth between OLT and ONTs. The OLT is responsible forallocating bandwidth to the ONTs on traffic contracts. The OLT shoulddevise a dynamic bandwidth allocation (DBA) method to allocatebandwidth dynamically, thus responding effectively to the dynamicchanges in traffic demand for vaious ONTs to the network resourcesefficiently. However, the conventional DBA is based onqueue-status reports (SR) sent by ONTs to OLT periodically. The grantscheduler at the OLT defines a granting cycle W. During each Wperiod, the OLT solicits the queue-status reports from ONTs; the ONTsrespond with queue-status reports; and, then, the grant schedulerprocesses these reports and assigns bandwidth for the next W period.The SR delay time, OLT processing time, and PON round-trip timedetermine the minimal response time.

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    ()During this period, the queue status changes, often causing SR-DBA to fallbelow optimal accuracy. In addition to bandwidth efficiency, SR-DBAdeployment heavily depends on interoperability between OLT and ONTsystems. Specifically, the complexity of ONTs increases due to the higher real-time constraints and additional circuitry required to support queue-statusreports. For instance, SR-DBA is inefficient under varyingtraffic conditions. For instance, the overall bandwidth utilization remains under80% and the packet delay usually exceeds 4 ms. SR-DBA also implies highbuffer requirements over 4 MB and a high packet loss ratio exceeding 5%. SR-DBA is inefficient for FTTH, creating a situation in whichinefficient bandwidth utilization expends a considerable amount of investmentin PON networks. Additional resources are necessary to achieve the requiredbandwidth. Additionally, delay-sensitive services such as voice or interactiveservices cannot comply with standard requirements under a high packet delay.

    Moreover, users can not wait for a response from the peer for a long delay time.High buffer requirements also imply high overhead costs for a service providerand, ultimately, high subscription charges for users. In sum, a high packet losscannot satisfy the service level agreement and deteriorate the quality of severalservices such as in video and FTP. Therefore, a predictive DBAmethod based on pseudo status report from ONTs must be developed toincrease the DBA efficiency.

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    () A predictive DBA method based on pseudo status report

    from ONTs can be developed to increase the DBA efficiency. The

    proposed method can fully grant the excess bandwidth and grants each

    active ONT at least once in a W period to decrease the packet delay

    and increase the link throughput. To do so, the usage

    pattern for ONT bandwidth can be monitored as pseudo status reports.

    In a period W, the allocated bandwidth and used bandwidth of each

    ONT can then be compared. Next, several parameters can be

    manipulated to control the trade-off between optimizing link throughput

    and packet delay. Additionally, the bandwidth in the next W period can

    be predicted. Moreover, a bandwidth assignment map for the next Wperiod can be constructed based on these demand predictions.

    Furthermore, the DBA can be fine-tuned for various scenarios, e.g.,

    FTTH vs. FTTC.

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    () As anticipated, the predictive DBA method can elevate the

    PON efficiency. While the overall bandwidth utilization can exceed

    80%, the packet delay can be reduced to less than 4 ms. In addition to

    low buffer requirements under 4 MB and a low packet loss ratio not

    exceeding 5%, the predictive DBA method also implies buffer

    requirements less than 4 MB, and an extremely low packet loss ratio

    under 5%., thus satisfying requirements of delay and packet loss

    sensitive services. Additionally, the predictive DBA method can

    simplify ONT design and reduce the risk of having inter-operability

    problems between OLTs and ONTs from different vendors. Moreover,

    the predictive DBA method can support not only dynamic bandwidthallocation, but also a static one that is used for fixed bandwidth traffic

    such as voice and leased line traffic such as voice and leased line

    traffic.

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    ()Furthermore, the proposed method can contain several parameters that

    not only control the trade-off between throughput optimization and

    packet delay optimization, but also provide the ability to fine tune the

    DBA for various scenarios. The predictive DBA method can also be

    used accurately reflect a certain level of fairness among ONTs by

    determining the effective traffic rate and packet delay.

    Importantly, the proposed predictive DBA method can be more efficient

    than SR-DBA with respect to increasing the PON efficiency in order to

    reduce the amount of equipment in PON systems The proposed

    method can also reduce overhead costs of the service providers

    implementing PON networks., ultimately making next generationnetwork services less expensive and of high quality.

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    () Time to market delivery and reduction of overhead costsin the electronics industry have received increasing attention in recentyears owing not only to stringent competition in audio and video hand-held devices, but also to the increasing number of companies in thismarket. For instance, this market niche includes various mp3, photoand MPEG4 players, allowing customers to base their decisions on

    price, appearance, storage capacity of FLASH or mini hard disk, audioor video quality, as well as functions and operational interfaces. Anotable example is iPod. As a fascinating operational interface, the

    Apple Click Wheel possesses 20G or 30G large capacity that enablesusers to store thousands of mp3 files. However, theconventional hardware design method depends only on experience ofthe designer. As mentioned above, time to market delivery andreduction of overhead costs are vital to product success or failure.Unfortunately, such requirements are normally exclusive if designersadopt the conventional method. Consequently, designers addredundant hardware components if hardware computational power isinsufficient. Insufficient hardware computational power fails to satisfythe basic product requirements. Additionally, more functions required

    complicate hardware design, explaining the redundancy in hardwarecomponents.

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    () For instance, the likelihood of success inhardware design at ABC Company using the conventional method isroughly 50%. Therefore, ABC Company mandates that two teamsprocess the same hardware design, resulting in at least one teamexperiencing success. Given the competition between the two teamsto succeed, more hardware components are added to ensure sufficient

    hardware computational power in order to comply with productrequirements. Such tendency increases hardware costs and powerconsumption. Power consumption is essential hand-held devices giventhat batteries are the power resource of such devices. An excessive amount of human resources expended in hardwaredesign lowers the success probability below 100%. Additionally,success probability varies according to knowledge expertise of thedesigners. Given the inability to reduce high hardware costs, manyredundant hardware components are added owing to the impossibilityof ensuring sufficient computational power, ultimately resulting in thefailure of hand-held devices owing to battery constraints. Therefore, a novel method must be developed to determine whetherhardware deign complies with minimum product requirements and

    ensure that the hardware design contains no redundant hardwarecomponents.

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    () A novel method can be developed to determine whetherhardware deign complies with minimum product requirements andensure that the hardware design contains no redundant hardwarecomponents. To do so, the hardware cycle can besimulated accurately. SystemC is a C++ class library method to createa cycle-accurate model of hardware architecture, as well as interfaces

    of System On a Chip (SoC). Therefore, SystemC can be adopted asthe simulator language. For instance, if designers want to designhardware such as a MPEG4 decoder, the hardware can be simulatedby writing the system using SystemC. Designers can then fee theMPEG4 data to the simulator and evaluate whether the computationalpower is sufficient to comply with product requirements, e.g., 30 framesper second. Next, if the computational power is sufficient, redundanthardware components can be removed. If computational power isinsufficient, some hardware components, e.g., digital signal processors(DSPs), can be added to increase the computational power. Thecomputational power can be evaluated again until the minimum numberof hardware components can be used to conform to productrequirements. Additionally, the power consumption model can be

    incorporated into a simulator to evaluate power consumption.

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    () As anticipated, the proposed method can minimizehardware costs because minimal hardware components are used tocomply with product requirements; hence, the success probabilityapproaches 100%. Adding or removing hardware components in asimulator is easier than doing so in actual hardware, thus reducing thetime needed to verify the completeness and performance of hardware

    significantly. Moreover, the added power consumption model can helpdesigners to design higher power-saving hand-held devices. Importantly, the proposed method can orient hardware designers onhardware functions, performance and power-consumption. Additionally,companies can minimize hardware overhead costs and reduce thetime-to-market delivery period. Furthermore, the proposed method cancontribute to efforts of hardware architecture researchers attempting toidentify hardware architecture that performs optimally and saves power.

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