Workshop - November 2011 - Toulouse

SoCKET Workshop Introduction

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Program (1st half day)10h-10h30 Welcome and presentation of the SoCKET project (V.Lefftz,

Astrium) 10h30-12h Description of the industrial case studies

Avionics flight control remote module (P.Moreau, Airbus)Space high resolution image processing (V.Lefftz, Astrium)Pedestrian tracking with smart cameras (P.Brelet, Thales R&T)Controller for an absolute scalar magnetometer (J.Bertrand,

A.Boness, CNES)System for secure communication (P.Gouriou, Maya)

Synthesis of critical embedded systems needs (V.Lefftz, Astrium)

Lunch

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Program (2nd hald day)13h30-14h20 Tutorial "SoC modeling with SystemC TLM" (L.Maillet-

Contoz, STMicroelectronics)14h20-15h10 Tutorial "IP-XACT for critical system assembly and

requirements traceability" (E.Vaumorin and R.Lucas, Magillem Design Services)

Break15h30-16h20 Tutorial "High-level synthesis" (P.Coussy, Lab-STICC UBS)16h20-17h10 Tutorial "Assertion-Based Verification (ABV): Verification of

logical and temporal properties" (L.Pierre, TIMA Univ. Grenoble)17h10-18h Tutorial "Worst Case Execution Time: theory and practice"

(H.Cassé, IRIT Univ. Toulouse)

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Program (3rd half day)8h–9h Presentation of the proposed design flow, and application to

the different case studies (L.Maillet-Contoz, STMicroelectronics) 9h - 10h45 SystemC modeling in the design flow

L.Letellier and P.Moreau (Airbus Operations S.A.S.)A.Berjaoui, A.Lefèvre, C. Le Lann (Astrium)A.Boness (CNES)P.Brelet (Thales R&T)

Break11h15-12h IP-XACT in the design flow

L.Letellier and P.Moreau (Airbus Operations S.A.S.)P.Brelet (Thales Research & Technology)

Lunch

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Program (4th half day)13h30-14h20 High-level synthesis in the design flow

J.Lachaize (Astrium)P.Brelet (Thales Research & Technology)

14h20-15h20 Verification in the design flow L.Pierre (TIMA Univ. Grenoble) V.Lefftz (Astrium), L.Pierre (TIMA Univ. Grenoble) A.Boness (CNES)

15h20-15h40 Debug in the design flowP.Gouriou (Maya)

15h40-16h20 Presentation of the demonstrations

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Demonstrations16h20-18h Break and demonstrations

High-Level Synthesis: an efficient solution to design hardware accelerators in SoC (Lab-STICC UBS)

FPGA implementation of the DSP unit and model of a magnetometric probe (CNES)

Automatic and efficient assertion-based verification for SystemC TLM hardware/software platforms (Airbus Operations S.A.S., Astrium, TIMA Univ. Grenoble)

Demonstration of object detection on a SoC (Thales Research & Technology)

Workshop - November 2011 - Toulouse

SoCKET Collaborative Project(SoC toolKit for critical Embedded sysTems)

AEROSPACE VALLEY DAS Systèmes EmbarquésMINALOGIC Cluster EmSoC

Vincent LEFFTZ - Astrium SatellitesMail: vincent.lefftz@astrium.eads.net

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SoCKET Administrative figuresFrench poles of competitiveness project

5ieme FUI-AAP (5th Call to Project: Common Inter-ministries Funds)

Labelled by MINALOGIC(Grenoble) and AESE(Midi-Pyrenee) polesSupported by ASTECH(Paris)/PEGASE(PACA)/AESE AllianceAdministrative Start: 2 June 2008Technical Start: 9 October 2008Official End: 30 November 201111 partners – 75 man.year - ~10M€

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Wording (1)SoC = System On Chip

Integration on the same die of various HW IPs and SW parts providing a given set of functions.

SoC technology advantages: Better performance Better integration

Resources usage optimization Mass and consumption gains Reliability

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Wording (2)Critical Embedded Systems:

Defined by safety level requirementsSafety level defined by the consequences of any

deviation against the nominal behaviour putting in danger humans, goods, mission achievement, and/or economic returns

Require a certification agreed by internal or accredited third party audit

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Technological challengesApplication needs lead to develop more and more complex

embedded systems at HW AND SW levels

Master this complexity is the key point for next industrial projects in order to improve the time cycle and the costs of critical embedded system development and its validation/qualification/certification

Define a “seamless” design flow built upon an integrated set of engineering tools to master this complexity and get the expected productivity gain

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Industrial challengesAeronauticsCertification of SoC-based systems -> time cycle, costsDistributed computers -> Miniaturization, wiring and mass

Space data processingQualification of SoC-based systems -> time cycle, costsComputing power -> new mission feasibility Complexity increase -> Integration without risk

Electrical distributionCertification of secured power-> Secured application-> New markets

Semiconductor industryHigh complexity SoCs with increasing volume of SW

-> Time cycle, costs

-> SoCs validation/certification

-> New markets

Image processing

VideoI/O

Audio

CLK & Power management

ARM Core

ARM Core

MEMUnits

IP Units

IP Units

MEMUnits

MEMUnits

Image processing

VideoI/O

Audio

CLK & Power management

ARM Core

ARM Core

MEMUnits

IP Units

IP Units

MEMUnits

MEMUnits

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ContextAlready established collaboration between

aerospace industries (South-West of France) and semiconductor industry/academics (South-East of France)

Other projects address the SoC development problematic but not with the critical embedded system point of view

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ObjectivesDefine a “seamless” development flow, integrating the

equipment qualification/certification, from the system level, to the IC and validated SW on these ICs;

Master the SoC solutions for critical embedded systems;

Master the “system dimension” (software + hardware) into the SoCs integration problematics;

Master the complexity, the time cycle reduction, design optimisation of SoC-based systems

Implement requirements traceability through all the design flow;

Evaluate the HW simulation models (get from the design flow) usage for the integration and the validation of the critical embedded SWs.

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“Seamless” design flowCo-design processClassical process

System Specifications

HW/SWPartitioning

HW Design

HW Simulation

HW Synthesis(netlist)

Unit Tests

Equipment Tests

SW Design

SW Simulation

SW Compilation(code binaire)

Modules Unit Tests

SW Validation Tests

HW/SW Integration

HW Synthesis(netlist)

Unit Tests

Equipment Tests

SW Compilation(binary code)

Modules Unit Tests

SW Validation Tests

HW/SW Integration

HW Design

HW Simulation

SW Design

SW Simulation

HW/SWPartitioning

HW/SWco-simulation

System Specifications

Executable Specification(system level simulation)

Alternate architecturesexploration

TO

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“Seamless” design flowFormalisms unification

Remove any semantic holes into HW/SW interfaces

Models transformation operators AutomationTraceabilityOverall coherency insurance

Tools interoperabilityKeystone of 2 previous points

Co-design processClassical processSystem Specifications

HW/SWPartitioning

HW Design

HW Simulation

HW Synthesis(netlist)

Unit Tests

Equipment Tests

SW Design

SW Simulation

SW Compilation(code binaire)

Modules Unit Tests

SW Validation Tests

HW/SW Integration

HW Synthesis(netlist)

Unit Tests

Equipment Tests

SW Compilation(binary code)

Modules Unit Tests

SW Validation Tests

HW/SW Integration

HW Design

HW Simulation

SW Design

SW Simulation

HW/SWPartitioning

HW/SWco-simulation

System Specifications

Executable Specification(system level simulation)

Alternate architecturesexploration

TO

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Positioning vs other projects

OPEES

OpenTLMTopcased

SoCLib

SoCKETMultival

IP-XACT

Toolset for

Virtual Prototyping

XML Description

SystemC IPs

library

Verification methods &performance analysis

Tools&collaborativeplatform

Tools &Methods

TWINS

HW/SWflow

SPICES

AADL->SystemCgenerator

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SoCKET: Consortium• International groups: Airbus, Astrium, STMicroelectronics,Thalès R&T

• PMEs:PSI-S, PSI-E, Magillem Design Services

• Academics and Research Centers:CNES, IRIT, Lab-STICC, TIMA

Paris

Toulouse

Grenoble

Lorient HLSGaut

Security Camera Use Case

Secondary Flight Control Computer

Image ProcessingMoving Object Tracking

& Compression

Swarm MagnetometerComputer

SW Properties WCET

OTAWA

IP-XACT

SystemC/TLM modellingHeterogeneous

Simulation Techniques

ABVISIS & HORUS

SoC Debug & Trace

SW Secure Architecture

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Thank you for your attention

? ??

Any questions ?

ConclusionPresentation: Available Next Week

http://socket.imag.fr Semiconductor world and critical embedded systems

industries cross-fertilization1st prototype enabling the maturation of the Critical

Embedded Systems needsVarious projects started or are currently brewing to

refine and complete the design flow

Workshop - November 2011 20