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Transcript of Work in Progress – Do Not Publish! 1 Summer Public Conference ORTC 2010 Update Messages A. Allan,...
Work in Progress – Do Not Publish!
1
Summer Public Conference ORTC 2010 Update Messages
A. Allan, 07/14/10, Rev 8
Work in Progress – Do Not Publish!
2
Summer Update to the 4/3 Italy 2009 ITRS ORTC1) ORTC Model Proposals to TWGs for TWG Interdependency Preparation for other
ORTC section features:1) “Beyond CMOS” timing unchanged in 2010 for ERD/ERM early research and transfer to PIDS;
however need for continued discussion about transfer of III/V Gate Material technology in 2011 Renewal
2) Logic “Equivalent Scaling” Roadmap Timing Update underway, and ongoing discussion of alignment of “node” and dimensional Trends for 2011 Renewal
3) New “More than Moore” (MtM) white paper draft review and discussion underway for 2011 ITRS Renewal impact and added to the ITRS website at www.itrs.net
2) MPU contacted M1 1) Unchanged for 2010 [validated by FEP data]2) 2-year cycle trend through 20133) Cross-over DRAM M1 2010/45nm4) Smaller 60f2 SRAM 6t cell Design Factor5) Smaller 175f2 Logic Gate 4t Design Factor6) Proposal from Taiwan [2011 Renewal]: Design TWG evaluate 1-year pull-in of M1
3) DRAM contacted M1 1) Unchanged for 2010: Dimensional M1 half-pitch trends remain unchanged from
2007/08/09 ITRS; new 4f2 Design factor begins 20112) Proposal [2011 Renewal]: 1-year pull-in of M1 and bits/chip trends; 4f2 push out
4) Flash Un-contacted Poly1) Unchanged for 2010: 2yr cycle trend through 2010/32nm; then 3yr cycle and also added
“equivalent scaling” bit design:1) Inserted 3bits/cell MLC 2009-11; and delayed 4bits/cell (2 companies in production) until 2012
2) Proposal [2011 Renewal]: 1-year pull-in of Poly; however 3bits/cell extended to 2018; 4bits/cell delay to 2019
Work in Progress – Do Not Publish!
3
5) Unchanged for 2010 Tables: MPU GLpr – ’08-’09 2-yr flat; Low operating and standby line items track changes
6) Unchanged for 2010 Tables: MPU GLph – ’08-’09 2-yr flat with equiv. scaling process tradeoffs; Low operating and standby line items track changes
1) Performance targets (speed, power) on track with tradeoffs7) Unchanged for 2010 Tables: MPU Functions/Chip and Chip Size Models
1) Utilized Design TWG Model for Chip Size and Density Model trends – tied to technology cycle timing trends and updated cell design factors
2) ORTC line item OverHead (OH) area model, includes non-active area3) ORTC model impact from Taiwan proposal will be evaluated for 2011 Renewal
8) DRAM Bits/Chip and Chip Size Model Unchanged for 2010 Tables - 3-year generation “Moore’s Law” doubling cycle;
1) smaller Chip Sizes (<60mm2) with 4f2 design factor included 2) ORTC model impact updating from PIDS/FEP Survey proposals will be evaluated for 2011
Renewal9) Flash Bits/Chip and Chip Size Model Unchanged for 2010 Tables
1) 2-year generation “Moore’s Law” doubling cycle; 2) growing Chip Sizes after return to 3-year technology cycle3) ORTC model impact updating from PIDS/FEP Survey proposals will be evaluated for 2011
Renewal]10) IRC 450mm Position: Pilot lines/2012; Production/2014-16 Unchanged for 2010; also
Unchanged: “double S-curve” graphic in 2009 Executive Summary1) 450mm Program status and Long-Range IEM v12 Demand Update Scenario was presented by
ISMI to IRC for 2011 ITRS Renewal preparation2) ISMI believes the 450mm program is presently on track to meet ITRS Timing
Italy 4/9 Update to the 12/16 Taiwan 2009 ITRS ORTC (cont.)
Work in Progress – Do Not Publish!
4
2009 Definition of the Half Pitch – unchanged[No single-product “node” designation; DRAM half-pitch still litho driver; however,
other product technology trends may be drivers on individual TWG tables]
Source: 2009 ITRS - Exec. Summary Fig 1
Poly Pitch
Typical flash Un-contacted Poly
FLASH Poly Silicon ½ Pitch = Flash Poly Pitch/2
8-16 Lines
Metal Pitch
Typical DRAM/MPU/ASIC Metal Bit Line
DRAM ½ Pitch = DRAM Metal Pitch/2
MPU/ASIC M1 ½ Pitch = MPU/ASIC M1 Pitch/2
2009 Unchanged
Work in Progress – Do Not Publish!
5
Production Ramp-up Model and Technology/Cycle Timing
Months
0-24
Alpha
Tool
12 24-12
Development Production
Beta
Tool
Production
Tool
First
Conf.
Papers
First Two Companies
Reaching Production 2
20
200
2K
20K
200K
AdditionalLead-time:ERD/ERM
Research andPIDS Transfer
Volum
e (Wafers/M
onth)
Production Ramp-up Model and Technology Cycle Timing
Source: 2009 ITRS - Exec. Summary Fig 2a
2009 – Unchanged
*Examples: 25Kwspm ~= 4.5Mu/mo @ 280mm210Mu/mo @ 140mm215Mu/mo @ 100mm222mu/mo @ 70mm2
Work in Progress – Do Not Publish!
6
Continuing SoC and SiP: Higher Value Systems
Moore’s Law & MoreMore than Moore: Diversification
Mo
re M
oo
re:
Min
iatu
riza
tio
nM
ore
Mo
ore
: M
inia
turi
zati
on
Combining SoC and SiP: Higher Value SystemsBas
eli
ne
CM
OS
: C
PU
, M
emo
ry,
Lo
gic
BiochipsSensors
ActuatorsHV
PowerAnalog/RF Passives
130nm
90nm
65nm
45nm
32nm
22nm...V
130nm
90nm
65nm
45nm
32nm
22nm...V
Information Processing
Digital contentSystem-on-chip
(SoC)
Interacting with people and environment
Non-digital contentSystem-in-package
(SiP)
Beyond CMOS
Traditional ORTC Models
[Ge
om
etr
ica
l &
Eq
uiv
ale
nt
sc
ali
ng
]
Sca
lin
g (
Mo
re M
oo
re)
Functional Diversification (More than Moore)
HVPower
Passives
Sca
lin
g (
Mo
re M
oo
re)
2007 ITRS Executive Summary Fig 4New work In 2009
New in 2009: Research and PIDS transfer timing clarified Work underway to identify next storage element
Online in 2008: SIP “White Paper”www.itrs.net/papers.html
New in 2009: More than Moore “White Paper” More CommentaryIn ITWG Chapters
New in 2009: Survey updates to ORTC Models Equivalent ScalingRoadmap TimingSynchronized with PIDS and FEP
Source: 2009 ITRS - Executive Summary Fig 1
2009 WAS
Work in Progress – Do Not Publish!
7
Moore’s Law & MoreMore than Moore: Diversification
Mo
re M
oo
re:
Min
iatu
riza
tio
n
Combining SoC and SiP: Higher Value SystemsBa
se
lin
e C
MO
S:
CP
U,
Me
mo
ry,
Lo
gic
BiochipsSensors
ActuatorsHV
PowerAnalog/RF Passives
130nm
90nm
65nm
45nm
32nm
22nm
16 nm...V
Information Processing
Digital contentSystem-on-chip
(SoC)
Beyond CMOS
Interacting with people and environment
Non-digital contentSystem-in-package
(SiP)
2010 Update/2011 Renewal MtM Graphic Proposal from Europe IRC 2010 MtM White Paper
Update
[Note: iNEMI Roadmap work will Propose additional modifications and
Cross-roadmap alignment workTo the IRC at the July USA ITRS
Meetings]
Work in Progress – Do Not Publish!
8
Current figure 8c in ITRS executive summary (page 69)Equivalent Scaling Process Technologies Timing WAS 2009
[Orig. Source: ITRS, European Nanoelectronics Initiative Advisory Council] (ENIAC)Source: 2009 ITRS - Exec. Summary, Fig 8c, Equivalent Scaling Process Technologies Timing
PDSOI FDSOI
bulk
stressors + high µ SiGematerials
MuGFETMuCFET
Electrostaticcontrol
SiON
poly
high k
metal
Gatestack
+ III/V High µAlternative
Channel Mat’ls
Channelmaterial
high k [II, etc]
metal
Work in Progress – Do Not Publish!
9
Equivalent Scaling Process Technologies Timing Final Proposal - for 2011 work
Proposed figure 8c in ITRS executive summary
Metal
High kGate-stack material
2009 2012 2015 2018 2021
Bulk
FDSOI
Multi-gate(on bulk or SOI)Structure
(electrostatic control)
Channelmaterial
Metal
High k
2nd generation
Si + Stress
S D
High-µ material ?
S D
PDSOI
Metal
High k
nth generation
= Additional timing movementconsiderations for 2011 ITRS work
See also PIDS, FEP, ERD, and ERM chapters’ text and tables for additional detail)
Work in Progress – Do Not Publish!
10
ERD/ERM Long-Range R&D and PIDS Transfer Timing Model Technology Cycle Timing [Example: III-V MOSFET High-mobility Channel Replacement Materials]
Source: 2009 ITRS - Executive Summary Fig 2b
Months
Alpha
Tool
Development Production
Beta
Tool
Product
Tool
Vol
ume
(Waf
ers/
Mon
th)
2
20
200
2K
20K
200KResearch
-72 0 24-48 -24-96
Transfer to PIDS/FEP(96-72moLeadtime)
First Tech. Conf.
Device PapersUp to ~12yrs
Prior to Product
20192017201520132011 2021
III/V Hi- gateExample:
1st 2 Co’s
Reach
Product
First Tech. Conf.
Circuits PapersUp to ~ 5yrs
Prior to Product
2009
Unchanged
Work in Progress – Do Not Publish!
11
Vo
lum
e
Years
Alpha
Tool
Beta
ToolTools for Pilot line
32nm (extendable to 22nm) M1 half-pitch capable Beta tools by end of 2011
Consortium Pilot Line Manufacturing
22nm (extendable to 16nm) M1 half-pitch capable tools
Development Production
450mm 32nm M1 half-pitchPilot Line Ramp
2010 2011 2012 2013 2014 2015 2016
Beta
Tool
Production
Tool
450mm Production Ramp-up Model[ 2009 Figure 2c A Typical Wafer Generation Pilot Line and Production “Ramp” Curve ]
Source: 2009 ITRS - Executive Summary Fig 2c
2009 Unchanged
Work in Progress – Do Not Publish!
12
IRC Graphic update Proposal Considerations
Also 450mm “Dual S-Curve” and possible alignment with “Node vs. Technology Trends”
Work in Progress – Do Not Publish!
13
13
2009 ITWG Table Timing: 2007 2010 2013 2016 2019
68nm 45nm 32nm 22nm 16nm2009 IS ITRS DRAM M1 :
2009 ITRS MPU/hpASIC M1 : 76nm 65nm 54nm 45nm 38nm 32nm 27nm 19nm 13nm
MPU/hpASIC “Node”: “45nm” “32nm” “22nm” “16nm” “11nm” “8nm”
2009 ITRS hi-perf GLph : 32nm 29nm 29nm 27nm 24nm 22nm 20nm 15nm 12nm2009 ITRS hi-perf GLpr : 54nm 47nm 47nm 41nm 35nm 31nm 28nm 20nm 14nm
45nm 32nm 22nm 16nm 11nm2009 IS ITRS Flash Poly : 54nm
New for 2009
Vo
lum
e
Years
Alpha
Tool
Beta
ToolTools for Pilot line
32nm (extendable to 22nm) M1 half-pitch capable Beta tools by end of 2011
Consortium Pilot Line Manufacturing
22nm (extendable to 16nm) M1 half-pitch capable tools
Development Production
450mm 32nm M1 half-pitchPilot Line Ramp
2010
2011
2012
2013
2014
2015
2016
Beta
Tool
Production
Tool
450mm Production Ramp-up Model[ 2009 Figure 2c A Typical Wafer Generation Pilot Line and Production “Ramp” Curve ]
Source: 2009 ITRS - Executive Summary Fig 2c
450mm Production Ramp-up Model[ 2009 ITRS Figure 2c A Typical Wafer Generation Pilot Line and Production “Ramp” Curve ]
Versus “Node”/actual contacted M1 and un-contacted Poly Half-Pitch alignment
2009 WAS
Work in Progress – Do Not Publish!
14
Technology Cycle Timing Compared to Actual Wafer Production Technology Capacity Distribution
* Note: The wafer production capacity data are plotted from the SICAS* 4Q data for each year, except 2Q data for 2009. The width of each of the production capacity bars corresponds to the MOS IC production start silicon area for that rangeof the feature size (y-axis). Data are based upon capacity if fully utilized.
Year
W.P.C.= Total Worldwide Wafer Production Capacity* Sources:SICAS
0.01
0.1
1
10
200620052004
W.P.C.
1999
W.P.C.
2000
W.P.C.
2001
W.P.C.
2002
W.P.C.
2003
W.P.C. W.P.C.
2007 2008 2009
W.P.C. W.P.C.
-
-
-
--
-
-
-
W.P.C. W.P.C.
-
-
-
Fea
ture
Siz
e (H
alf
Pitc
h) (m
) >0.7m
0.7-0.4m
0.4-0.3m
0.3- 0.2m
0.2- 0.16m
0.16-.12m
<0.08m
0.08-.12m
2008/09 ITRS: 2.5-Year Ave Cycle for DRAM
2-Year DRAM Cycle 3-Year DRAM Cycle ; 2-year Cycle Flash and MPU3-Year Cycle
2010 2013
= 2003/04 ITRS DRAM Contacted M1 Half-Pitch Actual = 2007/09 ITRS DRAM Contacted M1 Half-Pitch Target = 2009 ITRS Flash Uncontacted Poly Half Pitch Target = 2009 ITRS MPU/hpASIC Contacted M1 Half-Pitch Target
3-Year CycleAfter 2010 for
Flash; after 2013For MPU
Source: 2009 ITRS - Executive Summary Fig 3
2009 WAS
Work in Progress – Do Not Publish!
15
0.01
0.1
1
10
2006200520041999 2000 2001 2002 2003 2007 2008 2009
W.P.C.= Total Worldwide Wafer Production Capacity* Sources:SICAS
W.P.C.
W.P.C W.P.C.
W.P.C W.P.C.
W.P.C.
W.P.C W.P.C.
W.P.C.
W.P.C W.P.C.
>0.7m
0.7-0.4m
0.4-0.3m
0.3- 0.2m
0.2- 0.16m
0.16-.12m
<0.08m
0.08-.12m
<0.06m
Technology Cycle Timing Compared to Actual Wafer Production Technology Capacity Distribution
* Note: The wafer production capacity data are plotted from the SICAS* 4Q data for each year, except 2Q data for 2009. The width of each of the production capacity bars corresponds to the MOS IC production start silicon area for that rangeof the feature size (y-axis). Data are based upon capacity if fully utilized.
Year
Fea
ture
Siz
e (H
alf
Pitc
h) (m
)
2008/09 ITRS: 2.5-Year Ave Cycle for DRAM
2-Year DRAM Cycle 3-Year DRAM Cycle ; 2-year Cycle Flash and MPU3-Year Cycle
2010 2013
= 2003/04 ITRS DRAM Contacted M1 Half-Pitch Actual = 2007/09 ITRS DRAM Contacted M1 Half-Pitch Target = 2009 ITRS Flash Un-contacted Poly Half Pitch Target = 2009 ITRS MPU/hpASIC Contacted M1 Half-Pitch Target
3-Year CycleAfter 2010 for
Flash; after 2013For MPU
Source: 2009 ITRS - Executive Summary Fig 3
4Q09 SICAS Update ProposalFrom Furukawa-san/Japan
To IRC 3/28/10 (modified by AA)
Year