Without hash sorting, all O(n2)

combinations must be checked.

Hash Sorter - Firmware Implementation and an Application for the Fermilab BTeV Level 1 Trigger System

J. Wu, M. Wang, E. Gottschalk, G. Cancelo and V. Pavlicek,Fermilab, Oct. 2003

Hash Sorter

• Hash sorter logically stores data items (e.g. triplets) into bins derived from a key value (e.g. slope of the triplets).

• Each bin represents a range of the key value.

• Each writing or reading takes one memory access (one clock cycle in FPGA implementation).

Hash sorting ~

histogram booking

+ saving ID’s of the data items.

Data Items

Hash sorted Data Items

Internal Triplets

Hash Sorting for Triplet Matching Acceleration

External Triplets

With hash sorting, only these combinations need to be checked.

Hash sorted Internal Triplets according to their slopes

Hash sorted External Triplets according to their slopes

Hash Sorter

Triplet MatchingWithout Hash Sorting

Triplet MatchingWith Hash Sorting

The slopes of matching triplets must be approximately equal.

0

500000

1000000

1500000

2000000

0 2 4 6 8 10 12

Number of Interaction/Beam Crossing

seg_matchseg_match_hashtotal

0

500000

1000000

1500000

2000000

0 2 4 6 8 10 12

Number of Interaction/Beam Crossing

seg_matchseg_match_hashtotal

Timing Results

FPGA segment finders

Merge

Trigger decision to Global Level 1

Switch: sort by crossing number

track/vertex farm(~2500 processors)

30 station pixel detector

Firmware Implementation of Hash Sorter

External T

riplets

Internal Triplets

• Internal and external triplets are first found by the FPGA segment finders.

• Triplets data are sent through the switch.

• The nodes of the track/vertex farm match the internal and external triplets to form tracks for further trigger processes.

Buffer Manager

DSP

DSP

Pre-prototype of the Track/Vertex Farm Node

DS

P0

DS

P1

DS

P2

DS

P3

InBuff

DxBin

HashBlk

HashBlk

HashBlk

HashBlk

DSPSELS4STEPS

Silicon Usage: 1% 4 x 1%

Hash Sorter Added to Existing Buffer Manger (xc2v1000)

BTeV Level 1 Pixel Trigger

DIN DOUT

Index RAM

Pointer RAM

DATA RAM

COUNT

BEGIN

END The HashBlk Block (+ DATA RAM)

• Triplet data are hash sorted in the Buffer Manager parasitically.

• The hash sorted data are sent to the DSP daughter cards.

• DSP’s match the internal and external triplets faster with hash sorted data.

Pixel detector half-station

Multichip module50 m

400 m5 cm

1 cm

6 cm

10 cm

HDI flex circuitWire bonds

Sensor module

Readout module Bump bonds

Si pixel sensors

sensor module

5 FPIX ROC’s

128 rows x22 columns

14,080 pixels (128 rows x 110 cols)

380,160 pixelsper half-station

total of 23Million pixelsin the full pixel detector

b

p p

B-meson

BTeV Si Pixel Detector and Its Level 1 Detached Vertex Trigger

Fermilab

CZero

BTeV

Si-Pixel Detector

Tracks Detached from the Primary Vertex

Simulated B Event