Wireless Video StreamingWireless Video Streaming

Mikko Ruotsalainen

HUT

PapersPapers

”Performance of H.263 Video Transmission over Wireless Channels Using Hybrid ARQ,” H.Liu, and M. El Zarki, IEEE Journal on Selected Areas in Communications, Vol. 15, No. 9, Dec. 1997, pp. 1775-86

”Feedback-Based Error Control for Mobile Video Transmission,” B. Girod, and N. Farber, Proceedings of the IEEE, Vol. 87, No. 10, Oct. 1999, pp. 1707-23

”Wireless MPEG-4 Video Communication on DSP Chips,” M. Budagavi, W.R. Heinzelman, J. Webb, and R. Talluri, IEEE Signal Processing Magazine, Jan. 2000, pp. 36-53

Performance of H.263 Video Performance of H.263 Video Transmission over Wireless Transmission over Wireless Channels Using Hybrid ARQChannels Using Hybrid ARQ

Concatenated Hybrid ARQConcatenated Hybrid ARQ

two conventional hybrid ARQ schemes– type-I

parity bits for both error detection and error correction in every transmitted packet

if error can not be corrected, packet is rejected and retransmission is requested

– type-II erroneus packet is kept for future rather than discarded

like in type-I scheme redundancy bits are transmitted only when needed (more

and more redundancy is sent until errors can be corrected)

CH-ARQ– based on Reed-Salomon and rate-compatible punctured

convolutional (RCPC) codes– combines the advantages of both type-I and type-II

schemes certain error correction capability with every packet the information can be recovered from each transmission

or retransmission alone retransmitted packet contains redundancy bits, which

combined with previous transmitted packet, result powerful RS/convolutional concanated code

– employs three codes C0, C1 and C2

C0 is cyclic redundancy check (CRC) code used for error detection

C1 is RCPC code for error correction

C2, is half-rate invertible shortened Reed-Salomon code for both error detection and correction

– code rate at the RCPC can be selected according to the channel conditions

Coding using CH-ARQCoding using CH-ARQ

1. Using RS code form parity block P(D). (D,P(D)) is code word in C2.

2. k information (D) blocks are interleaved and CRC based on C0 is attached to interleaved blocks to form macroblock I.

3. I is encoded with RCPC encoder and information packet is transmitted to the receiver

4. If no ACK is received, states 2 and 3 are performed for parity blocks P(D) to form parity packet.

Decoding using CH-ARQDecoding using CH-ARQ

1. Decode using RCPC2. CRC check3. If no error is detected send ACK, else

deinterleave and store received information packet

4. Do 1 and 2 for parity packet.5. If no error is detected, invert parity packet to get

the information, else combine parity packet with information packet to form RS code

6. Error correction is performed on the RS code

Performance AnalysisPerformance Analysis

For the performance analysis Multistate Markov channel model (MSMC) is used to model the fading radio channel – Bit-error rate (BER) and SNR change over time – the channel quality at any instant depends on the

previous channel condition– model is constructed by partitioning the range of SNR

into multiple intervals– each state in MSMC correspond to one interval and is

characterized by particular BER

– probabilities for state transitions derived from the Rayleigh fading channel model

– assumptions: fading is slow, transtions happen only after packet transmission and state can change only to it’s neighboring states

Numerical results – CH-ARQ over MSMC modeled radio channel– RCPC rates 1, 4/5 and 4/8, Viterbi decoder– under a certain channel condition it is possible to find

optimal code rate that yields low RPER and high throughput

Simulation of H.263Simulation of H.263

CH-ARQ error control scheme is simulated in H.263 video transmission

Rayleigh fading simulator is used to simulate the radio channel (instead of MSMC used in numerical analysis)

average peak-signal-to-noise ratio (PSNR) and objective video qualitity assesment using grade point (GP)

for each channel SNR there is RCPC rate that maximizes visual quality (adaptive algorithm)

Feedback-Based Error Control for Feedback-Based Error Control for Mobile Video TransmissionMobile Video Transmission

Motion-Compansated Hybrid CodingMotion-Compansated Hybrid Coding two modes: INTRA and INTER coding

– INTRA: intraframe is coded with no reference– INTER: motion-compansated prediction is carried out

by estimating the motion between successive frames and the residual is intraframe code

H.263 coding standard– each picture is divided into macroblocks (MB)– each MB is either INTRA or INTER coded– in INTER mode one motion vector / MB– a fixed number of MB´s form group of block (GOB)– for low-bit rate acceptable image quality

Decoding the Erroneus Video Bit Decoding the Erroneus Video Bit StreamStream

error detection and resynchronization– a single bit error may cause loss of synchronization,

since variable length code (VLC) words are used– GOB headers are used as resynchronization points

(previous GOB discarded entirely)– errors can be detected using forward error correction

(FEC)– video decoder itself can detect errors (syntax

violations)

error concealment– the visual effect of errors is minimized using error

concealment techniques– simplest and most common approach is corrupted

pixels are replaced pixels from previous frame not very good approach when heavy motion

– motion vectors can be used for motion-compansated concealment

error propagation– errors remaining after the concealment propagate to

successive frames and stay visual for long time– decay of propagation determined by two effects

some blocks encoded in INTRA mode (stops propagation)

spatial filtering in motion-compensated predictor

Error Mitigation by FeedbackError Mitigation by Feedback

error tracking– uses INTRA mode for some MB´s to stop error

propagation– when decoder finds errors that can not be corrected it

sends NACK– when receiving NACK encoder calculates the error

distribution (using past motion vectors), and encodes next MB´s using INTRA mode

error confinement– motion compensated prediction within region, no error

propagation from region to another region– encoding efficiency suffers

reference picture selection– instead of coding with INTRA mode, use correctly

coded INTER –frames as reference– decoder uses either ACK or NACK, to inform how

succesfull the decoding has been (can GOB´s be used)– if encoder (doesn’t) receives NACK (ACK), it does not

use that GOB as reference to encode, but the last correctly decoded frame

Video Transmission over a Wireless Video Transmission over a Wireless DECT ChannelDECT Channel

Wireless MPEG-4 Video Wireless MPEG-4 Video Communication on DSP ChipsCommunication on DSP Chips

DSP processorsDSP processors

DSP processor features for wireless video communicators– low power consumption– Viterbi accelators– multiply-accumulate (MAC)– barrel shifters abd bit-manipulation support– various memory access modes for efficient data transfer – software reuse (time-to-market)

Architecture– processors have to be size-, cost- and power-efficient– usually DSP instruction sets support application

spesific instruction (MAC, Viterbi accelators)– memory-to-memory data transfer using direct memory

access (DMA)– zero overhead loops and conditional execution to avoid

flushing the pipeline – low-power DSP´s include IDLE or power-down modes

MPEG-4MPEG-4 pictures are coded either in INTRA (I-frame) or

INTER (P-frame) mode (similar to H.263) basic unit is macroblock 16x16 pixels no required pattern for I- and P-frames individual macroblocks within P-frame can be

INTRA-coded image or the residual is split into 8x8 blocks and

DCT is calculated for these for INTER coded macroblocks motion

information is also transmitted

error resilience tools included in MPEG-4– resynchronization markers

when ever error is detected, decoder jumps to next marker to synchronize

– data partioning– header extension codes (HEC)– reversible variable length codes (RVLC)

ImplementationImplementation

Issues in implementing video coding– memory allocation: on-chip memory is faster

than off-chip memory, but very limited– data transfer: management of data transfer from

off-chip to on-chip memory (DMA)– DSP –friendly algorithms: processor may

support instructions that favor some algortihms– development tools: compilers (C instead of

assembler), debugging tools

Performance of the MPEG-4 Performance of the MPEG-4 implementationimplementation

simple-profile SQCIF encoder and decoder on 40 MHz TMS320C541 (40 MIPS)– encoder 1 f/s and decoder 20 f/s of simple

talking-head sequence – more powerfull DSP´s needed to implement

both decoder and encoder– more powerfull DSP´s needed to support higher

resolutions

ex. low power C55x DSP platform offer 288 to 600 MIPS (144 to 200MHz)