WinVLSI: A Free Windows CAD Framework for Mixed Full-Custom … · 2014-09-30 · Universitat...

Universitat Autonoma de Barcelona - Departament d’Informatica - Unitat de Microelectronica

WinVLSIA Free Windows CAD Framework for

Mixed Full-Custom VLSI Design

CNM25 Kit Edition

Francesc Serra-Graells

[email protected]

CENTRE NACIONAL DE MICROELECTRÒNICA IMB Centre Nacional de Microelectronica - Institut de Microelectronica de Barcelona

Index 2/54

I Objectives

I Schematic and Layout Capture

I Electrical an Physical Verification

I Numerical Simulation

I Complete Tutorials

• V /I Conversion Based on a New CMOS Low-Voltage CCII+

• Slew-Rate Optimization for a Miller OpAmp

• A First-Order Low-Pass Switched-Capacitor Filter

• A Third-Order Low-Pass Σ∆ Modulator for ADCs

I Conclusions

WinVLSI: A Free Windows CAD Framework for Mixed Full-Custom VLSI Design F.Serra-Graells

Objectives 3/54

I Wanted features:

• Full-Custom Design

• Mixed Simulation

• Circuit Optimization

• Easy to use

• Freeware

• Windows Platforms

I Tested tools:

Electric, www.staticfreesoft.com

Magic, vlsi.cornell.edu/magic

XCircuit, xcircuit.ece.jhu.edu

WinSpice, www.winspice.com

Microwind2, intrage.insa-tlse.fr/˜etienne

Kic, www.srware.com

and many others. . .

SpecsSynthesis

Prototype

Schematic CaptureCNM25 Technology

Extraction+ERC

M1 D G S MODN W= L= M=

Simulation

Phyisical Design

DRC

Extraction+ERC

M1 D G S MODN W= L= M=

CPAR 1 2

Simulation

==?

LVS

Codification

Foundry Processing

LASI

SPICE OPUS

Available Devices

Nominal, Cornerand MismatchingModel Parameters

Table of Layers

Design Rules

VerticalConnectivity

ParasiticModel ParametersParasiticModel Parameters

Conversion Table


Objectives 4/54

I Main parts:

LASI, members.aol.com/lasicad

SPICEOPUS, fides.fe.uni-lj.si/spice

cir2sp3, custom parser for netlist interface

I Target technology:

2.5µm 2P 2M CMOS (CNM25), www.cnm.es

I Homepage of WinVLSI:

www.cnm.es/˜pserra/winvlsi

I The developed Design Kit:

WinVLSI

LASI SPICEOPUScir2sp3

Schematic/Layout Editor,DRC, Extractor, LVS andSpice Netlister.

Spice3F5 Simulator,XSpice and Optimizer.

CNM25 TechnologyTutorials


Objectives 5/54

I Easy installation:

1 Download all required files from WinVLSI homepage.

2 Install WinVLSI kit files (default path is c:\), resulting:

WinVLSI\x.x\bin Kit console and utilities

\cnm25\doc Manual in PDF

\template CNM25 default starting directory

\tutor Complete design examples

3 Install LASI files (default path is c:\LASI).

4 Install SPICE OPUS files (default path is c:\spiceopus).

5 If required, correct path references in bin\winvlsi.bat and create a shortcut

for a direct access to: lasi7, lasickt7, lasidrc7, spice3 and cir2sp3.

6 Finally, READ THE MANUAL!.


Objectives 6/54

I Typical working directory:

projectX\ lasi7.usf LASI editor configuration for CNM25.

lasickt.usf LASI extractor configuration for CNM25.

lasidrc.usf LASI DRChecker configuration for CNM25.

cells7.dbd List of cells in projectX.

loadbkup.tlc LASI backup for last loaded cell.

undobkup.tlc LASI backup for undo’s.

cnm25.drc CNM25 design rules.

cnm25f.drc CNM25 fast design rules (orthogonal only).


Objectives 6/54


projectX\ vsource sch.tlc Basic X/SPICE primitives and subcircuits.

isource sch.tlc

vcvs sch.tlc

res sch.tlc

gnd sch.tlc

inv sch.tlc

...


Objectives 6/54


projectX\ cellnameY.tlc Cellname file.

cellnameY.cir Extracted netlist for generic SPICE.

cellnameY.nod Extracted node file for LVS.

cellnameY ruleW.pcx PCX bitmap of DRC errors for Design Rule W.

cellnameY.tld Optional transportable LASI drawing format.

...


Objectives 6/54


projectX\ sim\cnm25typ.mod2 CNM25 typical SPICE Level=2 model parameters.

cnm25typ.mod3 CNM25 typical SPICE Level=3 model parameters.

cnm25mc.txt CNM25 Technology Mismatching parameters.

environment SPICE OPUS config paths.

cellnameY.sp3 SPICE3 compatible netlist from cellnameY.cir.

testZ.sp3 SPICE3 Nutmeg test script for cellnameY.sp3.

testZ.dat ASCII/binary simulation data.

testZ.eps Encapsulated PostScript simulation graphics.


Index 7/54

I Objectives









I Conclusions


Schematic and Layout Capture 8/54

I LASI drawing tool: lasi7

Cell Name

Cell Hierarchical RankDrawing Directory

Toolbar

Resident Command

CoordinatesNumbered Layers/Layer Table Mode

FlagsObjects SummaryGrid DefaultObject

DefaultLayer

Menu 1/2

MenuSelector

Layout / ScehmaticDrawing Window



I LASI basic elements for sch & lyt:

opened0Wdth>

Box

opened0Wdth=

closed0Wdth=

TextPoly/Path

Parameter sch lyt Units

wGrid 10 0.25 µm

dGrid 10 1 µm

tSiz 7.5 3.75

Wdth 0 µm

I LASI Layer and object selection



I WinVLSI symbol library (cnm25\tutor\basic\all_sch.tlc):



I WinVLSI design rule examples (cnm25\tutor\basic\cnm25drc_lyt.tlc):


Index 12/54

I Objectives









I Conclusions


Electrical an Physical Verification 13/54

I WinVLSI labeling layers for SPICE extraction: NAME PIN PARM



I LASI SPICE macro-extraction and Electrical Rule Checker (ERC) tool: lasickt7

Startsprocess!

to viewresults

choose the proper view!

*.tlc −→ *.cir & *.nod



I LASI Design Rule Checker (DRC) tool: lasidrc7

Starts DRC!summaryof results

errorviewer

selection ofwhole circuit area



I Example for a DRC error report:

Errorlocation

Design Ruledescription

Displayed bounding box

Zoom

Pan



I LASI Layout Versus Schematic (LVS) tool: lasickt7

Layout node file

Scehmatic node file

Common cellname

Output report

Start process!

I Typical LVS report:

*** Node Compare Error List made by LASICKT

Comparing CCII_LYT.NOD to CCII_SCH.NOD

Comparing CCII_SCH.NOD to CCII_LYT.NOD

Finished ... 0 Errors


Index 18/54

I Objectives









I Conclusions


Numerical Simulation 19/54

I SPICEOPUS Analog/Digital multi-level + optimizer engine:

Core

SPICE3

(UC.Berkeley)

Event-Driven

Algorithm

Code Models

+

Node TypesLib

XSPICE (Georgia Tech Research Institute)

SPICE OPUS (CACD Group at U.Ljubljana)

Optimization

Tool

Nutmeg

User

Interface

C CompilerMS Visual C++

Linux/Solaris GCC

User



I SPICE3 Nutmeg interface:



I WinVLSI Netlist interface:

Generic SPICE(*.cir)

Specific SPICE3(*.sp3)

CNM25 Device-ModelParameters(*.mod)

MixedResults(*.dat)

Schematic (*_sch)

cir2sp3

LASI

SPICEOPUS

User Code-ModelParameters(*.cm)

title test

.include *.mod

.include *.cm

.include *.sp3

.control<test script>.endc

.end

CNM25 MismatchingParameters(*.mod)



I SPICE3 scripting for signals:

plotname.v(node:subckt) or plotname.i(element:subckt)

assignment let <v name> = <expression>

building let <v name> = (<first>;...;<last>)

element values <v name>[<m>] or <v name>[<m>][<n>]

subvector values <v name>[<m>] for multidim.

subrange values <v name>[<lower>,<upper>]

interpolation <v name>[%<non integer index>]

arithemric substitution <expression>e.g.: .control

save all

op

tran 1u 1m

let vrms = sqrt(sum((tran1.v(out)[501,1000]−op1.v(out))^2)/500)echo Output Amplitude = $&vrms [Vrms]

.endc



I SPICE3 scripting for parameters:

@instance:subckt[parameter] for device parameters.

@@model[parameter] for model card parameters.

@@@variable for simulator variables (e.g. temp).

e.g.: .control

foreach ccomp 1p 2p 5p ...

let @cl.xopamp[c] = $ccomp

save v(out)

tran 1u 1m

end

plot tran1.v(out) tran2.v(out) ...

.endc



I XSPICE Pre-defined code-models and node-types:

a<instance name> <node1> ... <nodeN> <model name>

.model <model name> (<parameter name> = <value>)

Code Model Description

d dt differentiator block

gain a simple gain block

hyst hysteresis block

limit limit block

mult multiplier block

oneshot one-shot

s xfer s-domain transfer function block

real delay a z ** -1 block working on real data

adc bridge analog-to-digital converter node bridge

dac bridge digital-to-analog converter node bridge

d to real node bridge from digital to real with enable

real to v node bridge from real to analog voltage

Node type Description

analog Built-in, used for analog circuits

d 3-state 4-strength digital data

int integer valued data

real real valued data

Code Model Description

d and digital n-input and gate

d buffer digital one-bit-wide buffer

d dff digital d-type flip flop

d fdiv digital frequency divider

d open c digital one-bit-wide open-collector buffer

d pulldown digital pulldown resistor

d ram digital random-access memory

d source digital signal source

d state digital state machine



I SPICEOPUS optimization tool: optimize

1 Define parameters that can vary along optimization:

optimize parameter <par identifier> element <instance name>......parameter <par name> low <minimum> high <maximum> initial <guess>

2 Declare the evaluation analysis:

optimize analysis <analysis identifier> <definition>

3 List all constrains and cost function:

optimize implicit <par identifier> <expression>

optimize cost <expression>

4 Select optimization method:

optimize method <method name> <parameters>

5 Perform optimization and select results:

optimize and setplot optimize

parameter list of final parameter values

cost cost versus iteration

<par name> paramter value versus iteration


Index 26/54

I Objectives









I Conclusions


Complete Tutorials: V /I Conversion Based on a New CMOS Low-Voltage CCII+ 27/54

I Circuit description:

IY

VX

Iout

=

0 0 0

1 0 0

0 +1 0

0

Iin

Vout

Iin =Vin − VX

R

Iout =Vin

R

Iout

Vout

X

Y

Z

Iin

Vin

VDD

VSS

R

M4

IX

M6

M1

M3

VY

M5

M2

M10

VX

IZ



I Full schematic of the complete V /I converter (i.e. lasi7):



I SPICE macro-extraction (i.e. lasickt7 + cir2sp3):

.SUBCKT CCII SCH Y X Z IBIAS VDD VSS

M7 X IBIAS VDD VDD MODP W=6u L=18u M=1

M4 2 X 3 VSS MODN W=48u L=6u M=1

M3 1 Y 3 VSS MODN W=48u L=6u M=1

M9 IBIAS IBIAS VDD VDD MODP W=6u L=18u M=1

M10 3 1 VSS VSS MODN W=16u L=6u M=4

M2 2 2 VDD VDD MODP W=6u L=18u M=1

M1 1 2 VDD VDD MODP W=6u L=18u M=1

CCOMP 1 VSS CPOLY W=92u L=92u

M5 X X 3 VSS MODN W=48u L=6u M=1

M8 Z IBIAS VDD VDD MODP W=6u L=18u M=1

M6 Z X 3 VSS MODN W=48u L=6u M=1

MD1 3 Y 3 VSS MODN W=48u L=6u M=1

MD2 3 X 3 VSS MODN W=48u L=6u M=1

MD3 3 X 3 VSS MODN W=48u L=6u M=1

.ENDS



I SPICE macro-extraction (i.e. lasickt7 + cir2sp3):.subckt ccii sch y x z ibias vdd vss

m7m1 x ibias vdd vdd modp w=6u l=18u

m4m1 2 x 3 vss modn w=48u l=6u

m3m1 1 y 3 vss modn w=48u l=6u

m9m1 ibias ibias vdd vdd modp w=6u l=18u

m10m1 3 1 vss vss modn w=16u l=6u




m2m1 2 2 vdd vdd modp w=6u l=18u

m1m1 1 2 vdd vdd modp w=6u l=18u

ccomp 1 vss cpoly w=92u l=92u

m5m1 x x 3 vss modn w=48u l=6u

m8m1 z ibias vdd vdd modp w=6u l=18u

m6m1 z x 3 vss modn w=48u l=6u

md1m1 3 y 3 vss modn w=48u l=6u

md2m1 3 x 3 vss modn w=48u l=6u

md3m1 3 x 3 vss modn w=48u l=6u

.ends



I SPICE simulation (i.e. spice3):

* VI Converter circuit: Large Signal Static Input Analysis

.include cnm25typ.mod2

.include viconvert sch.sp3

.control

destroy all

delete all

dc vinput -1.5 1.5 3m

let iout=-dc1.i(vout)

let rceq=1/deriv(-dc1.i(vout))

let rin=deriv(dc1.v(x))/deriv(-dc1.i(vinput))

print rceq[500]

print rin[500]

plot iout ylimit -5u 5u xlimit -0.5 0.5 xlabel ’Input Voltage...

plot rceq rin ylog ylimit 1e3 1e6 xlimit -0.5 0.5 xlabel ...

.endc

.end




* VI Converter circuit: Large Signal Static Output Analysis



.control

destroy all

delete all

dc vout -1.5 1.5 3m

let iout=-dc1.i(vout)

let rout=1/deriv(-dc1.i(vout))

print rout[500]

plot iout ylimit -5u 5u xlabel ’Output Voltage [V]’...

plot rout ylog ylimit 1e3 10e6 xlabel ’Output Voltage...

.endc

.end




* VI Converter circuit: Small Signal Spectral Transfer Analysis...

.control

foreach csweep 0 1p 2p 5plet @cin[capacitance] = $csweep

save all

ac dec 50 1e4 1e7

endlet gm0pF=mag(-ac1.i(vout))

let gm1pF=mag(-ac2.i(vout))...

plot 1e6*gm0pF 1e6*gm1pF 1e6*gm2pF 1e6*gm5pF loglog xlimit...

set units=degrees

let gm0pF=phase(-ac1.i(vout))

let gm1pF=phase(-ac2.i(vout))...

plot gm0pF gm1pF gm2pF gm5pF xlog xlimit 1e3 1e7 xlabel...

.endc

.end




* VI Converter circuit: Small Signal Spectral Noise Analysis



.control

noise v(outnoise) vinput dec 100 100 100k

setplot noise1

plot sqrt(onoise spectrum) loglog xlimit 100 1e5...

setplot noise2

let inout=sqrt(onoise total)

let vnin=inout*100e3

echo Integrated Output Noise Current in Arms from 100Hz to...

print inout

echo Equivalent Input Noise Voltage in Vrms from 100Hz to...

print vnin

.endc

.end




* VI Converter circuit: Large Signal Spectral Transfer Analysis...

.control

ac dec 50 100e3 10e6

foreach vain 0.05 0.1 0.2let @vinput[pulse] = (0;$vain;0;0.1n;0.1n;0.5u)

save all

tran 0.02u 10u 0 0.02u

endplot -10*tran1.v(vin) 1e6*tran1.i(vout) vs 1e6*tran1.time...

setplot tran1

linearize i(vout) v(vin)...

setplot tran4

spec 100e3 10e6 100e3 i(vout) v(vin)...

plot 1e6*mag(-ac1.i(vout)) vs ac1.frequency...

.endc

.end




* VI Converter circuit: Large Signal Harmonic Distortion Analysis...

.control

foreach vain 0.10 0.15let @vinput[sin]=(0;$vain;10e3;0;0)

save all

tran 1u 2m 1m 1u

endsetplot tran1

let iout10=-i(vout)

setplot tran2

let iout15=-i(vout)

plot 1e6*tran1.iout10 1e6*tran2.iout15 vs time*1e3 xlabel...

setplot tran1

fourier 10k iout10...

.endc

.end




* VI Converter circuit: Technology Mismatching Offsets...

.control

op

let Avto=32e-3*1e-6*unitvec(vector(1))

let mvtoA=@@modp1[vto]...

let svtoA=Avto/sqrt(@m1m1[l]*@m1m1[w])...

repeat 1000let @@modp1[vto]=gaussian(op1.mvtoA,op1.svtoA,0.001)

let @@modp2[vto]=gaussian(op1.mvtoA,op1.svtoA,0.001)...

op

let op1.result=(op1.result;i(vout))

endlet mn=mean(op1.result)*@rconv[resistance]*1e3

let std=sqrt(mean((op1.result-mean(op1.result))ˆ2))*@rconv[resistance]*1e3

echo Equivalent Input Offset = $&mn mV +/- $&std mV

.endc

.end




-100 -50 0 50 1000

1

2

3

4

5

6victest7.sp3

Equivalent Input Offset [mV]

Sam

ple

s [%

]

= 10mV

¹

¾ §

= 1mV<



I Physical design and verification (i.e. lasi7+lasidrc7+lasickt7):



I Physical design and verification (i.e. lasi7+lasidrc7+lasickt7):

*main circuit ccii lyt





...

* parasitic caps

c vss vss 0 0.131821pf

c 3 3 0 0.0580808pf

c y y 0 0.0498004pf

c x x 0 0.118084pf

c 1 1 0 0.027746pf

c 2 2 0 0.0359047pf

c z z 0 0.0262004pf

c vdd vdd 0 0.167788pf

c ibias ibias 0 0.0320506pf



Parameter Pre-Layout Post-Layout Units

Voltage Supply (±VDD/SS) ±1.5 ±1.5 V

Input Capacitance (Cin) 1 1 pF

Conversion Resistance (R) 100 100 KΩ

Temperature 25 25 C

Quiescent Current 9.7 9.7 µA

V /I Static Transconductance 1/101.8 1/101.8 mS

Input Voltage Range ±200 ±200 mV

Current Range ±2 ±2 µA

Output Voltage Range ±0.8 ±0.8 V

Output Static Resistance (Rout) >3 >3 MΩ

Signal Bandwidth (−3dB) 2.7 2.5 MHz

Equivalent Input Noise 4 4 mVrms

Max. Signal to Noise Ratio 31 31 dB

THD (Vin = 300mVpp at 1KHz) 0.6 0.6 %

Equivalent Input Offset (σ) ±20 ±20 mV


Index 39/54

I Objectives









I Conclusions


Complete Tutorials: Slew-Rate Optimization for a Miller OpAmp 40/54

I Circuit description:

+

-

Vin+

Vin-

VDD

VSS

VoutM2

M8

M1Vin-

M3 M4M9 M6

M7

Ccomp

M5

Vin+

Vout

VSS

VDD

(a) (b)

+

-V

in

Vout

+

Cload

90%

10%

2

3

Output Voltage [V]

SR+ SR-

Time [ s]¹



I Defining the optimize procedure (i.e. spice3):

Parameters: Current sources (M8:M7:M5), initial (1:6:4), between (1:9:1) and (1:1:9)

optimize parameter 0 element m7 parameter w low 12u high 108u initial 72u

optimize parameter 1 element m5 parameter w low 12u high 108u initial 48u

Analysis:

optimize analysis 0 op

optimize analysis 1 let idd=-(vdd#branch)*1e6

optimize analysis 2 tran 5n 5u

optimize analysis 3 let vout=v(vout)

optimize analysis 4 let tdn1=max((vout gt 2.90V)*time)*1e6

optimize analysis 5 let tdn2=max((vout gt 2.10V)*time)*1e6

optimize analysis 6 let srneg=0.8V/(tdn2-tdn1)

optimize analysis 7 let tup1=tdn2-sum((vout gt 2.10V))*5e-3

optimize analysis 8 let tup2=tdn1-sum((vout gt 2.90V))*5e-3

optimize analysis 9 let srpos=0.8V/(tup2-tup1)

optimize analysis 10 print srpos

optimize analysis 11 print srneg



Constrains: Constant-power condition ±5µA

optimize implicit 0 abs(op2.idd-op1.idd) lt 5

Cost Function: Minimum Difference Rule?

optimize cost abs(srpos-srneg)

Method and Options:

optimize options number of iterations 50

optimize method complex size 2.5u

Starting and Collecting:

optimize

setplot optimize

plot m7 w*1e6 m5 w*1e6 ylimit 0 120 xlabel ’Iteration’ ylabel ’M7 & M5 Width [um]’

set nobreak

set noprintheader

set noprintindex

set width=32

print m7 w*1e6 m5 w*1e6 > results.dat



I Optimization results (i.e. spice3):

IDD SR+ SR−[µA] [V/µs] [V/µs] M8:M7:M5 round(M8:M7:M5)

initial 100.6 2.86 4.85 10:60:40 1:6:4

105.1 1.52 1.54 10:10:88 1:1:9

104.5 2.46 2.46 10:18:81 1:2:8

105.2 3.90 3.90 10:37:63 1:4:6

98.9 3.40 3.40 10:28:65 1:3:7

optimize cost abs(srpos-srneg)





initial 100.6 2.86 4.85 10:60:40 1:6:4

104.9 3.81 4.44 10:47:54 1:5:5

105.3 3.14 4.85 10:59:46 1:6:5

105.4 2.91 5.00 10:69:40 1:7:4

105.4 3.81 4.44 10:47:54 1:5:5

optimize cost 1/(srpos+srneg)





initial 100.6 2.86 4.85 10:60:40 1:6:4

105.4 4.00 4.32 10:44:57 1:4:6

103.5 3.90 4.32 10:42:57 1:4:6

optimize cost 1/srpos+1/srneg


Index 44/54

I Objectives









I Conclusions


Complete Tutorials: A First-Order Low-Pass Switched-Capacitor Filter 45/54

I Stray-insensitive topology [Mosc84]:

KC

+

-

Vout

C

CVin

ÁÁÁ

Á

Á

Á Á

f−3dB ' fs

(2K + 1)πf−3dB ¿ fs

I Mixed and multi-level schematic:

.model dac dac bridge (out low=0 out high=5)

.model adc adc bridge (in low=0.3 in high = 3.5)

.model inverter d inverter (rise delay=1.2e-6 fall delay=1.2e-6)

.model nand d nand (rise delay=1.2e-6 fall delay=1.2e-6)

.model vlimit limit (gain=1000 out lower limit=-2.5 out upper limit=2.5 limit range=1)



I Transistor versus Functional:

anand [d3 dctrl] d1 nand2.model nand2 d_nand (rise_delay = 1.2e-6+ fall_delay = 1.2e-6)

xnand a3 actrl a1 nand2.subckt nand2 a b yvdd 99 0 5mna 1 a 0 0 modn w=6e-6 l=6e-6mnb y b 1 0 modn w=6e-6 l=6e-6mpa y a 99 99 modp w=6e-6 l=6e-6mpb y b 99 99 modp w=6e-6 l=6e-6.ends nand2



I Complete mixed-mode and multi-level simulation (e.g. fs=125KHz and K=10):

* Steady-State Analysis


.include cm.mod

.include sc sch.sp3

.options gmin=1e-12

.control

foreach fin 2k 5k

let @vin[sin]=(2.5;0.5;$fin;10u)

tran 0.08u 1m 500u

endplot tran1.v(vout) tran2.v(vout) vs time*1e3

.endc

.end

∣∣∣∣H(f1)

H(f2)

∣∣∣∣2

=(f2/f−3dB)

2 + 1

(f1/f−3dB)2 + 1

'(

0.6Vpp

0.3Vpp

)2

f−3dB ' 1.7KHz ↔ 1.9KHz (theory)


Index 48/54

I Objectives









I Conclusions


Complete Tutorials: A Third-Order Low-Pass Σ∆ Modulator for ADCs 49/54

I Single-loop topology [Teme94]:

Vin 1

¿1

1¿2

1¿3

DAC

Vtun

D Q

Dout

Integrators Quantizer S/H

VCO

Optimal parameters [Marq98]:

1

τ1= 0.2fs

1

τ2,3= 0.5fs

fs.= 1024KHz

I Mixed and multi-level schematic:

.model int1 int (in offset=0 gain=205k out lower limit=0 out upper limit=5 limit range=100m out ic=0)

.model quant adc bridge (in low=2.49975 in high=2.50025 rise delay=10n fall delay=10n)

.model clkgen d osc (cntl array=[0 1] freq array=[0 1.024e6] duty cycle=0.5 init phase=0 rise delay=10n fall delay=10n)



I Playing with the modulator order. . .

FC-6dB@4KHz input

-60dB/dec

FC-6dB@4KHz input

-40dB/dec

order=3 order=2



I . . . and the oversampling ratio:

FC-6dB@4KHz input FC-6dB@4KHz input

OSR=64 OSR=32



I Quantifying second-order effects:

+

-

G(DC) SR+/-

G(DC)=60dB and SR±=10V/µs

THD 3%=

G(DC)=20dB and SR±=10V/µs


Index 53/54

I Objectives









I Conclusions


Conclusions 54/54

I A free environment for VLSI teaching in Windows platforms

I Configurable for most technologies

I Mixed analog and digital native simulation

I Functional/block/transistor-level schematics

I Practical examples and tutorials available

I Also covering full-custom design and circuit optimization


WinVLSI: A Free Windows CAD Framework for Mixed Full-Custom … · 2014-09-30 · Universitat...

Documents

Transcript of WinVLSI: A Free Windows CAD Framework for Mixed Full-Custom … · 2014-09-30 · Universitat...