wiki.gsi.de€¦ · AXIS ETRAX 100LX Designer's Reference (February 9, 2006) i Contents 1...

AXIS ETRAX 100LXDesigner’s Reference

A X I S E T R A X 1 0 0 L X D e s i g n e r ’ s R e f e r e n c e ( F e b r u a r y 9 , 2 0 0 6 )

Axis Communications AB cannot be held responsible for any technical ortypographical errors, and reserves the right to make changes to this manual and to theproduct without prior notice. If you do detect any inaccuracies or omissions, pleaseinform us at:

E-mail: [email protected]

Axis Communications ABEmdalavägen 14SE-223 69 Lund, SwedenPhone:+46 46 272 1800Fax: +46 46 13 61 30

Copyright © Axis Communications AB

A X I S E T R A X 1 0 0 L X D e s i g n e r ’ s R e f e r e n c e ( F e b r u a r y 9 , 2 0 0 6 )

Contents

1 Introduction ............................................................................................................11.1 Overview.............................................................................................................................. 11.2 Features................................................................................................................................ 21.3 Functional Block Diagram ................................................................................................... 3

2 RISC CPU ...............................................................................................................52.1 Registers............................................................................................................................... 52.2 Flags and Condition Codes .................................................................................................. 62.3 Data Organization in Memory............................................................................................. 72.4 Instruction Format............................................................................................................... 82.4.1 Addressing Modes ......................................................................................................... 102.4.2 Data Transfers .............................................................................................................. 122.4.3 Arithmetic Instructions ................................................................................................. 132.4.4 Logical Instructions ....................................................................................................... 132.4.5 Shift Instructions .......................................................................................................... 142.4.6 Bit Test Instructions ..................................................................................................... 142.4.7 Condition Code Manipulation Instructions .................................................................. 142.4.8 Jump and Branch Instructions ...................................................................................... 152.4.9 No Operation Instruction ............................................................................................. 152.5 MMU Support................................................................................................................... 162.5.1 Overview ...................................................................................................................... 162.5.2 Protected Registers and Flags ........................................................................................ 162.5.3 Transition Between Operation Modes .......................................................................... 172.5.4 Bus Fault Sequence ....................................................................................................... 172.5.5 Format of the CPU Status Record ................................................................................ 182.6 Integral Read-Write Operations ......................................................................................... 192.7 Interrupts ........................................................................................................................... 192.7.1 NMI ............................................................................................................................. 202.8 Software Breakpoints ......................................................................................................... 202.9 Hardware Breakpoint Mechanism...................................................................................... 20

3 Single step .............................................................................................................213.1 General .............................................................................................................................. 213.2 Programming Considerations............................................................................................. 21

4 Memory Management Unit ...................................................................................234.1 MMU Memory Areas ........................................................................................................ 244.1.1 Kernel/User Address Space ............................................................................................ 244.1.2 Kernel Address Space .................................................................................................... 244.2 Translation Lookaside Buffer ............................................................................................. 264.2.1 TLB Memory Sets ......................................................................................................... 264.2.2 TLB Entries .................................................................................................................. 284.2.3 TLB Register Interface .................................................................................................. 294.2.4 Virtual Address from the CPU ...................................................................................... 294.2.5 MMU Exceptions ......................................................................................................... 294.3 MMU Registers ................................................................................................................. 324.4 MMU Test Mode .............................................................................................................. 334.5 Example of Virtual Memory Configuration ....................................................................... 34

A X I S E T R A X 1 0 0 L X D e s i g n e r ' s R e f e r e n c e ( F e b r u a r y 9 , 2 0 0 6 ) i

Contents

5 Bus Interface .........................................................................................................375.1 Data Bus ............................................................................................................................ 375.2 Bus Interface Registers ....................................................................................................... 375.3 Address and Chip Selects ................................................................................................... 385.4 Internal Bus Arbitration ..................................................................................................... 385.5 Bus Width, Cycle Timing and Wait States......................................................................... 395.6 Memory Timing ................................................................................................................ 415.7 Write Modes ...................................................................................................................... 415.7.1 Normal and Extended Write Mode .............................................................................. 415.7.2 Bytewise and Common Write Enable Mode ................................................................. 415.8 External Interrupt Acknowledge......................................................................................... 425.9 Access to Internal I/O ........................................................................................................ 425.10 Wait Input and Bus Cycle Rerun ....................................................................................... 425.11 DRAM Interfaces............................................................................................................... 435.12 Asynchronous DRAM Interface ......................................................................................... 435.12.1 Connecting the Asynchronous DRAM Banks ............................................................... 445.12.2 Asynchronous DRAM Bank Configuration .................................................................. 475.13 Synchronous DRAM Interface ........................................................................................... 495.13.1 Power up and initialization ........................................................................................... 515.13.2 Power save mode ........................................................................................................... 525.13.3 100 MHz mode ............................................................................................................ 525.13.4 DDR mode ................................................................................................................... 535.13.5 Connecting the Synchronous DRAM banks ................................................................. 535.13.6 Synchronous DRAM Bank Configuration .................................................................... 54

6 Bootstrap Methods ................................................................................................576.1 Bootstrap Methods............................................................................................................. 576.1.1 Normal Bootstrap ......................................................................................................... 576.1.2 Serial Bootstrap ............................................................................................................. 576.1.3 Network Bootstrap ....................................................................................................... 576.1.4 Parallel Bootstrap .......................................................................................................... 58

7 DMA .....................................................................................................................597.1 DMA Operation ................................................................................................................ 597.1.1 Overview of the ETRAX 100LX DMA Architecture ..................................................... 597.1.2 Data Transfer ................................................................................................................ 607.2 The DMA Channels .......................................................................................................... 617.3 DMA Registers, Linked Lists, and Descriptor Format........................................................ 637.3.1 DMA Registers ............................................................................................................. 637.3.2 DMA Linked Lists ........................................................................................................ 657.3.3 DMA Descriptor Format .............................................................................................. 667.4 DMA Registers, Linked Lists, and Descriptor Format for USB .......................................... 687.4.1 DMA Registers for USB ............................................................................................... 687.4.2 DMA Linked Lists for USB .......................................................................................... 697.4.3 DMA Descriptor Format for USB ................................................................................ 707.5 DMA Interrupt .................................................................................................................. 757.6 DMA Transfer/Setup Examples ......................................................................................... 75

i i A X I S E T R A X 1 0 0 L X D e s i g n e r ' s R e f e r e n c e ( F e b r u a r y 9 , 2 0 0 6 )

Contents

7.6.1 Initiate and Setup a DMA Transfer ............................................................................... 767.6.2 Reset DMA Channel .................................................................................................... 767.6.3 Initiating Linked List .................................................................................................... 777.6.4 Start a DMA Transfer ................................................................................................... 777.6.5 Restart a DMA Transfer ............................................................................................... 777.6.6 Hold DMA Temporarily and Continue Later ............................................................... 787.7 Memory to Memory DMA ................................................................................................ 787.8 External DMA Channels.................................................................................................... 797.8.1 External DMA Configuration ....................................................................................... 807.8.2 External DMA Address ................................................................................................. 807.8.3 Initialization ................................................................................................................. 807.8.4 Request/Acknowledge Signaling .................................................................................... 817.8.5 Start and Stop of the Transfers ...................................................................................... 827.8.6 Transfer Counter .......................................................................................................... 827.8.7 External DMA Interrupts .............................................................................................. 82

8 Universal Serial Bus ..............................................................................................838.1 Principle of Operation ....................................................................................................... 848.1.1 Basic Architecture of the USB Interface ........................................................................ 848.1.2 Modes of Operation of the USB Interface ..................................................................... 848.2 Operational States of the USB Controller .......................................................................... 858.3 USB Registers .................................................................................................................... 868.3.1 Register Access Timing ................................................................................................. 868.3.2 USB Mode Registers ..................................................................................................... 868.4 USB Host mode................................................................................................................. 888.4.1 USB Controller Commands in Host Mode ................................................................... 898.4.2 USB Port (Root Hub) Commands in Host Mode ......................................................... 908.5 USB Data Structures in Host Mode................................................................................... 918.5.1 Transfer Frames ............................................................................................................ 918.5.2 DMA Descriptors ......................................................................................................... 938.5.3 Endpoint Table in Host Mode ...................................................................................... 998.5.4 Host Mode Interrupts ................................................................................................. 1008.6 Device Mode.................................................................................................................... 1028.6.1 USB Controller Commands in Device Mode .............................................................. 1028.6.2 USB Port (Root Hub) Commands in Device Mode .................................................... 1038.6.3 USB Data Structures in Device Mode ......................................................................... 1038.6.4 EP Table in Device Mode ........................................................................................... 1058.6.5 Device Mode Interrupts .............................................................................................. 1068.7 Physical Interface ............................................................................................................. 1078.7.1 Data Transmission ...................................................................................................... 1078.7.2 Power Management .................................................................................................... 1078.7.3 Hardware Reset ........................................................................................................... 1078.8 Procedures ....................................................................................................................... 1088.8.1 Configuring the USB Interface for Host Mode ........................................................... 1088.8.2 Starting and Stopping the Host Mode ........................................................................ 1088.8.3 Starting and Stopping Traffic in Host Mode ............................................................... 1088.8.4 Managing EP Descriptor Lists in Host Mode ............................................................. 109

A X I S E T R A X 1 0 0 L X D e s i g n e r ' s R e f e r e n c e ( F e b r u a r y 9 , 2 0 0 6 ) i i i

Contents

8.8.5 Managing SB Descriptor Lists in Host Mode .............................................................. 1108.8.6 Managing the EP Table in Host Mode ....................................................................... 1118.8.7 Managing the DMA Channel 9 Descriptor List .......................................................... 1128.8.8 Managing the Root Hub ............................................................................................. 1128.8.9 Managing USB IN Traffic in Device Mode ................................................................ 1138.8.10 USB OUT Traffic in Device Mode ............................................................................. 1168.8.11 USB Control Traffic in Device Mode ......................................................................... 117

9 Network Interface ...............................................................................................1199.1 The Ethernet II and IEEE 802.3 Standards...................................................................... 1199.2 Network interface registers ............................................................................................... 1209.3 Network Interface Configuration ..................................................................................... 1219.4 Pin Usage in MII and SNI Modes.................................................................................... 1229.5 Receiver Logic Functions ................................................................................................. 1229.5.1 Data Transfer to the Receiving FIFO .......................................................................... 1239.5.2 Address Recognition ................................................................................................... 1239.5.3 Receiver CRC Check. ................................................................................................. 1249.5.4 Received Frame Length Check .................................................................................... 1249.6 Transmitter Logic Functions............................................................................................ 1259.6.1 Transmission of Frames .............................................................................................. 1259.6.2 CSMA/CD Access Protocol ........................................................................................ 1269.6.3 Demand Priority Access Protocol ................................................................................ 1269.7 Management Interface ..................................................................................................... 1279.8 Ethernet Error and Statistics Counters ............................................................................. 1279.9 Network interrupts .......................................................................................................... 128

10 EIDE/ATA-2/ATA-3 Interface ............................................................................12910.1 ATA Interface Pin Connection ........................................................................................ 12910.2 EIDE/ATA-2/ATA-3 Interface Registers.......................................................................... 13010.3 Data Transfer................................................................................................................... 13010.3.1 Programmed Input/Output (PIO) .............................................................................. 13010.3.2 ATA DMA Handshaking ............................................................................................ 13010.3.3 ETRAX 100LX Register Access ................................................................................... 13110.3.4 ETRAX 100LX DMA Access ...................................................................................... 13110.4 Timing............................................................................................................................. 13110.5 Interrupts ......................................................................................................................... 132

11 Asynchronous Serial Ports ...................................................................................13311.1 General ............................................................................................................................ 13311.2 Connection to Input/Output Pins ................................................................................... 13311.3 Asynchronous Serial Port Registers................................................................................... 13411.4 Operation Modes............................................................................................................. 13511.5 Baud Rate Selection ......................................................................................................... 13611.6 CPU Controlled Operation ............................................................................................. 13711.7 DMA Controlled Operation ............................................................................................ 13711.8 Asynchronous Serial Port Interrupts................................................................................. 138

12 Synchronous Serial Interface ...............................................................................139

i v A X I S E T R A X 1 0 0 L X D e s i g n e r ' s R e f e r e n c e ( F e b r u a r y 9 , 2 0 0 6 )

Contents

12.1 Overview.......................................................................................................................... 13912.2 Mode Selection ................................................................................................................ 13912.3 Pin Usage......................................................................................................................... 14012.3.1 Pin Configuration ....................................................................................................... 14012.3.2 Pin Usage in the Different Modes ............................................................................... 14012.4 Synchronous Serial Port Registers .................................................................................... 14312.5 Configuration .................................................................................................................. 14412.6 Word Length ................................................................................................................... 14412.7 Frame Synchronization .................................................................................................... 14512.7.1 Frame Synchronization Modes .................................................................................... 14512.7.2 Frame Strobe Generation ............................................................................................ 14612.7.3 Stream Mode .............................................................................................................. 14612.8 Clocking .......................................................................................................................... 14712.8.1 Clock Generator ......................................................................................................... 14712.8.2 Data Sampling ............................................................................................................ 14712.8.3 Clock Gating .............................................................................................................. 14812.9 Flow Control ................................................................................................................... 14912.10 Interrupts ......................................................................................................................... 14912.11 Using The Sync Serial Ports with DMA........................................................................... 150

13 Parallel Ports .......................................................................................................15113.1 Parallel Port Registers....................................................................................................... 15113.2 Modes of Operation......................................................................................................... 15213.2.1 IEEE-1284 Compatibility (Centronics) Mode ............................................................ 15313.2.2 Fastbyte Mode ............................................................................................................ 15713.2.3 IEEE-1284 Nibble Mode ............................................................................................ 15813.2.4 IEEE-1284 Byte Mode ............................................................................................... 15913.2.5 IEEE-1284 ECP Mode (Forward and Reverse) ........................................................... 16013.2.6 ECP Wide (16-Bit) Mode ........................................................................................... 16313.2.7 EPP Mode .................................................................................................................. 16513.2.8 Manual Mode ............................................................................................................. 16913.3 Parallel Port Interrupts ..................................................................................................... 17013.3.1 Peripheral Interrupt .................................................................................................... 17013.3.2 ECP Command Interrupt ........................................................................................... 17013.3.3 Data Available Interrupt ............................................................................................. 17013.3.4 Ready Interrupt .......................................................................................................... 17113.3.5 EPP Interrupts ............................................................................................................ 171

14 Shared RAM Interface .........................................................................................17314.1 Shared RAM Interface Configuration .............................................................................. 17414.2 Shared RAM Interrupts.................................................................................................... 174

15 Timers .................................................................................................................17515.1 General ............................................................................................................................ 17515.2 Timer Registers ................................................................................................................ 17515.3 Clock Prescaling: The Programmable Clock Divider........................................................ 17615.4 Programmable Timers...................................................................................................... 17615.4.1 Timer Operation ........................................................................................................ 176

A X I S E T R A X 1 0 0 L X D e s i g n e r ' s R e f e r e n c e ( F e b r u a r y 9 , 2 0 0 6 ) v

Contents

15.5 Timer Input Clock........................................................................................................... 17715.5.1 Timer0 Input Clock .................................................................................................... 17715.5.2 Timer1 Input Clock .................................................................................................... 17815.6 Cascade Mode.................................................................................................................. 17815.7 Watchdog Timer.............................................................................................................. 17815.8 Timer Interrupts .............................................................................................................. 179

16 General I/O Ports ................................................................................................18116.1 General Port PA............................................................................................................... 18116.1.1 Interrupts at General Port PA ..................................................................................... 18116.2 General Port PB............................................................................................................... 18216.2.1 Configuration of Signal Directions at General Port PB ............................................... 18316.2.2 General Port PB and the I2C Interface ....................................................................... 18316.2.3 General Port PB and the Peripheral Chip-Select Signals .............................................. 18416.2.4 General Port PB and the Synchronous Serial Ports ...................................................... 18416.2.5 General Port PB and the SCSI Ports ........................................................................... 18416.2.6 General Port PB and the USB Ports ............................................................................ 18516.3 Discrete General Ports ..................................................................................................... 18516.4 General I/O Registers....................................................................................................... 186

17 Interrupts ............................................................................................................18717.1 Interrupt Masks ............................................................................................................... 18717.2 Interrupt Status................................................................................................................ 18817.3 USB Interrupts................................................................................................................. 18817.4 Interrupt Registers ........................................................................................................... 18817.5 Non-Maskable Interrupts................................................................................................. 19017.6 Masked Interrupts with Internally Generated Vector Numbers........................................ 19017.6.1 Interrupts in Register Sub-Set 0 .................................................................................. 19217.6.2 Interrupts in Register Sub-Set 1 .................................................................................. 19617.6.3 Interrupts in Register Sub-Set 2 .................................................................................. 19917.6.4 Interrupts in the USB Register Set .............................................................................. 20117.6.5 Vector Number Register Sub-Set ................................................................................ 20217.7 External Maskable Interrupt with an External Vector Number ........................................ 20417.8 Software Interrupts .......................................................................................................... 204

18 Internal Registers ................................................................................................20718.1 Conventions..................................................................................................................... 20718.1.1 Notation ..................................................................................................................... 20718.1.2 Base Address ............................................................................................................... 20718.2 Bus Interface Configuration Registers .............................................................................. 20718.2.1 R_WAITSTATES ...................................................................................................... 20718.2.2 R_BUS_CONFIG ...................................................................................................... 20918.2.3 R_BUS_STATUS ....................................................................................................... 21018.2.4 R_DRAM_TIMING .................................................................................................. 21118.2.5 R_SDRAM_TIMING ................................................................................................ 21218.2.6 R_DRAM_CONFIG ................................................................................................. 21318.2.7 R_SDRAM_CONFIG ............................................................................................... 21518.3 External DMA Registers................................................................................................... 217

v i A X I S E T R A X 1 0 0 L X D e s i g n e r ' s R e f e r e n c e ( F e b r u a r y 9 , 2 0 0 6 )

Contents

18.3.1 R_EXT_DMA_0_CMD ............................................................................................ 21718.3.2 R_EXT_DMA_0_STAT ............................................................................................ 21818.3.3 R_EXT_DMA_0_ADDR ........................................................................................... 21918.3.4 R_EXT_DMA_I_CMD ............................................................................................. 22018.3.5 R_EXT_DMA_I_STAT ............................................................................................. 22118.3.6 R_EXT_DMA_I_ADDR ........................................................................................... 22218.4 Timer Registers ................................................................................................................ 22318.4.1 R_TIMER_CTRL ...................................................................................................... 22318.4.2 R_TIMER_DATA ..................................................................................................... 22518.4.3 R_TIMER01_DATA ................................................................................................. 22618.4.4 R_TIMER0_DATA ................................................................................................... 22718.4.5 R_TIMER1_DATA ................................................................................................... 22818.4.6 R_WATCHDOG ...................................................................................................... 22918.4.7 R_CLOCK_PRESCALE ............................................................................................ 23018.4.8 R_TIMER_PRESCALE ............................................................................................. 23118.4.9 R_PRESCALE_STATUS ........................................................................................... 23218.4.10 R_TIM_PRESC_STATUS ......................................................................................... 23318.5 Shared RAM Interface Registers....................................................................................... 23418.5.1 R_SHARED_RAM_CONFIG ................................................................................... 23418.5.2 R_SHARED_RAM_ADDR ....................................................................................... 23518.6 General Configuration Registers ...................................................................................... 23618.6.1 R_GEN_CONFIG ..................................................................................................... 23618.6.2 R_GEN_CONFIG_II ................................................................................................ 23818.6.3 R_PORT_G_DATA .................................................................................................. 23918.7 General Port Configuration Registers............................................................................... 24018.7.1 R_PORT_PA_SET .................................................................................................... 24018.7.2 R_PORT_PA_DATA ................................................................................................. 24118.7.3 R_PORT_PA_DIR .................................................................................................... 24218.7.4 R_PORT_PA_READ ................................................................................................. 24318.7.5 R_PORT_PB_SET ..................................................................................................... 24418.7.6 R_PORT_PB_DATA ................................................................................................. 24618.7.7 R_PORT_PB_DIR .................................................................................................... 24718.7.8 R_PORT_PB_CONFIG ............................................................................................ 24818.7.9 R_PORT_PB_I2C ..................................................................................................... 24918.7.10 R_PORT_PB_READ ................................................................................................. 25018.8 Serial Port Registers.......................................................................................................... 25118.8.1 R_SERIAL0_CTRL .................................................................................................... 25118.8.2 R_SERIAL0_BAUD ................................................................................................... 25318.8.3 R_SERIAL0_REC_CTRL .......................................................................................... 25418.8.4 R_SERIAL0_TR_CTRL ............................................................................................ 25518.8.5 R_SERIAL0_TR_DATA ............................................................................................ 25618.8.6 R_SERIAL0_READ ................................................................................................... 25718.8.7 R_SERIAL0_STATUS ............................................................................................... 25818.8.8 R_SERIAL0_REC_DATA ......................................................................................... 25918.8.9 R_SERIAL0_XOFF .................................................................................................... 26018.8.10 R_SERIAL1_CTRL .................................................................................................... 261

A X I S E T R A X 1 0 0 L X D e s i g n e r ' s R e f e r e n c e ( F e b r u a r y 9 , 2 0 0 6 ) v i i

Contents

18.8.11 R_SERIAL1_BAUD ................................................................................................... 26318.8.12 R_SERIAL1_REC_CTRL .......................................................................................... 26418.8.13 R_SERIAL1_TR_CTRL ............................................................................................ 26518.8.14 R_SERIAL1_TR_DATA ............................................................................................ 26618.8.15 R_SERIAL1_READ ................................................................................................... 26718.8.16 R_SERIAL1_STATUS ............................................................................................... 26818.8.17 R_SERIAL1_REC_DATA ......................................................................................... 26918.8.18 R_SERIAL1_XOFF .................................................................................................... 27018.8.19 R_SERIAL2_CTRL .................................................................................................... 27118.8.20 R_SERIAL2_BAUD ................................................................................................... 27318.8.21 R_SERIAL2_REC_CTRL .......................................................................................... 27418.8.22 R_SERIAL2_TR_CTRL ............................................................................................ 27518.8.23 R_SERIAL2_TR_DATA ............................................................................................ 27618.8.24 R_SERIAL2_READ ................................................................................................... 27718.8.25 R_SERIAL2_STATUS ............................................................................................... 27818.8.26 R_SERIAL2_REC_DATA ......................................................................................... 27918.8.27 R_SERIAL2_XOFF .................................................................................................... 28018.8.28 R_SERIAL3_CTRL .................................................................................................... 28118.8.29 R_SERIAL3_BAUD ................................................................................................... 28318.8.30 R_SERIAL3_REC_CTRL .......................................................................................... 28418.8.31 R_SERIAL3_TR_CTRL ............................................................................................ 28518.8.32 R_SERIAL3_TR_DATA ............................................................................................ 28618.8.33 R_SERIAL3_READ ................................................................................................... 28718.8.34 R_SERIAL3_STATUS ............................................................................................... 28818.8.35 R_SERIAL3_REC_DATA ......................................................................................... 28918.8.36 R_SERIAL3_XOFF .................................................................................................... 29018.8.37 R_ALT_SER_BAUDRATE ....................................................................................... 29118.8.38 R_SERIAL_PRESCALE ............................................................................................. 29318.8.39 R_SER_PRESC_STATUS ......................................................................................... 29418.9 Network Interface Registers ............................................................................................. 29518.9.1 R_NETWORK_SA_0 ................................................................................................ 29618.9.2 R_NETWORK_SA_1 ................................................................................................ 29718.9.3 R_NETWORK_SA_2 ................................................................................................ 29818.9.4 R_NETWORK_GA_0 ............................................................................................... 29918.9.5 R_NETWORK_GA_1 ............................................................................................... 30018.9.6 R_NETWORK_REC_CONFIG ............................................................................... 30118.9.7 R_NETWORK_GEN_CONFIG .............................................................................. 30218.9.8 R_NETWORK_TR_CTRL ....................................................................................... 30318.9.9 R_NETWORK_MGM_CTRL .................................................................................. 30418.9.10 R_NETWORK_STAT ............................................................................................... 30518.9.11 R_REC_COUNTERS ............................................................................................... 30618.9.12 R_TR_COUNTERS .................................................................................................. 30718.9.13 R_PHY_COUNTERS ............................................................................................... 30818.10 Parallel Port Registers....................................................................................................... 30818.10.1 R_PAR0_CTRL_DATA ............................................................................................ 30818.10.2 R_PAR0_CTRL ......................................................................................................... 310

v i i i A X I S E T R A X 1 0 0 L X D e s i g n e r ' s R e f e r e n c e ( F e b r u a r y 9 , 2 0 0 6 )

Contents

18.10.3 R_PAR0_STATUS_DATA ........................................................................................ 31118.10.4 R_PAR0_STATUS ..................................................................................................... 31318.10.5 R_PAR_ECP16_DATA ............................................................................................. 31518.10.6 R_PAR0_CONFIG .................................................................................................... 31618.10.7 R_PAR0_DELAY ....................................................................................................... 31918.10.8 R_PAR1_CTRL_DATA ............................................................................................ 32018.10.9 R_PAR1_CTRL ......................................................................................................... 32218.10.10 R_PAR1_STATUS_DATA ........................................................................................ 32318.10.11 R_PAR1_STATUS ..................................................................................................... 32518.10.12 R_PAR1_CONFIG .................................................................................................... 32718.10.13 R_PAR1_DELAY ....................................................................................................... 33018.11 ATA Interface Registers.................................................................................................... 33118.11.1 R_ATA_CTRL_DATA .............................................................................................. 33118.11.2 R_ATA_STATUS_DATA .......................................................................................... 33218.11.3 R_ATA_CONFIG ..................................................................................................... 33318.11.4 R_ATA_TRANSFER_CNT ....................................................................................... 33418.12 SCSI Registers.................................................................................................................. 33518.12.1 R_SCSI0_CTRL ........................................................................................................ 33518.12.2 R_SCSI0_CMD_DATA ............................................................................................ 33718.12.3 R_SCSI0_DATA ........................................................................................................ 33818.12.4 R_SCSI0_CMD ......................................................................................................... 33918.12.5 R_SCSI0_STATUS_CTRL ........................................................................................ 34018.12.6 R_SCSI0_STATUS .................................................................................................... 34118.12.7 R_SCSI0_DATA_IN ................................................................................................. 34318.12.8 R_SCSI1_CTRL ........................................................................................................ 34418.12.9 R_SCSI1_CMD_DATA ............................................................................................ 34618.12.10 R_SCSI1_DATA ........................................................................................................ 34718.12.11 R_SCSI1_CMD ......................................................................................................... 34818.12.12 R_SCSI1_STATUS_CTRL ........................................................................................ 34918.12.13 R_SCSI1_STATUS .................................................................................................... 35018.12.14 R_SCSI1_DATA_IN ................................................................................................. 35218.13 Interrupt Mask and Status Registers ................................................................................. 35318.13.1 R_IRQ_MASK0_RD ................................................................................................. 35318.13.2 R_IRQ_MASK0_CLR ............................................................................................... 35818.13.3 R_IRQ_READ0 ......................................................................................................... 36018.13.4 R_IRQ_MASK0_SET ................................................................................................ 36218.13.5 R_IRQ_MASK1_RD ................................................................................................. 36518.13.6 R_IRQ_MASK1_CLR ............................................................................................... 36918.13.7 R_IRQ_READ1 ......................................................................................................... 37118.13.8 R_IRQ_MASK1_SET ................................................................................................ 37318.13.9 R_IRQ_MASK2_RD ................................................................................................. 37518.13.10 R_IRQ_MASK2_CLR ............................................................................................... 37818.13.11 R_IRQ_READ2 ......................................................................................................... 38018.13.12 R_IRQ_MASK2_SET ................................................................................................ 38218.13.13 R_VECT_MASK_RD ................................................................................................ 38418.13.14 R_VECT_MASK_CLR .............................................................................................. 386

A X I S E T R A X 1 0 0 L X D e s i g n e r ' s R e f e r e n c e ( F e b r u a r y 9 , 2 0 0 6 ) i x

Contents

18.13.15 R_VECT_READ ........................................................................................................ 38818.13.16 R_VECT_MASK_SET .............................................................................................. 39018.14 DMA Registers ................................................................................................................ 39118.14.1 R_SET_EOP .............................................................................................................. 39118.14.2 R_DMA_CH0_HWSW ............................................................................................. 39218.14.3 R_DMA_CH0_DESCR ............................................................................................. 39318.14.4 R_DMA_CH0_NEXT ............................................................................................... 39418.14.5 R_DMA_CH0_BUF .................................................................................................. 39518.14.6 R_DMA_CH0_FIRST ............................................................................................... 39618.14.7 R_DMA_CH0_CMD ................................................................................................ 39718.14.8 R_DMA_CH0_CLR_INTR ...................................................................................... 39818.14.9 R_DMA_CH0_STATUS ........................................................................................... 39918.14.10 R_DMA_CH1_HWSW ............................................................................................. 40018.14.11 R_DMA_CH1_DESCR ............................................................................................. 40118.14.12 R_DMA_CH1_NEXT ............................................................................................... 40218.14.13 R_DMA_CH1_BUF .................................................................................................. 40318.14.14 R_DMA_CH1_FIRST ............................................................................................... 40418.14.15 R_DMA_CH1_CMD ................................................................................................ 40518.14.16 R_DMA_CH1_CLR_INTR ...................................................................................... 40618.14.17 R_DMA_CH1_STATUS ........................................................................................... 40718.14.18 R_DMA_CH2_HWSW ............................................................................................. 40818.14.19 R_DMA_CH2_DESCR ............................................................................................. 40918.14.20 R_DMA_CH2_NEXT ............................................................................................... 41018.14.21 R_DMA_CH2_BUF .................................................................................................. 41118.14.22 R_DMA_CH2_FIRST ............................................................................................... 41218.14.23 R_DMA_CH2_CMD ................................................................................................ 41318.14.24 R_DMA_CH2_CLR_INTR ...................................................................................... 41418.14.25 R_DMA_CH2_STATUS ........................................................................................... 41518.14.26 R_DMA_CH3_HWSW ............................................................................................. 41618.14.27 R_DMA_CH3_DESCR ............................................................................................. 41718.14.28 R_DMA_CH3_NEXT ............................................................................................... 41818.14.29 R_DMA_CH3_BUF .................................................................................................. 41918.14.30 R_DMA_CH3_FIRST ............................................................................................... 42018.14.31 R_DMA_CH3_CMD ................................................................................................ 42118.14.32 R_DMA_CH3_CLR_INTR ...................................................................................... 42218.14.33 R_DMA_CH3_STATUS ........................................................................................... 42318.14.34 R_DMA_CH4_HWSW ............................................................................................. 42418.14.35 R_DMA_CH4_DESCR ............................................................................................. 42518.14.36 R_DMA_CH4_NEXT ............................................................................................... 42618.14.37 R_DMA_CH4_BUF .................................................................................................. 42718.14.38 R_DMA_CH4_FIRST ............................................................................................... 42818.14.39 R_DMA_CH4_CMD ................................................................................................ 42918.14.40 R_DMA_CH4_CLR_INTR ...................................................................................... 43018.14.41 R_DMA_CH4_STATUS ........................................................................................... 43118.14.42 R_DMA_CH5_HWSW ............................................................................................. 43218.14.43 R_DMA_CH5_DESCR ............................................................................................. 433

x A X I S E T R A X 1 0 0 L X D e s i g n e r ' s R e f e r e n c e ( F e b r u a r y 9 , 2 0 0 6 )

Contents

18.14.44 R_DMA_CH5_NEXT ............................................................................................... 43418.14.45 R_DMA_CH5_BUF .................................................................................................. 43518.14.46 R_DMA_CH5_FIRST ............................................................................................... 43618.14.47 R_DMA_CH5_CMD ................................................................................................ 43718.14.48 R_DMA_CH5_CLR_INTR ...................................................................................... 43818.14.49 R_DMA_CH5_STATUS ........................................................................................... 43918.14.50 R_DMA_CH6_HWSW ............................................................................................. 44018.14.51 R_DMA_CH6_DESCR ............................................................................................. 44118.14.52 R_DMA_CH6_NEXT ............................................................................................... 44218.14.53 R_DMA_CH6_BUF .................................................................................................. 44318.14.54 R_DMA_CH6_FIRST ............................................................................................... 44418.14.55 R_DMA_CH6_CMD ................................................................................................ 44518.14.56 R_DMA_CH6_CLR_INTR ...................................................................................... 44618.14.57 R_DMA_CH6_STATUS ........................................................................................... 44718.14.58 R_DMA_CH7_HWSW ............................................................................................. 44818.14.59 R_DMA_CH7_DESCR ............................................................................................. 44918.14.60 R_DMA_CH7_NEXT ............................................................................................... 45018.14.61 R_DMA_CH7_BUF .................................................................................................. 45118.14.62 R_DMA_CH7_FIRST ............................................................................................... 45218.14.63 R_DMA_CH7_CMD ................................................................................................ 45318.14.64 R_DMA_CH7_CLR_INTR ...................................................................................... 45418.14.65 R_DMA_CH7_STATUS ........................................................................................... 45518.14.66 R_DMA_CH8_HWSW ............................................................................................. 45618.14.67 R_DMA_CH8_DESCR ............................................................................................. 45718.14.68 R_DMA_CH8_NEXT ............................................................................................... 45818.14.69 R_DMA_CH8_BUF .................................................................................................. 45918.14.70 R_DMA_CH8_FIRST ............................................................................................... 46018.14.71 R_DMA_CH8_CMD ................................................................................................ 46118.14.72 R_DMA_CH8_CLR_INTR ...................................................................................... 46218.14.73 R_DMA_CH8_STATUS ........................................................................................... 46318.14.74 R_DMA_CH8_SUB .................................................................................................. 46418.14.75 R_DMA_CH8_NEP .................................................................................................. 46518.14.76 R_DMA_CH8_SUB0_EP .......................................................................................... 46618.14.77 R_DMA_CH8_SUB0_CMD .................................................................................... 46718.14.78 R_DMA_CH8_SUB0_CLR_INTR ........................................................................... 46818.14.79 R_DMA_CH8_SUB1_EP .......................................................................................... 46918.14.80 R_DMA_CH8_SUB1_CMD .................................................................................... 47018.14.81 R_DMA_CH8_SUB1_CLR_INTR ........................................................................... 47118.14.82 R_DMA_CH8_SUB2_EP .......................................................................................... 47218.14.83 R_DMA_CH8_SUB2_CMD .................................................................................... 47318.14.84 R_DMA_CH8_SUB2_CLR_INTR ........................................................................... 47418.14.85 R_DMA_CH8_SUB3_EP .......................................................................................... 47518.14.86 R_DMA_CH8_SUB3_CMD .................................................................................... 47618.14.87 R_DMA_CH8_SUB3_CLR_INTR ........................................................................... 47718.14.88 R_DMA_CH9_HWSW ............................................................................................. 47818.14.89 R_DMA_CH9_DESCR ............................................................................................. 479

A X I S E T R A X 1 0 0 L X D e s i g n e r ' s R e f e r e n c e ( F e b r u a r y 9 , 2 0 0 6 ) x i

Contents

18.14.90 R_DMA_CH9_NEXT ............................................................................................... 48018.14.91 R_DMA_CH9_BUF .................................................................................................. 48118.14.92 R_DMA_CH9_FIRST ............................................................................................... 48218.14.93 R_DMA_CH9_CMD ................................................................................................ 48318.14.94 R_DMA_CH9_CLR_INTR ...................................................................................... 48418.14.95 R_DMA_CH9_STATUS ........................................................................................... 48518.15 Test Mode Registers......................................................................................................... 48618.15.1 R_TEST_MODE ....................................................................................................... 48618.15.2 R_SINGLE_STEP ...................................................................................................... 48818.16 Universal Serial Bus Interface Control Registers ............................................................... 48918.16.1 R_USB_REVISION ................................................................................................... 48918.16.2 R_USB_COMMAND ............................................................................................... 49018.16.3 R_USB_COMMAND_DEV ..................................................................................... 49118.16.4 R_USB_STATUS ....................................................................................................... 49218.16.5 R_USB_IRQ_MASK_SET ........................................................................................ 49318.16.6 R_USB_IRQ_MASK_READ ..................................................................................... 49418.16.7 R_USB_IRQ_MASK_CLR ........................................................................................ 49518.16.8 R_USB_IRQ_READ .................................................................................................. 49618.16.9 R_USB_IRQ_MASK_SET_DEV .............................................................................. 49718.16.10 R_USB_IRQ_MASK_READ_DEV ........................................................................... 49818.16.11 R_USB_IRQ_MASK_CLR_DEV .............................................................................. 49918.16.12 R_USB_IRQ_READ_DEV ........................................................................................ 50018.16.13 R_USB_FM_NUMBER ............................................................................................ 50118.16.14 R_USB_FM_NUMBER_DEV .................................................................................. 50218.16.15 R_USB_FM_INTERVAL .......................................................................................... 50318.16.16 R_USB_FM_REMAINING ...................................................................................... 50418.16.17 R_USB_FM_PSTART ............................................................................................... 50518.16.18 R_USB_RH_STATUS ............................................................................................... 50618.16.19 R_USB_RH_PORT_STATUS_1 .............................................................................. 50718.16.20 R_USB_RH_PORT_STATUS_2 .............................................................................. 50818.16.21 R_USB_EPT_INDEX ................................................................................................ 50918.16.22 R_USB_EPT_DATA ................................................................................................. 51018.16.23 R_USB_EPT_DATA_ISO ......................................................................................... 51118.16.24 R_USB_EPT_DATA_DEV ....................................................................................... 51218.16.25 R_USB_EPID_ATTN ............................................................................................... 51318.16.26 R_USB_PORT1_DISABLE ....................................................................................... 51418.16.27 R_USB_PORT2_DISABLE ....................................................................................... 51518.17 MMU Registers ............................................................................................................... 51618.17.1 R_MMU_CONFIG ................................................................................................... 51618.17.2 R_MMU_KSEG ........................................................................................................ 51818.17.3 R_MMU_CTRL ........................................................................................................ 51918.17.4 R_MMU_ENABLE ................................................................................................... 52018.17.5 R_MMU_KBASE_LO ............................................................................................... 52118.17.6 R_MMU_KBASE_HI ................................................................................................ 52218.17.7 R_MMU_CONTEXT ............................................................................................... 52318.17.8 R_MMU_CAUSE ...................................................................................................... 524

x i i A X I S E T R A X 1 0 0 L X D e s i g n e r ' s R e f e r e n c e ( F e b r u a r y 9 , 2 0 0 6 )

Contents

18.17.9 R_TLB_SELECT ....................................................................................................... 52518.17.10 R_TLB_LO ................................................................................................................ 52618.17.11 R_TLB_HI ................................................................................................................. 52718.18 Synchronous Serial Port Registers .................................................................................... 52818.18.1 R_SYNC_SERIAL1_REC_DATA ............................................................................. 52818.18.2 R_SYNC_SERIAL1_REC_WORD ........................................................................... 52918.18.3 R_SYNC_SERIAL1_REC_BYTE .............................................................................. 53018.18.4 R_SYNC_SERIAL1_STATUS ................................................................................... 53118.18.5 R_SYNC_SERIAL1_TR_DATA ................................................................................ 53218.18.6 R_SYNC_SERIAL1_TR_WORD .............................................................................. 53318.18.7 R_SYNC_SERIAL1_TR_BYTE ................................................................................. 53418.18.8 R_SYNC_SERIAL1_CTRL ....................................................................................... 53518.18.9 R_SYNC_SERIAL3_REC_DATA ............................................................................. 53818.18.10 R_SYNC_SERIAL3_REC_WORD ........................................................................... 53918.18.11 R_SYNC_SERIAL3_REC_BYTE .............................................................................. 54018.18.12 R_SYNC_SERIAL3_STATUS ................................................................................... 54118.18.13 R_SYNC_SERIAL3_TR_DATA ................................................................................ 54218.18.14 R_SYNC_SERIAL3_TR_WORD .............................................................................. 54318.18.15 R_SYNC_SERIAL3_TR_BYTE ................................................................................. 54418.18.16 R_SYNC_SERIAL3_CTRL ....................................................................................... 54518.18.17 R_SYNC_SERIAL_PRESCALE ................................................................................. 548

19 Electrical Information .........................................................................................55119.1 Pinout.............................................................................................................................. 55119.2 Clock and PLL Signals ..................................................................................................... 55219.3 Power and Ground Signals............................................................................................... 55219.4 Bus Interface Signals ........................................................................................................ 55319.5 Logic Analyzer Mode and Test Signals ............................................................................. 55619.6 General Port PA Signals ................................................................................................... 55719.7 Asynchronous Serial Port 0 Signals .................................................................................. 55719.8 Network Interface Signals ................................................................................................ 55819.9 Multiplexed Signal Groups .............................................................................................. 55919.9.1 Multiplexed I/O Signals - Group A ............................................................................. 56119.9.2 Multiplexed I/O Signals - Group B ............................................................................. 56119.9.3 Multiplexed I/O Signals - Group C ............................................................................ 56219.9.4 Multiplexed I/O Signals - Group D ............................................................................ 56219.9.5 Multiplexed I/O Signals - Group E ............................................................................. 56319.9.6 Multiplexed I/O Signals - Group F ............................................................................. 56319.10 Multiplexed Interfaces...................................................................................................... 56419.10.1 SCSI Ports .................................................................................................................. 56419.10.2 ATA ............................................................................................................................ 56719.10.3 Parallel Ports ............................................................................................................... 56819.10.4 Shared RAM and Shared RAM-W .............................................................................. 57019.10.5 Asynchronous Serial Ports ........................................................................................... 57219.10.6 Synchronous Serial Ports p1 and p3 ............................................................................ 57319.10.7 USB ............................................................................................................................ 57619.10.8 Chip Selects for Peripherals (CSP) .............................................................................. 577

A X I S E T R A X 1 0 0 L X D e s i g n e r ' s R e f e r e n c e ( F e b r u a r y 9 , 2 0 0 6 ) x i i i

Contents

19.10.9 I2C ............................................................................................................................. 57719.10.10 General Port PB .......................................................................................................... 57719.11 I/O Pin Default Values .................................................................................................... 57819.12 DC Electrical Specifications ............................................................................................. 57919.12.1 Absolute Maximum Ratings ........................................................................................ 57919.12.2 Recommended Operating Conditions ......................................................................... 57919.12.3 Capacitance ................................................................................................................ 58019.12.4 DC Electrical Characteristics ...................................................................................... 58019.12.5 Input Buffer Types ..................................................................................................... 58019.13 AC Electrical Specifications.............................................................................................. 58119.13.1 Conditions .................................................................................................................. 58219.13.2 SRAM/Flash/Peripheral Timing ................................................................................. 58319.13.3 Synchronous DRAM .................................................................................................. 58619.13.4 Asynchronous DRAM ................................................................................................ 59019.13.5 General Bus Interface Timing Diagrams ..................................................................... 59419.13.6 External DMA Timing Diagrams ............................................................................... 59719.13.7 irq and nmi Timing .................................................................................................... 60119.13.8 Shared RAM Interface Timing .................................................................................... 60219.13.9 Network Interface Timing .......................................................................................... 60419.13.10 Reset and Clock Timing ............................................................................................. 60519.14 Physical Dimensions ........................................................................................................ 607Appendix A Register Address Index .....................................................................609Appendix B PLL Clock Generation .....................................................................615

x i v A X I S E T R A X 1 0 0 L X D e s i g n e r ' s R e f e r e n c e ( F e b r u a r y 9 , 2 0 0 6 )

1 Introduction

1 Introduction

1.1 Overview

The AXIS ETRAX 100LX is a single-chip integrated circuit designed for embedded network connectivity applications. The ETRAX 100LX improves upon the features available for the AXIS ETRAX 100, including support for Universal Serial Bus 1.1. It is compatible with the widespread ETRAX family, and offers further advances in microprocessor design and performance. The ETRAX 100LX chip incorporates the AXIS CRIS CPU which not only suits all the requirements of a network connectivity product, but also acts as an integrated core especially suited for our system.

The ETRAX 100LX is ideal in executing multi protocol network stacks on one chip. The ETRAX 100LX has a 100 MIPS RISC CPU, 8 kilobyte unified instruction/data cache, high bandwidth DMA controlled I/O ports, and an on-chip Fast Ethernet controller. Its integrated functions, minimal power consumption, and high code density makes it highly suitable for a wide range of embedded applications that require high performance and low system cost.

The ETRAX 100LX programmable bus interface supports both 16-bit and 32-bit data bus widths, and interfaces directly to SDRAM, EDO DRAM, SRAM, EPROM, parallel EEPROM, and FlashPROM.

Optimized Network Controller with RISC CPU, Cacheand Multiple I/O Ports

A X I S E T R A X 1 0 0 L X D e s i g n e r ' s R e f e r e n c e ( F e b r u a r y 9 , 2 0 0 6 ) 1

1 Introduction

1.2 Features

• High performance 100 MIPS (200 MIPS/W) 32-bit RISC CPU, 112k Dhrystones.

• Designed specifically for running Linux by including an MMU.

• Ethernet controller supports 100Mbit/10Mbit MII (Compatible with IEEE 802.3 and Fast Ethernet standards).

• Four asynchronous serial ports with an internal baudrate programmable from 48 Hz to 6.25 MHz, and an external baudrate up to 3.125 MHz.

• Two synchronous serial ports. Master or Slave synchronous serial mode with a codec clock between 32 kHz and 4.096 MHz.

• Universal Serial Bus 1.1 Host and Device mode operation. Hardware support for dynamic connect/disconnect, suspend/resume and remote wakeup.

• Configuration of up to four EIDE/ATA-2 ports for up to 8 IDE disk drives.

• 16-bit general I/O port. The direction of each bit can be individually controlled.

• Two configurable parallel I/O ports for Centronics, IEEE 1284 byte, ECP, and EPP mode, and Shared RAM interface.

• Optimized for compact code and high speed with configurable 16-bit or 32-bit bus width.

• Bus interface supporting SDRAM, EDO DRAM, SRAM, EPROM, parallel EEPROM, and FlashPROM.

• 8 kilobyte on chip cache memory.

• DMA controlled network and port I/O for high performance

• Excellent C/C++ language support and high code density.

• Configurable bootstrap through network, serial, and parallel ports as well as FlashPROM.

• Low power consumption, 350 mW typically.

• 256-pin PBGA package, 27 x 27 x 2.15 mm.

2 A X I S E T R A X 1 0 0 L X D e s i g n e r ' s R e f e r e n c e ( F e b r u a r y 9 , 2 0 0 6 )

1 Introduction

1.3 Functional Block Diagram

The CPU in ETRAX 100LX is a RISC CPU with internal cache memory. Data handling is provided by internal DMA within the chip as well as to and from external units. The internal clocks are generated by a PLL clock multiplier that takes its input from an external clock generator. ETRAX 100LX provides internal and external vectorized interrupt.

ClockGenerator

InterruptController

CRIS CORE100 MHz

8Kb Instruction/Data Cache

General Purpose Timers,1 Fixed Timer, Watchdog Timer

MMU

ExternalPeripheralController

MemoryController

10/100 EthernetMII/SNI MAC

UART x2

GP

IO (

up to

62

Pin

s)

10-C

hann

el D

MA

, 64

Byt

e F

IFO

ConfigurableBlocks

USB 1.1 x2

IDE x4

UART x2

1284 x2

SynchronousSerial x2

GPIO,I2C

50 MHz BUS32-bit Data, 32-bit Address

A X I S E T R A X 1 0 0 L X D e s i g n e r ' s R e f e r e n c e ( F e b r u a r y 9 , 2 0 0 6 ) 3

1 Introduction

4 A X I S E T R A X 1 0 0 L X D e s i g n e r ' s R e f e r e n c e ( F e b r u a r y 9 , 2 0 0 6 )

2 RISC CPU

2 RISC CPUThe CPU in ETRAX 100LX is a 32-bit RISC CPU with a 16-bit wide instruction. The CPU complies with the Axis Code Reduced Instruction Set (CRIS) architecture. It runs at a cycle frequency of 100 MHz, giving a peak performance of 100 MIPS. A summary of the CRIS architecture is given below. The CRIS CPU architecture is described in more detail in the “ETRAX 100LX Programmer’s Manual”.

2.1 Registers

The processor contains 14 32-bit General Registers (R0 - R13), one 32-bit Stack Pointer (R14 or SP), and one 32-bit Program Counter (R15 or PC).

The processor architecture also contains 16 Special Registers (P0 - P15), ten of which are implemented. The registers are presented in the figures below:

General Registers:

Figure 2-1 General Registers

31 16 15 8 7 0

R0 - R13: General Registers

SP or R14: Stack Pointer

PC or R15: Program Counter

A X I S E T R A X 1 0 0 L X D e s i g n e r ’ s R e f e r e n c e ( F e b r u a r y 9 , 2 0 0 6 ) 5

2 RISC CPU

Special Registers:

Figure 2-2 Special Registers

2.2 Flags and Condition Codes

The Condition Code Register (CCR) and its 32-bit extension, the Dword Condition Code Register (DCCR), for the ETRAX 100LX contain eleven different flags. The remaining bits are always zero:

Figure 2-3 The Condition Code Register (CCR)/ Dword Condition Code Register (DCCR)

31 16

15 8

7 0

VR

CCR

IBR

IRP

SRP

BAR

DCCR

BRP

(P0)

(P1)

(P2)

(P3)

(P4)

(P5)

(P6)

(P7)

(P8)

(P9)

(P10)

(P11)

(P12)

(P13)

(P14)

(P15)

Constant Zero Register

Version Register

Reserved

Reserved


Condition Code Register

Reserved

Multiply Overflow Register


Interrupt Base Register

Interrupt Return Pointer

Subroutine Return Pointer

Breakpoint Address Register

Dword Condition Code Register

Breakpoint Return Pointer

User Mode Stack PointerUSP

MOF

0 U I X N Z V C

msb 0

User Mode Flag

Breakpoint Enable Flag

Interrupt Enable Flag

Extended Arithmetic Flag

Negative Flag

Zero Flag

Overflow Flag

Carry Flag

BPF

Write Failed Flag

Interrupt Acknowledge Flag

M

NMI Flag

10

6 A X I S E T R A X 1 0 0 L X D e s i g n e r ’ s R e f e r e n c e ( F e b r u a r y 9 , 2 0 0 6 )

2 RISC CPU

These flags can be tested using one of the 16 condition codes specified below:

2.3 Data Organization in Memory

The data types supported by the CRIS are:

Each address location contains one byte of data. Data is stored in memory with the least significant byte at the lowest address (“little endian”). The CRIS CPU in ETRAX 100LX has a 32-bit wide data bus. A conversion from 32 bits to 16 bits is performed by the bus interface in the case of an external 16-bit data bus mode.

Data can be aligned to any address. If the data crosses a 32-bit boundary, the CPU will split the data access into two separate accesses. So, the use of unaligned word and dword data will degrade performance.

Code Alt Condition Encoding Boolean Function

CC HS Carry Clear 0000 C

CS LO Carry Set 0001 C

NE Not Equal 0010 Z

EQ Equal 0011 Z

VC Overflow Clear 0100 V

VS Overflow Set 0101 V

PL Plus 0110 N

MI Minus 0111 N

LS Low or Same 1000 C + Z

HI High 1001 C * Z

GE Greater or Equal 1010 N * V + N * V

LT Less Than 1011 N * V + N * V

GT Greater Than 1100 N * V * Z + N * V * Z

LE Less or Equal 1101 Z + N * V + N * V

A Always True 1110 1

WF Write Failed 1111 P

Table 2-1 Condition Codes

Name Description Size Modifier

Byte 8-bit integer .B

Word 16-bit integer .W

Dword 32-bit integer or address .D

Table 2-2 Data Types supported by the CRIS

A X I S E T R A X 1 0 0 L X D e s i g n e r ’ s R e f e r e n c e ( F e b r u a r y 9 , 2 0 0 6 ) 7

2 RISC CPU

The figures below show examples of data organization with a 16-bit bus and a 32-bit bus:

Figure 2-4 Example of Data Organization with a 16-bit Bus

Figure 2-5 Example of Data Organization with a 32-bit Bus

2.4 Instruction Format

The basic instruction word is 16 bits long. Instructions must be 16-bit aligned.

When the CPU fetches 32 bits, containing two 16-bit aligned instructions, it saves the upper two bytes in an internal prefetch register. Thus, the CPU will only perform one read for every second instruction when running consecutive code.

The most common instructions follow the same general instruction format:

Figure 2-6 General Instruction Format

Byte a

Address

Byte b

Word c

An

An + 2

An + 4

An + 6

0

lsbmsb

Dword dlsb

msb

Dword g

lsb

msblsb

msb

An + 8

An + 10

An + 12

An + 14

15

Byte eWord f

Word f

Even addressOdd address

31 24 23 16 15 8 7 0An + 3 An + 2 An + 1 An Address

An

An + 4

An + 8

An + 12

Word c Byte b Byte a

Dword d

Dword g Word f Byte e

Dword g

msb lsb

wiki.gsi.de€¦ · AXIS ETRAX 100LX Designer's Reference (February 9, 2006) i Contents 1...

Documents

Transcript of wiki.gsi.de€¦ · AXIS ETRAX 100LX Designer's Reference (February 9, 2006) i Contents 1...