DISTRIBUTION STATEMENT A. Approved for public release as Document #88 ABW-09-4332Distribution is unlimited.

TELA Wideband Array

Demonstration

Thomas W. Dalrymple

Materials Engineer

AFRL/RYDR

6 April 2010

2

Transformational Element Level Array

(TELA) Testbed

6 April 2010

Wideband Arrays

Miniature WidebandReceivers

Wideband Digital Beamforming

Integrated RF Front-end MMICs

Sub-System IntegrationSub-System Modeling

Sub-System Testing

Multiple High-gain beams

Improved Range Resolution

Plastic Packaging

TDU MMIC

Wideband SIGINTDigitalReceiver

Centralized Beamformer

OutputBeam

x1 x2 xN

y = wTx

Weight and Sum

3

Time Delay Beamsteering

• Requirements

– 1 – 8 GHz RF Bandwidth (BW)

– >2 GHz Instantaneous BW

– ± 60° scan

– 8 element linear array

• Element Level Phase Shifting

– Traditional Approach

– Frequency Dependent

– Leads to beam squint over instantaneous bandwidth

• Element Level Time Delay– Frequency Independent

– Accurate beam pointing over broad frequency range

– Avoid Elaborate Calibration Schemes

– Wideband Replacement for Phase Shifters

6 April 2010

4

TELA TDU Module

• Module developed by AFRL & Cobham (formerly REMEC & M/A-COM)

• Flat insertion loss vs. frequency and delay state

• 100 MHz Serial Control ASIC with Cyclic Redundancy Checking

• Plastic QFN Packaging for light weight and reduced cost

– Compared to traditional Ceramic Packaging

• 8-bit True Time Delay Unit

– 764-ps total delay, 4-ps LSB

• 0.8 – 8 GHz Frequency Coverage

• 6-bit Attenuator

– 31.5-dB total attenuation, 0.5-dB LSB

• 20-dB gain, 5-dB NF

• 18-dB I/O return loss

• 13 mm x 9 mm

6 April 2010

5

Measured On-Wafer Gain and Return Loss of

TDU MMIC for Cardinal Time-Delay States

0 1 2 3 4 5 6 7 8 9 10 11 12

Frequency (GHz)

-40

-20

0

20

40

Input RL

Output RL

Res

po

nse

(d

B)

Gain

On-Wafer RF Probe Data; No Bond Wires; T = 25 C; VD = +3.3 V, ID = 150 mA;-3.3 V supply current – 2 to 4 mA

The gain change from reference for any cardinal state (4-, 8-, 16-, 32-, 64-, 128-, 256 psA and 256 psB bits) is typically less than 0.5 dB. There is a very small change in the input and output return loss.

6 April 2010

6

Measured Time-Delay of

Packaged TDU Module

0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8

Frequency (GHz)

0

200

400

600

800

1.0 GHz16.3

1.0 GHz31.1

1.2 GHz63.0

1.0 GHz123.7

1.0 GHz264.1

1.0 GHz767.5

4.5 GHz16.5

4.5 GHz32.3

4.5 GHz780.9

4.5 GHz61.0

4.5 GHz124.5

4.5 GHz260.6

Tim

e-d

elay

(p

s)

6 April 2010

7

AFRL Control ASIC

• Serial to parallel control using daisy chain architecture

• Low cost scalable control approach

• Reduces routing complexity vs. competing control techniques

6 April 2010

Legend:

Data

Latch

Master Latch

SL

SL

SL

SL

SL

SL

SL

SL

SL

MS MS MS

OL

FPGA

Beamsteering Commands

(Ethernet)

3x3 Phased Array

8

Time Delay Array – 1D Scan

• Time Delay Array is capable of 1-D Scan across Azimuth

• Array combines 8 columns of 16 elements each into 8 outputs received by the TDU board which forms beams along the azimuth direction

256 Element Wideband ArrayCenter 8 Columns Used

8 x 1 8 1

Power & control lines

8 Element TDU Board 8:1 Combiner Board

PC Motherboard FPGA

Ethernet

6 April 2010

9

Test Setup

Phased Array Nearfield Calibration and Holography (PANCHO) Chamber

6 April 2010

10

TDU Array Patterns - Boresite

Initial Patterns2 GHz

Instantaneous BW

6 April 2010

11

TDU Array Patterns - 26° Steer

TDU Steered Pattern

Ideal Pattern

Cable Steered

6 April 2010

12

TDU Array Patterns - 45° Steer

TDU Steered Pattern

Ideal Pattern

Cable Steered

6 April 2010

13

Summary

• Initial demonstration of time delay technology has

proven successful

• Future efforts

– 16 Element Array

– 2D Scan Array with 64 elements

– Multi-beam array demo

6 April 2010