What is the Electronics Resurgence Initiative? - DARPA · PDF fileWhat is the Electronics...
Transcript of What is the Electronics Resurgence Initiative? - DARPA · PDF fileWhat is the Electronics...
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What is the Electronics Resurgence Initiative?
Defense Industry Executive SummitJuly 11, 2017
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Reference herein to any specific commercial product, process, or service by trade name, trademark or other trade name, manufacturer or otherwise, does not necessarily constitute or imply endorsement by
DARPA, the Defense Department or the U.S. government, and shall not be used for advertising or product endorsement purposes.
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Program managers from the community…
on a temporary 3 to 5 year assignment…
executing ~$3 billion in the hands of ~90 PM’s through ~250 programs…
to eliminate technical surprise.
Programs / Challenges
National Defense NeedsCommercial Impact
Academia CommercialSector
Defense Industry
How do we operate?
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Grand Challenge(2005-2007)
Today2005 2015 2020
DARPA has evolved to using challenges
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2014 2015 2016 2017
2015
Robotics Challenge
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Video not included
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Cyber Grand Challenge
2014 2015 2016 2017
2016
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Spectrum Collaboration Challenge
2014 2015 2016 2017
2017
DARPA Spectrum Challenge
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Video not included
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Grand Challenge(2005-2007)
Robotics Challenge (2012-2015)
Cyber Grand Challenge (2016)
Spectrum Collaboration Challenge (2017-2018)
Today2005 2015 2020
Exploring the capabilities of learning / autonomy and
their societal impact
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But, we still have a long way to go
A revolution in sensing and processing is requiredDISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.
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P.1 P.2
Everyone focuses on page 2“…The complexity for minimum component costs has increased at a rate of roughly a
factor of two per year (see graph)…”
Fig.1
The miracle of Moore’s Law has taken us incredibly far…
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Electronics, April 19, 1965: Cramming More Components onto Integrated Circuits; Gordon Moore
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VIII. DAY OF RECKONING
Clearly, we will be able to build such component-crammed equipment. Next, we ask under what circumstances we should do it. The total cost of making a particular system function must be minimized. To do so, we could amortize the engineering over several identical items, or evolve flexible techniques for the engineering of large functions so that no disproportionate expense need be borne by a particular array. Perhaps newly devised design automation procedures could translate from logic diagram to technological realization without any special engineering.
It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected. The availability of large functions, combined with functional design and construction, should allow the manufacturer of large systems to design and construct a considerable variety of equipment both rapidly and economically.
DesignQuickly enabling
specialization
ArchitectureMaximizing specialized
functions
Materials & IntegrationAdding separately packaged novel materials and
using integration to provide specialized computing
P.3
But nothing lasts forever
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Electronics, April 19, 1965: Cramming More Components onto Integrated Circuits; Gordon Moore
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Sparse + Dense
Compiler-directed Hardware Reconfiguration
Pseudolithic Integration Specialized Hardware Blocks Software Hardware Co-design
3.0 µm
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Where are we heading?Sowing the seeds for a revolution in processing
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Programs / Challenges
National DefenseNeeds
CommercialImpact
Academia CommercialSector
Defense Industry What is the initiative?
Program managers hired directly from the electronics community…
Aligning incentives as we both stare at an uncertain future
Co-developing electronics to manage the coming inflection to support both a national electronics
base and national defense
Electronics Resurgence Initiative
Beyond Scaling:Materials
ArchitecturesDesign
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MTO ELECTRONICS RESURGENCE INITIATIVE TIMELINE
OctSepAugJulJunMay Dec Jan Apr
Launch, Learn, & Organize
6/21: Industry Discussion7/11: Defense Base Summit
Open Competition
9/12: Proposals Requested (Expected)
Complete Contracting
4/20: Start Work
Summer of Listening
7/18: 2-day workshop onMaterials, Architectures, Designs
V
V
Nov
$75 Million Additional in FY18 Budget
Press Release Announcing Initiative
Happening Now Summer 2017 Fall 2017 Spring 2018
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materials architectures designs
Foundational
Industry Engagement
National Electronics Capability
JUMP + Traditional Programs
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$141 million in Current Efforts (FY18)
$75 millionOf New Funding
(FY18)
$216 MILLION TOTAL (FY18)
materials architectures designs
JUMP + Traditional Programs
NATIONAL ELECTRONICS CAPABILITY
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2025 - 2030
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materials architectures designs• JUMP – Joint University Microelectronics Program
• CHIPS – Common Heterogeneous Integration and IP Reuse Strategies
• HIVE – Hierarchical Identify Verify Exploit
• L2M – Lifelong Learning Machines
• SSITH – System Security Integrated Through Hardware and software
• N-ZERO - Near-Zero Power Radio Frequency Receivers
• CRAFT – Circuit Realization at Faster Time Scales
Traditional Programs Currently Funded
JUMP + Traditional Programs
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Joint University Microelectronics Program(JUMP)
RF to THz Distributed Computing
Cognitive Computing
IntelligentMemory/Storage
Advanced IC Architectures
Devices/Materials
Industry
40% 60% World Class Idea Generation
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Stanford University3D System on Chip
Joint University Microelectronics Program (JUMP)
Linton SalmonDARPA Program Manager
The intersection of industry, academics, and government
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National Electronics Capability
TomorrowWorld Class
Translation of Technology
World Class Idea Generation
IndustryGovernment,
Commercial, and Defense
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Stanford University3D System on Chip
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Circuit Realization at Faster Time Scales (CRAFT)
Driving a design methodology that can be used to quickly design flexible, high
performance custom integrated circuits using leading-edge CMOS technology while
driving DoD to use the best commercial fabrication and design practices
Sharply reduce barriers to DoD use of leading-edge custom integrated circuits (ICs) for orders-of-magnitude higher performance
at low power for DoD systems.
DoD (Today)
CRAFT(Future)
Chip Design and Fabrication Time (weeks)
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Hierarchical identify Verify Exploit (HIVE)
Enabling the DoD to perform graph analytics at the edge of the battlefield and not rely on datacenters back in the United
States; providing greater situational awareness in addition to the ability to do
real time sensor fusion and exploitation at the lowest echelons
Next-generation server processor designed to find patterns in streaming data sets by using graph analytics
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Lifelong Learning Machines (L2M)
Pursuing approaches for biologically-inspired artificial intelligence utilizing
flexible models to continue adapting during execution in the field
Continual Learning
Mechanisms
Fundamentally new machine learning mechanisms for machines that learn continuously as they operate
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Secure Processing Architecture by Design (SPADE)
Incorporating untrusted commercial devices with proprietary trusted government
designs
Technology-driven security techniques can enable new DoD options for acquiring state-of-the-art, commercial
microelectronics
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Common Heterogeneous Integration and IP Reuse Strategies (CHIPS)
Market IP Proprietary IP
6 –
12 W
eeks
Integrate
CHIPS enables rapid integration of modular circuits at the die level
Developing the design tools and integration standards required to demonstrate modular
integrated circuit (IC) designs that leverage the best of the DoD and commercial designs and
technology
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System Security Integrated Through Hardware and software (SSITH)
Develop hardware design tools to provide inherent security against hardware
vulnerabilities exploited through software in DoD and commercial electronic systems
Hardware protectionFlexibleScalableIntegrated architecture
Circuit design tools that can be used to implement security architectures in DoD and commercial integrated circuits
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8/22/2016JUMP
program approved
MTO Electronics Timeline
4/26/2017CHIPS Announced
4/26/2017SSITH BAA Released
2016 2017 2018 2019
1/13/2017HIVE Funds Released
JUMPUniversity Driven
Beyond ScalingIndustry Driven
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3/18/2016CRAFT Kickoff
3/23/2017SPADE Kickoff
1/19/2017L2M Program Approved
Today
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Andreas OlofssonDesignsFrom Kickstarter to Supercomputer
JUMP + Traditional Programs
materials architectures DESIGNS How do we lower the design barrier to specialization?
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2012 Parallella Kickstarter
16-core65nm
Processor(<2W)
World’s first crowd-funded chip
Parallella.org
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0
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40
60
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180nm 130nm 90nm 65nm 45nm 28nm 16nmIP Design Verification Masks
System-on-chip design costs are inhibiting US innovation
DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.
Milli
ons
of d
olla
rs
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1
10
100
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
1,000,000,000
10,000,000,000
100,000,000,000
0.00
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0.30
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0.50
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0.90
1.00
1960 1970 1980 1990 2000 2010 2020Automation Transistors
Auto
mat
ion
Tran
sisto
rs8088
4004
486Pentium4
Westmere
Design: The curse of Moore’s Law
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2018
*
100%
0%
90%80%70%60%50%40%30%20%10%
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
*20
15*
2016
*20
17*
Average # of IP blocks
Aver
age
% o
f reu
sed
IP b
lock
s250
200
150
100
50
0
52 blocks
110 blocks
55 blocks
18 blocks
Research Corporation, 2014
2016• 175 IP blocks• 80% reuse
IP: Reuse and complexity growth
Percent of reuse Avg. number of IP blocks
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Verification: “Software is eating the world”
Video Display
Wireless
TV Decode
xDSL
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Masks: Expensive but manageable
$0
$2
$4
$6
$8
$10
$12
$14
$16
1 5 25 125 625
100,000 units10,000 units1,000 units100 units
Chip size
Cost to produce(millions)
Chip production costs
The total cost of producing 10,000 units of an “Apple-A9” grade 14nm custom SoCs is only $1.8M!DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.
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How do we get out of the SoC tar pit?
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COTS FPGAs are great, but not appropriate for every application!
$-
$100
$200
$300
$400
$500
$600
$700
2001
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2005
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2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
ASIC & ASSP FPGA
Milli
ons
Global military/aeronautics shipments
Source: Multiple industry market trackers & DMEA internal data from FPGA manufacturers
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Sprouts of hope…
Process TSMC 16FF+Transistors 4.5B
Die Area 117 mm2
Performance 2 TFLOPSRTL to GDS ~24hrsEngineers 1
Process TSMC 16FF+Transistors 3.3B
Die Area 117 mm2
Apple A10 SoC 1024-core 64-bit Microprocessor
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My Questions
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Industory Total CostDoD Total CostIndustry Production CostDoD Production CostStatus
Quo
100% Automation2X silicon Area
100% Automation1X silicon Area
Milli
ons
of d
olla
rs
IDEA research year
Can DARPA help industry get over the design cost hump?
Chip costs (design + production)
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Can we leverage best practices from other industries?
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Should we pursue an open-source strategy?
Facebook Market Cap: $433B!
LINUX
MemCache MySQL
Apache PhPThrift
Cassandra Jenkins
Yoga
…
Facebook Code
User Content
$15B+Open source
codebase
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Can we automate “all of it”?
Machine generated chip and package layout
Intent driven system generation
Machine generated board layout
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Can we design by intent?
Interface5V,
Ethernet, USB,
HDMI, 5V
Processor: 2 x ARM-A9,
FPGA,20 GFLOPS
Memory:1GB DDR3
128MB Flash
Power:5V in:
1.8V. 2.5V, 3.3V out
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Can we reinvent SiP and PCB design?
Open Parts DB
Intent Pruning
Sche
mat
ics
F1 F2
F1 F2
GoalOptimizer
Sche
mat
ic
Layout Generator
Future
Today• 100% Manual• Error prone• Rarely optimal
ManualPart Selection Manual Schematic Manual Layout
Sche
mat
ics
SystemGenerator
New Concept: Machine synthesized board from intent and open COTS parts library.
Potential SolutionsInexact Description
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Can we fully automate analog layout?
Assign Strategies
Today FutureDesigner provides manual constraints to layout person (or tool)
Centroid Mirroring Isolation
Common Vocabulary of Strategies
VDD
IBIAS
VSS
VIN VIP
VOUT
Place dummies, interdigitize
Commoncentroid layout
Max 10um from main supply, 0.5um width
VDD
IBIAS
VSS
VIN VIP
VOUT
Circuit Classifier
Auto-Placement
Auto-Routing
Model Training
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Can we augment design teams with machine learning?
ControlDatapath
• Improved power, performance, area possible with custom datapaths
• Not possible in existing EDA solutions without significant manual work
Today Future
• Automatic datapath circuit classification
• Circuit specific cost models• Multi-strategy digital placers
Significant wire length
improvement[Pan, UT Austin]
Datapath
Leverage graph pattern asymmetries
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Will modern SoC design ever look like this?
Easy and funRobust and simple
plug and play interfaces
Black box encapsulation
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…when I leave DARPA…
48 Hours
Code EDA
My DARPA dream…
DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.
tovatech.com
keysight.com
shutterstock.com fedex.comamazon.com
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How do we integrate new materials for
specialized functions?JUMP + Traditional Programs
MATERIALS architectures designs
Dan Green / Linton SalmonMaterialsSteering the science of materials to commercial product lines
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300mm diameter Si CMOS wafer Si (45nm), InP (TF5 HBT), GaN (GaN20 HEMT)
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DAHI Program DAHI Program
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University of Massachusetts, Amherst University of California, Santa BarbaraStanford University
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JUMP + Traditional Programs
materials ARCHITECTURES designs
How do we manage the complexity of
specialization with new architectures?
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GNU Radio
DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.
Tom RondeauArchitecturesThe intersection of connectivity and computation
Wade ShenArchitecturesThe intersection of big data and architecture
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General Purpose Processor
Portable and programmable
Programmable Logic
concurrent stream processing
Graphics Processing UnitEmbarrassingly
Parallel
Digital Signal Processor
Optimized serial processing
AcceleratorThe best at one thing
Math Domains• Dense Linear Algebra• Transforms• Learning, optimization
Data Representation• Data Structures• Fixed point math• Numerical precision /
quantization
Programming Tools• Compilers• Debuggers• Performance
measurements/tools
Performance• Power• Bandwidth• Latency
Intel.com Xilinx.com nvidia.com analogdevices.com
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materials architectures designs
JUMP + Traditional Programs
NATIONAL ELECTRONICS CAPABILITY
MaterialsHow do we integrate new materials for specialized functions?
ArchitecturesHow do we manage the complexity of specialization with new
architectures?
DesignHow do we lower the design barrier to specialization?
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The backdrop to this initiativeCommercial involvement around the world
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The United States has notable advantages1:
• Top 3 fabless companies
• Top 3 electronic design automation companies
• Two of the top 3 equipment manufacturers
• Top integrated device manufacturer
• Three of the 5 leading-edge foundries
U.S.-headquartered firms account for half of global semiconductor sales
1 2017 PCAST report “Ensuring Long-Term U.S. Leadership in Semiconductors”
1
2
4
2 , 5
6
7
4
The headlines are focused on China:
New York Times; Forbes; Image Courtesy Getty Images
Although the U.S. electronics advantage is not without challenges, we have the edge in microelectronics
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Leveraging commercialcapabilities
Secure processors
ARMHopu InvestmentsShenzhen Gov’t
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Models for engagement?An introduction to current corporate engagements at DARPA
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(HIVE) (CRAFT) (Possible)
Defense and National Needs
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MTO has started new partnerships with the commercial sector in areas of shared interest
Defense IndustryApplication layer
Traversing a one trillion edge graph
- Intel- Qualcomm
- Northrop Grumman
- Pacific Northwest National Laboratory- Georgia Tech
Universities and LabsSoftware
Commercial sectorHardware
HIVEHierarchical
Identify, Verify, Exploit
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© 2017 Intel CorporationIntel’s DARPA HIVE Program 61
Intel and DARPA: HIVE for Graph Analytics
Josh Fryman, PhD, Senior Principal EngineerPI for Intel’s DARPA HIVE program
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© 2017 Intel Corporation – PUBLIC RELEASEIntel’s DARPA HIVE Program62
Graph Analytics: DARPA’s “Big Bet”
• Thought leaders in academia, gov’t, industry believe that unstructured data will be encoded into sparse matrices and analyzed
• The world is inherently sparse, not dense• Stages of processing and compute types
alternate• Emerging future opportunities, insights
• DARPA HIVE is a proposal to build a Graph Analytics Processor
• Goal: 1,000x superior GTEPS processing “efficiency”
• GTEPS = Giga-TEPS = Traversed Edges per Second
• Existing workloads and state-of-the-art to be used as baseline
DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.
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© 2017 Intel Corporation – PUBLIC RELEASEIntel’s DARPA HIVE Program63
The Challenges
Parallel memory access enables random access
Sparse Matrix data format/operationsmore efficient processing
Memory SystemProcessor Design Interconnect Design
Scalable interconnectBalance energy/execution time consumed in data transfer
Scale poorly for data movement problems
Optimized for dense math and cache use
Graph problems driven by “random accesses”
~96% of time is spent moving data
Credit: Trung Tran, DARPA
0%
20%
40%
60%
80%
100%Memory Transfer
Processor Idle
Processor Active
Pointer-chasing dominates Large graphs don’t partition
> 1 trillion edges> billion edgesDISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.
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© 2017 Intel Corporation – PUBLIC RELEASEIntel’s DARPA HIVE Program64
HIVE Organization
• Pros:• No ITAR• No security clearances• No single solution• Bootstrap ecosystem
• Cons:• Borders are “fuzzy”• Baseline opaque• Lines may not be good
• Benefit is worth risk
TA1Vendor 1
TA1Vendor 2
TA2Vendor 3
TA2Vendor 4
TA3Vendor 5
TA3Vendor 6
Arch OnlyNo SW, No Algs
System SW OnlyNo Arch, No Algs
Algs OnlyNo Arch, No SysSW
Assembler to DSLMUST be OSS
App to AlgorithmCLASSIFIED
Firewall Firewall Firewall
Si to BIOSEmulator + Si Chip
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© 2017 Intel Corporation – PUBLIC RELEASEIntel’s DARPA HIVE Program65
Research vs. Product
• Intel doesn’t do “design for hire”• Challenges must align with one of
• Product Plans• Emerging opportunities• Risk reduction in solutions
• Product teams must be cautious• Massive (legacy) ecosystem• Cannot break things
• IP protections paramount• World-wide ongoing concerns
• Research needs to push edges• Challenges are dynamic
• Emerging threads• Risk-reward scenarios• May not succeed
• R&D has to be aggressive• Add risk to cautious plans• Success maps to product quickly
• Contract structure critical• IP terms at critical “cost-share” %
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© 2017 Intel Corporation – PUBLIC RELEASEIntel’s DARPA HIVE Program66
Industry – Government: Both Can Align
• Commercial workloads abound• PageRank / Search• Cyber Attack Recognition• Medical records• Genomics / cancer• Financial / fraud• Natural language processing• Associative memories / AI• Predictive failures and responses• Many-to-Many, not 1:1 or 1:n
• Government concerns map• Same• Same• Same – for military medical needs• Similar – general pattern matching• Same – for procurement/contracts• Same• Same• Same• Same
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Defense Industry
Comm
ercial Sector
Universities
75% Reduction in DoD Product Cycle Time
Defense, university, and commercial sectors working side-by-side towards a common goal
-Northrop Grum
man
-Boeing
-Harvard, UC-Berkeley
-UCSD, CM
U
-NVIDIA
MTO has started new partnerships with the commercial sector in areas of shared interest
DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.
Circuit Realization At Faster
Timescales(CRAFT)
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68@NVIDIA 2017
NVIDIA’s DARPA Programs
Ubiquitous High-Performance Computing (UHPC) – 2010-2012
Power Efficiency Revolution for Embedded Computing Technologies (PERFECT) – 2012-2015
VirtualEye – 2014-2017
Circuit Realization at Faster Time Scale (CRAFT) – 2016-2018
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69@NVIDIA 2017
Sample of NVIDIA PERFECT Technologies
High-Performance Parallel AlgorithmsThrust
CUB
SRAM and Signaling Circuits
On-chip Charge Recycling Signaling<10fJ/bit-mm
Low-voltage SRAM AssistsReduced Vmin: 0.75V 0.45V
Patch-based Image Processing Architectures
CuFFT
CUSPARSE
cuDNNDISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.
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70@NVIDIA 2017
VirtualEye – An Offshoot of PERFECTDemonstrate image processing capabilities enabled by PERFECT-era technologies
live event
Virtual View
Live Event: multiple cameras • Capture event with multiple (stereo) cameras
• Reconstruct 3D structure in real-time
• Stream to remote user
• User selects virtual view
Real-time virtual views of events constructed using live input streams from multiple sensors, including mobile UAVs.
Vision
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71@NVIDIA 2017DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited. Video not included
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72@NVIDIA 2017
VirtualEye – An Offshoot of PERFECTDemonstrate image processing capabilities enabled by PERFECT-era technologies
live event
Virtual View
Live Event: multiple cameras • Capture event with multiple (stereo) cameras
• Reconstruct 3D structure in real-time
• Stream to remote user
• User selects virtual view
Real-time virtual views of events constructed using live input streams from multiple sensors, including mobile UAVs.
Vision
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73@NVIDIA 2017
DARPA CRAFT Program
CRAFT objectivesReduce custom IC design time by 10x and increase design robustnessReduce technology node migration effort by 80%Ensure high IP reuse for DoD systems
ApproachRaise design abstraction level (hierarchy, generators, modern SW engineering)Automate front-end design flow, isolate process-specific design steps, and leverage common IP blocks ported across processes
Program structurePhase 1: 5 performers develop methodology and produce chips (MPW run)Phase 2: <5 performers (1) enable outsiders to test methodology, (2) port designTeams: industry/academic partnerships
Circuit Realization at Faster Time Scale
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74@NVIDIA 2017
MATCH: Modular Approach To Circuits and Hardware• Object-oriented HLS-based (OOHLS) Flow
• C++/SystemC language for design• HLS tools automate pipelining, resource scheduling, FSM design• All communication through Latency-Insensitive (LI) channels
• Developed MatchLib: OOHLS library of hardware components• Developed a unified SystemC/C++ architecture modeling framework
Partnership to demonstrate design flow
NVIDIA Harvard
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75@NVIDIA 2017
MATCH: Modular Approach To Circuits and Hardware
Scalable automated Modular FloorPlanner (MFP) based on total wire-length optimization
Correct-by-construction top-level timing with fine-grained Globally-Asynchronous-Locally-Synchronous (GALS) Clocking
NVIDIA
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76@NVIDIA 2017
NVIDIA’s Approach to Gov’t Partnerships
Gov’t and NVIDIA must be aligned on program objectives
Research must be aligned with technical/strategic direction of the company
Results must have the potential for transferto NVIDIA product teams
Vehicle for direct collaboration with universitiesStanford
UniversityThe University of
California, BerkeleyUniversity of Pennsylvania
GeorgiaTech
HarvardUniversity
The University of Utah
The University of Texas at Austin
University of Virginia
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Defense Industry
Comm
ercial Sector
Universities
Beta release of design flow in October 2017
Defense, university, and commercial sectors working side-by-side
towards a common goal
Circuit Realization At Faster
Timescales(CRAFT)
-Northrop Grum
man
-Boeing
-Harvard, UC-Berkeley
-UCSD, CM
U
-NVIDIA
MTO has started new partnerships with the commercial sector in areas of shared interest
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So how do you get involved?Timeline and structure
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Proposals Requested
Proposals Submitted
Partners Selected
Funding Released
MTO ELECTRONICS RESURGENCE INITIATIVE TIMELINE
OctSepAugJulJunMay Dec Jan Apr
Launch, Learn, & Organize
6/21: Industry Discussion7/11: Defense Base
Summit
Open Competition
9/12: Proposals Requested (Expected)
Complete Contracting
4/20: Start Work
Summer of Listening
7/18: 2-day workshop onMaterials, Architectures,
Designs
V
V
Nov
Happening Now Summer 2017 Fall 2017 Spring 2018
7 months
Defense Base Summit
2-day Workshop
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MTO ELECTRONICS RESURGENCE INITIATIVE POINTS OF CONTACT
• Commercial Engagement Lead• Mr. David Henshall• [email protected]
• Architectures Thrust Lead Program Manager (PM)• Dr. Thomas Rondeau• [email protected]
• Design Thrust Lead PM• Mr. Andreas Olofsson• [email protected]
• Materials Thrust Lead PM• Dr. Daniel Green• [email protected]
• Joint University Microelectronics Program PM• Dr. Linton Salmon• [email protected] For general questions, please contact Mr. David Henshall
For thrust-specific questions, please contact the relevant PM
DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.
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DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.