What is PCI Express(R) 3.0? What Needs To Be Tested? And ...

2011/7/28

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What is PCI Express(R) 3.0? What Needs To Be

Tested? And The Test Challenges!

Agenda

What is new about PCI Express (R) 3.0

Comparison to PCI Express (R) 2&1 Testing

What needs to be tested in PCI Express (R) 3.0

LeCroy involvement with PCI-SIG

Challenge with PCI Express (R) 3.0 Testing

Transmitter Test Challenges

Receiver Test Challenges

Dynamic Equalization Test Challenges

PLL Bandwidth and Peaking Test

SEG Compliance Testing

SEG Electrical Test Specifications

5 Areas of Testing

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PCIe Market Outlook

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2002 2004 2005 2006 2007 2008 2010 2011 2012

Early Adopters

for PCIe 3.0

PCIe 2.0 shipped on

systems deployed in

2007 and 2008Growth of PCIe 1.0

market

Early Majority for

PCIe 3.0

Mainstream

PCIe 3.0

shipping

PCI Express 3.0 Key Industry Milestones

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Q3 Q3 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

2007 2008 2009 2009 2009 2010 2010 2010 2010 2011 2011 2011 2011 2012

PCI Express 3.0 Specification (.7)


PIPE 3.0 Specification (.7)

LeCroy Announces PeRT3 Phoenix for PCIe 3.0 Rx Testing

LeCroy Ships First PeRT3 Phoenix

LeCroy Announces PCIe 3.0 End to End Test Solution

PCI Express 3.0 Specification (1.0)


First FYI Compliance Test

Electrical Test Spec. 0.5

Second FYI Compliance Test

Next FYI Compliance Test

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PCI Express 3.0 Applications

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Gen2

Server and Desktop High End Products

Switches, Servers, IO Boards targeted at PCIe

3.0 for 2011-13

Consumer Products

Workstation and graphics cards targeted at PCIe

2.0 for now.

Embedded Products

Telecommunication servers using Gen1/Gen2

Military systems using Gen1/Gen2

Embedded processors/ASICs going from PCI to

PCIe 1.1

Gen3

PCI Express 3.0 Specification Changes

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New Electrical Requirements

Power

Jitter

Sensitivity

32-Bit Support

Equalization

Digital Controller operates

at 2x data

Double the data path

Double the Clock

Removal of K-Codes

Change LTSSM

Application

Link

Transaction

Physical

Mechanical

Logical

Electrical

PIPE

Gen1/Gen2 Application

Link

Transaction

Physical

Physical Coding Sub-

layer

Digital Controller

Physical Interface

(PIPE)

PCS Layer

Electrical Sub-block

Rx Tx

Lane

Gen3

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PCI Express 3.0 Compared to PCIE 2&1

PCI Express 2.0 PCI Express 3.0

Bit Rate 5Gb/S 8Gb/s

Encoding/Decoding 8B/10B 128B/130B

Overhead 20% 1.5625%

Scrambling Optional Always

Effective Bit Rate 4Gb/s per lane 7.88Gb/s per lane

Transmission path Same as Gen1 Same as Gen1 and Gen2

Receiver Testing Informative Required


PCI Express 3.0 PHY Layer

IC System Board PCIE Connector Plug-In Card IC

Signal degrades over long transmission path and connectors


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How does PCI Express 3.0 Work

8Gb/s Transmitter with enhanced jitter

performance

Transmitter Equalization to reverse the effects

of the lossy channel

Smarter way to encode the signal for higher

transmission throughput

8Gb/s Receiver with better receiver jitter

tolerance performance

Improved Clock Data Recovery functions to filter

low frequency jitter

Adaptive CTLE and DFE capabilities to open the

eye at the end of the channel



TxEQ RxEQ

Tx implements a FIR based

equalization

1 of 11 presets are used during

TxEQ process

Equalization is based on 3 tap (pre

cursor + post cursor) to create de-

emphasis and pre-shoot

Rx implements a behavior

equalization algorithm

Behavorial CTLE

Behavioral DFE

Behavioral CDR

Rx with send TxEQ preset requests to Tx to

optimize TxEQ to achieve Dynamic

Equalization through link initialization


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TxEQ RxEQ

TxEQ – De-emphasis and Pre-shoot

RxEQ - CTLE

RxEQ – DFE


PCI-SIG and LeCroy

1. PCI-SIG EWG, CEM, SEG

LeCroy is an active contributing member to the PCI Express working groups.

2. New SEG electrical spec v. 0.5

There are 3 main work groups that contributes to the creation of the PCIE

Specifications

3. Customer base

80% of PCI-SIG Board Member Companies have selected the LeCroy solution

for testing PCI Express 3.0 as well as most early adaptors

Working with more key PCIe accounts to increase our exposure

4. Upcoming Events

Weekly PCI-SIG workshop meetings

Working closely with Intel and AMD test labs on initial Gen3 spec validation and

bring up

PCIE Plugfest April 2011 (first time offering FYI testing for PCIe gen3 products)


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PCI Express Specifications


PCI-SIG FYI Electrical Tx and Rx Testing


First PCI Express Gen3 FYI test suite

was offered in April 2011•8 add-in cards were tested

•2 host systems were tested

Second PCI Express Gen3 FYI test

suite was offered in June 2011•11 add-in cards were tested

•4 host systems were tested

Next PCI Express Gen3 FYI test suite

will be offered in Aug 2011•More products are expected for this

workshopPCI Express Gen3 FYI Gold Suite:Suite 1: Transmitter Testing

Suite 2: Receiver Testing

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Test Challenges with PCI Express 3.0

Challenges:

Transmitter Testing

Where to measure the signal? Cannot probe anywhere on the board or the connectors

Normative Jitter measurements are required to be tested at the end of the channel with CTLE and

DFE enabled, preset measurements are required to be tested prior to the channel

How to measure the preset values

How to open the closed eye

Receiver Testing

How to generate all the required jitter sources and signal conditions for PCI Express 3.0

Stressed Eye is completely closed after going through the compliance channel

How to perform PLL bandwidth and peaking measurements

Loopback and Dynamic Equalization

How to put the DUT into loopback

How to complete Dynamic Equalization training with the DUT within the timing requires of PCI

Express 3.0 specification


Transmitter Testing Challenges for PCI Express 3.0

Challenge: Where to measure the signal? Cannot probe anywhere on the board or the connectors.

Solution: PCIE Gen3 test fixtures


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Challenge: Normative Jitter measurements are required to be tested at the end of the channel with

CTLE and DFE enabled, preset measurements are required to be tested prior to the channel

Solution: The measurement tool (Oscilloscope) will embed the spec required channel (s4p) to

simulate the lossy channel and the measurement will be done in the New PCIE Gen3 Sigtest

Software. Sigtest software will also implement the necessary CTLE and DFE filters to open the

eye.


Embed using

EyeDoctor2

Software in the

Oscilloscope


Challenge: How to measure the preset values

Solution: The new Gen3 CLB/CBB has switch that will request the DUT to toggle the 11 different

preset. Then the Oscilloscope can record the waveform for measurements

Preset 4:

0dB de-emphasis

0dB pre-shoot

Preset 0:

6dB de-emphasis

0dB pre-shoot

Preset 7:

6dB de-emphasis

3.5dB pre-shoot


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Challenge: How to open the closed eye

Solution: By trying the different presets and enabling CTLE and DFE, we can open the eye at the

end of the channel for jitter and eye measurements

Signal after captured on the Scope

directly out of the Fixture

Signal after embedding the

channel






Signal after enabling Preset 7 of

TxEQ on transmitter

Signal after enabling TxEQ and

CTLE


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Signal after enabling de-emphasis and pre-shoot on the transmitter

and , enabling CTLE and DFE on the receiver.


Receiver Testing Challenges for PCI Express 3.0

Challenge: Now that receiver testing is required. We need the test equipment to generate different

types of jitter sources and signal conditions to replicate a real PCI Express 3.0 signal

Solution: PeRT3 Phoenix has all the Built-in jitter sources and signal conditioning functions

required for PCI Express 3.0 testing

Signal with All Jitter sources added:

De-emphasis = -6dB

Pre-shoot = 3.5dB

RJ = 2ps RMS at up to 1Ghz

SJ = 13ps at 100Mhz

Differential mode jitter = 14mV and 2.1Ghz

Calibration channel = -20dB

Total Generated Jitter = 0.3UI to 0.35UI +

Channel Effects


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PeRT3 Phoenix Built in Jitter Sources and 3 Tap De-emphasis

Clean Signal at 800mV with Preset 4 Clean Signal at 800mV with Preset 7



Clean eye with no added jitter Adding Rj of 2ps RMS only


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Adding Sj of 0.1UI at 100Mhz only

Adding Differential mode jitter of

>14mV at 2.1Ghz only



Stressed Eye with all generated jitter

Stressed eye after going through

Compliance fixture and long channel


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Challenge: Stressed Eye is completely

closed after going through the

compliance channel

Solution: By optimizing the TxEQ

presets and applying CTLE/DFE on the

Oscilloscope, we can open the eye for

measurements

Effects of the lossy channel

on a PCIE Gen3 compliance

pattern



Stressed Eye after CTLE and DFE on

OscilloscopeStressed Eye after CTLE and DFE

on Sigtest


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Dynamic Equalization Testing Challenges

TxEQ RxEQ

Tx implements a FIR based

equalization

1 of 11 presets are used during

TxEQ process

Equalization is based on 3 tap (pre

cursor + post cursor) to create de-

emphasis and pre-shoot

Rx implements a behavior

equalization algorithm

Behavorial CTLE

Behavioral DFE

Behavioral CDR

Rx sends TxEQ preset requests to Tx during

link initialization, this is called Dynamic

Equalization


Dynamic Equalization Testing Challenges

Challenge: Test equipment must be able to negotiate with DUT and put DUT into loopback mode.

Solution: There are two kinds of loopback mode. 1) Loopback through Configuration and 2)

loopback through full link dynamic equalization negotiation to L0 state. PeRT3 Phoenix can do

both.

Loopback through Configuration Loopback through L0 State


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Dynamic Equalization Process

There are 4 steps in the equalization process:

Phase 0: Transmitter and Receiver preset

sent from Upstream to Downstream in

8b/10b encoding

Phase 1: 8GT/s Link initiated with the preset

(<= 10-4 BER)

Phase 2: Downstream device adjusts

Upstream device’s transmitter output setting.

by sending equalization requests in the

Training sequence, until it obtains optimal

setting

Phase 3: Upstream device adjusts

Downstream devices Transmitter setting by

sending equalization coefficients/presets

11 Presets defined (de-emphasis and pre-shoot)

TS2 Ordered Set used for Phase 0 and TS1 Ordered Sets used for Phases 1..3

Loopback and Receiver Compliance: test equipment is needed to set up the DUT’s Tx using TS1 Ordered

Sets

LeCroy's PeRT3 is capable of this

Challenge: How to complete Dynamic Equalization training with the DUT within the timing requires

of PCI Express 3.0 specification

Solution: PeRT3 Phoenix has the ability to negotiate with the DUT through link equalization training

handshake


Phase 2: Respond to TxEQ Request in time

In order to test the adaptive capabilities of the Receiver Equalizer, the Test Equipment must

be able to accept the optimized Tx equalization requests and transmit the corresponding

de-emphasised signal within 500nS to change to each preset and a total of 12 tries.

Tx

Rx

Test Instrument

Generator

Error Detector

Optimized TxEQ value will

be sent to Test Intruments

Generator will generate de-

emphasized signal based on TxEQ

value (1 of 11 preset values)


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PLL Loopback BW Testing


Frequency (MHz): 3.0

Magnitude (dB): -3.00

Peaking (dB): 0.5

PLL bandwidth and

peaking test is

essentially a jitter

transfer function

measurement for a

specific frequency

range.

PLL Loopback BW Testing


Phoenix will generate 100Mhz clock as the reference

CLK and generate a sweep of SJ frequencies

Oscilloscope takes SJ measurement for each

frequency of SJ generated on the Phoenix

Graph the generated SJ amplitude against measured SJ

amplitude and the result is the jitter transfer functions of

the DUT PLL

Frequency (MHz): 3.9

Magnitude (dB): -3.03

Peaking (dB): 0.5

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SEG Compliance Testing for PCI-SIG Certification (FYI)

According to the SEG electrical test specification version 0.5, there are 5

sections that needs to be tested for PCI Express 3.0 for Add-In cards and

Systems. For the past two PCI-SIG compliance workshops, the Gen3 FYI gold

suites offered testing for section 1 and section 4. Sections 2, 3 and 5 will be

enabled for future workshops.

1. Tx Signal Integrity

2. Tx Preset Test for 8Gbps

3. Tx Link Equalization Response Test for 8Gbps

4. Rx Jitter Tolerance

Jitter Calibration

Jitter Tolerance

Loopback Compliance

5. Rx Link Equalization Test

Receiver Link Equalization Calibration

Receiver Link Equalization Test


SEG Compliance Testing for PCI-SIG Certification





Jitter Calibration

Jitter Tolerance

Loopback Compliance





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Tx Signal Integrity

Signal is captured from Compliance Base Board via SMA cables into

the Oscilloscope

Signal is analyzed using Sigtest software (PCI-SIG)

Sigtest is a built in analysis tool inside LeCroy Oscilloscopes







Jitter Calibration

Jitter Tolerance

Loopback Compliance





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Tx Preset tests

Switch control on Compliance Base Board to request DUT to output

different Tx Equalization presets.

DUT

Preset

Control

switch







Jitter Calibration

Jitter Tolerance

Loopback Compliance





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Tx Link Equalization Test

1) Does the Tx equalization respond to protocol level preset request?

2) Does the preset sent out match the preset requested and within the response

time?

Scope will measure the preset

response and verify

correctness and timing

requirements (<500ns)

Gen2 PCIE DUT

Phoenix will sent Tx preset request after

Gen3 initialization protocols (Protocol

Aware)







Jitter Calibration

Jitter Tolerance

Loopback Compliance





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Phoenix will generate signal

with required jitter profile and

signal shape into the DUT

through the CBB

Rx Jitter Sources calibration setup

Software will control both

the Phoenix and Scope to

automate the calibration

process.

After the signal passes

through the compliance

channel and CBB, signal can

be captured through the

calibration point to be

analyzed by scope


Rx Jitter Tolerance

rx_spkg

cbb_conn2

RX SMP

cbb_conn1TX SMP

Error

Detector

AIC Under Test

Signal

Generator

Sj + Rj +

Diff Noise

Signal with All Jitter sources added:

De-emphasis = -6dB

Pre-shoot = 3.5dB

RJ = 2ps RMS at up to 1Ghz

SJ = 13ps at 100Mhz

Differential mode jitter = 14mV and 2.1Ghz

Calibration channel = -20dB

Total Generated Jitter = 0.3UI to 0.35UI +

Channel Effects


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Jitter Calibration

Jitter Tolerance

Loopback Compliance





PCI Express 3.0 Architecture PHY Test Spec.


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Rx Link Equalization Training

rx_spkg

cbb_conn2

RX SMP

cbb_conn1TX SMP

Error

Detector

AIC Under Test

Signal

Generator

Sj + Rj +

Diff Noise


Conclusion:

Transmitter Testing

PCI Express 3.0 Compliance CLB/CBB are require for compliance testing of Add-in cards and

System products

LeCroy Oscilloscope incorporates Sigtest for real-time automated testing of PCI Express 3.0

signals

Combined with the PeRT3 Phoenix, LeCroy’s total solution makes preset measurement and Tx link

equalization measurements easy

LeCroy digital oscilloscope EyeDoctor II software has the ability to embed/de-embed channel

traces and apply CTLE and DFE filters on PCI Express 3.0 signals

Receiver Testing

PeRT3 Phoenix has all the required Built-in jitter sources and signal conditioning capabilities per the

PCI Express 3.0 specification requirement

PLL bandwidth test can be done by using the Phoenix to generate ref CLK with jitter and scope to

measure the jitter spectrum

Loopback and Dynamic Equalization

PeRT3 Phoenix is the only Protocol Aware Test Equipment in the industry designed for loopback

initialization and true dynamic equalization testing

PeRT3 Phoenix can respond to TxEQ preset request protocols within 500ns and is the only test

equipment that satisfies the PCI Express 3.0 link layer training specifications


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Conclusion:

The Most Comprehensive

and Only Protocol Aware

Test Tools for PCI EXPRESS

Specification Gen 3.0


Questions?

What is PCI Express(R) 3.0? What Needs To Be Tested? And ...

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