Welcome to CSE 143! Microelectronic System Design Spring 2009 Instructor: Rajesh K. Gupta,...
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Transcript of Welcome to CSE 143! Microelectronic System Design Spring 2009 Instructor: Rajesh K. Gupta,...
Welcome to CSE 143! Microelectronic System Design
Spring 2009
Instructor: Rajesh K. Gupta, [email protected]
Welcome!
Course Objective: Provide an introduction to microelectronic system design
Course Orientation: a systems view of the design and design process, not components system engineering issues related to performance, quality automation-centric design: tools and methodologies.
You will not learn: microelectronic device design, physics, process technology circuit, logic modeling, design, synthesis, simulation computer architecture CAD algorithms, writing CAD tools.
You should get skills in HDL-based circuit, system modeling, synthesis, optimization.
Course Organization
There are three basic parts to the course Review of microelectronics, circuits, process technology Structured VLSI design: design styles and global issues HDL-based modeling, synthesis and optimization
Not necessarily covered in that order
Course logistics described on the class web-page: http://mesl.ucsd.edu/gupta/cse143.html
Section ID: 656577 Lectures: Tu/Th 5-6:30PM CENTER 217A Office Hours:
Wed 2-4, call or drop by (822-4391, CSE 2120)
Lectures
1. Welcome, Introduction to Microelectronic Circuits and Systems (Thursday, March April 2, 2009)
2. Review of Microelectronic Processing and Devices 3. Circuit Styles, Structured VLSI Design 4. Clocking 5. Microsystem Modeling using HDLs 6. Simulation versus Synthesis using VHDL 7. From Modeling to Circuit Synthesis: Global Issues 8. Design for Low Power 9. Architectural Designs 10. Design Verification 11. Design for Test
Questions?
Three Trends Driving Microelectronic Systems Design
Trend 1: Relentless Digitization of Signals and Systems
Courtesy: Paul Gray, UC Berkeley (ISSCC97)
1. GaAs, Si Bipolar 2. Si Bipolar, BiCMOS 3. CMOS
Courtesy: Paul Gray, UC Berkeley (ISSCC97)
1. GaAs, Si Bipolar 2. Si Bipolar, BiCMOS 3. CMOS
Graphics ControllerGraphics ControllerCellphone BasebandCellphone Baseband
Microelectronic System Trends -- 2
Trend 2: increasing use of “embedded intelligence” variety of (multiple) compute engines available on-chip
The consequence: smart “spaces”, intelligent interfaces, sensor networks Integrated circuit chips are driving tremendous capability increases
Microelectronic System Trends -- 3
Trend 3: Networking of embedded intelligence multiple comm. front-ends, networking available on-chip
Pentium 3 & Pentium 4
42M transistors 217 mm^2 die 0.18-micron process 2GHz clock
28.1M transistors 106 mm^2 die size 0.18 micron, 6-layer metal CMOS
Source: Mani Srivastava, UCLA
Microprocessors
Adapted from Irwin & Nayaranan’s Slides from PSU. Copyright 2002 J. Rabaey et al."
Moore’s Law Defines The Competitive Necessity
40048008
80808085
8086286
386486 Pentium ® proc
P6
1
10
100
1970 1980 1990 2000 2010
Year
Die
siz
e (m
m)
~7% growth per year
~2X growth in 10 years
Die size grows by 14% to satisfy Moore’s LawDie size grows by 14% to satisfy Moore’s Law
Courtesy, Intel
40048008
80808085 8086
286386
486Pentium® proc
P6
0.001
0.01
0.1
1
10
100
1000
1970 1980 1990 2000 2010
Year
Tra
nsi
sto
rs (
MT
)
2X growth in 1.96 years!
Transistors on lead microprocessors double every 2 yearsTransistors on lead microprocessors double every 2 years
Courtesy, Intel
Lead microprocessors frequency doubles every 2 yearsLead microprocessors frequency doubles every 2 years
P6
Pentium ® proc486
38628680868085
8080
80084004
0.1
1
10
100
1000
10000
1970 1980 1990 2000 2010
Fre
qu
ency
(M
hz)
2X every 2 years
Courtesy, Intel
P6Pentium ® proc
486
3862868086
80858080
80084004
0.1
1
10
100
1971 1974 1978 1985 1992 2000Year
Po
we
r (W
att
s)
The ITRS: Tao of Scalinghttp://public.itrs.net
Source: Ken Yang, UCLA
2007 0.065 micron
6.7 GHz on chip clock 9 wiring levels 600-3000 pins Vdd=0.7-1.1V
3.5W / 104W / 190W DRAM:
4.29 Gb/chip, 183 mm^2, 2.35 Gb/cm^2 MPU
386 Mtrans/chip, 140 mm^2, 276.1 Mtrans/cm^2
Design Abstraction Levels
SYSTEM
GATE
CIRCUIT
VoutVin
CIRCUIT
VoutVin
MODULE
+
DEVICE
n+S D
n+
G
Adapted from Irwin & Nayaranan’s Slides from PSU. Copyright 2002 J. Rabaey et al."
Design Process
Conceptualization: function & structure HLM, behavioral modeling
Architecture: structure and organization microarchitectural implementation
Logical implementation: gates, modules logic synthesis, logic verification, static timing analysis
Circuit implementation: transistors circuit simulations
Physical design, verification floorplanning, placement, routing, dynamic timing analysis
Speed Power Cost
High Low Volume
Many Implementation Choices
Microprocessors Domain-specific processors
DSP Network processors Microcontrollers
ASIPs Reconfigurable SoC FPGA Gate-array ASIC
E.g. Degree of Customization of Processor Architecture
The architecture of the computation engine used to implement desired functionality
Processor does not have to be programmable “Processor” not equal to general-purpose processor
Application-specific
Registers
CustomALU
DatapathController
Program memory
Assembly code for:
total = 0 for i =1 to …
Control logic and State register
Datamemory
IR PC
Single-purpose (“hardware”)
DatapathController
Control logic
State register
Datamemory
index
total
+
IR PC
Registerfile
GeneralALU
DatapathController
Program memory
Assembly code for:
total = 0 for i =1 to …
Control logic and
State register
Datamemory
General-purpose (“software”)
[Adapted from Embedded Systems Design: A Unified Hardware/Software Introduction. Copyright 2000 Vahid & Givargis]
total = 0for i = 1 to N loop total += M[i]end loop
General-purpose Microprocessors
Programmable device used in a variety of applications Also known as “microprocessor”
Features Program memory General datapath with large register file and
general ALU User benefits
Low time-to-market and NRE costs High flexibility
“Pentium” the most well-known, but there are hundreds of others
IR PC
Registerfile
GeneralALU
DatapathController
Program memory
Assembly code for:
total = 0 for i =1 to …
Control logic and
State register
Datamemory
[Adapted from Embedded Systems Design: A Unified Hardware/Software Introduction. Copyright 2000 Vahid & Givargis]
Application-specific Instruction Processors, ASIP
Programmable processor optimized for a particular class of applications having common characteristics Compromise between general-purpose and single-
purpose processors Features
Program memory Optimized datapath Special functional units
Benefits Some flexibility, good performance, size and
power
IR PC
Registers
CustomALU
DatapathController
Program memory
Assembly code for:
total = 0 for i =1 to …
Control logic and
State register
Datamemory
[Adapted from Embedded Systems Design: A Unified Hardware/Software Introduction. Copyright 2000 Vahid & Givargis]
Single-purpose ‘Processors,’ or ASIC
Digital circuit designed to execute exactly one program a.k.a. coprocessor, accelerator or peripheral
Features Contains only the components needed to execute a
single program No program memory
Benefits Fast Low power Small size
DatapathController
Control logic
State register
Datamemory
index
total
+
[Adapted from Embedded Systems Design: A Unified Hardware/Software Introduction. Copyright 2000 Vahid & Givargis]
E.g. ASIC
A direct sequence spread spectrum (DSSS) radio receiver ASIC (UCLA)
ASIC FeaturesArea: 4.6 mm x 5.1 mmSpeed: 20 MHz @ 10 McpsTechnology: HP 0.5 mPower: 16 mW - 120 mW (mode dependent)
@ 20 MHz, 3.3 VAvg. Acquisition Time: 10 s to 300 s
The Implementation Choice is Important
The Co-design Ladder
In the past: Hardware and software design
technologies were very different
Recent maturation of synthesis enables a unified view of hardware and software
Hardware/software “codesign”
Implementation
Assembly instructions
Machine instructions
Register transfers
Compilers(1960's,1970's)
Assemblers, linkers(1950's, 1960's)
Behavioral synthesis(1990's)
RT synthesis(1980's, 1990's)
Logic synthesis(1970's, 1980's)
Microprocessor plus program bits: “software”
VLSI, ASIC, or PLD implementation: “hardware”
Logic gates
Logic equations / FSM's
Sequential program code (e.g., C, VHDL)
The choice of hardware versus software for a particular function is simply a tradeoff among various design metrics, like performance, power, size, NRE cost, and especially flexibility; there is no
fundamental difference between what hardware or software can implement.
[Adapted from Embedded Systems Design: A Unified Hardware/Software Introduction. Copyright 2000 Vahid & Givargis]
Core-based Design: System on Chip
SC3001 DIRAC chip (a radio receiver) from Sirius Communications
Reconfigurable SoC
Triscend’s A7 CSoC
Other Examples
Atmel’s FPSLIC(AVR + FPGA)
Altera’s Nios(configurable
RISC on a PLD)
IP-based Design
[Vincentelli]
Map from Behavior to Architecture
[Vincentelli]
Summary: Microsystems in New “Spaces”
Generational shift in computing devices lot more of everything: computing, networking, communications lot less of power, energy, volume, weight, patience Application is everything, the possibilities are limitless
System architectures are due for an overhaul the architectures are (radically) changed/challenged the programming context is changed the system software contract is changed
new awareness: location, power, timing, reactivity, stability
Instrumented wide-area spaces
Personal area spaces
Internet end-points
In-body, in-cell, in-vitro spaces
Next Lecture: Overview of Semiconductor Devices/Processes.