Week I

University of Malaya

Dr.HarikrishnanDepartment of Electrical Engineering

e-mail: [email protected]

KEEE 4469Analog VLSI Circuit Design

Course Outline

Course work (mini project) 20 %Test 20 %

Final Examination 60 %

Reference

University of Malaya KEEE 4469 HRK 2/20

CMOS Analog Circuit Design, P.E.Allen and D.R.Holberg, Oxford UniversityPress, 2002.

Design of Analog CMOS Integrated Circuit,B.Razavi, McGraw Hill, 1999.

Analysis and Design of Analog Integrated Circuits, P.R.Gray, P.J. Hurst, S.H.Lewis and R.G. Meyer, John Wiley & Sons, Inc., 2009.

Reference

Enhancement- Type MOSFET

Field effect transistor (FET) derives its name from the essence of its physical operation,where the current-control mechanism is based on an electric field established to thecontrol terminal.

The current is conducted by only one type of carrier (electrons or holes) depending on thetype of FET (n channel or p channel) which gives FET another name, the unipolartransistor.

Compared to BJTs, MOS transistors can be made quite small (occupying small silicon


area on IC chip). Digital logic and memory functions can be implemented with circuits thatuse only MOSFETs in very-large-scale integrated (VLSI) design.

MOS technology has been applied extensively in the design of analog integrated circuitsand in integrated circuits that combine both analog and digital circuits.

Although the FET family of devices has many different types, the discussion shall bedevoted to the enhancement type MOSFET, which is by far the most significantsemiconductor device available today.

OBJECTIVE : physical operation, terminal characteristic and application.

Device Structure


Figure 1(a) Figure 1(b) The n-channel enhancement device is fabricated on a p-type substrate or body, with two

heavily doped n-type regions indicated in Figure 1 as the n+ source and n+ drain regions.

Metal is deposited on top of the oxide layer to form the gate electrode of the device.

Four terminals are brought out : Gate (G), Source (S), Drain (D) and Substrate / Body / Bulk(B).

Device OperationNo Gate Voltage Operation

With no bias voltage applied to the gate, two back-to-back diodes exist in series betweenthe drain and source. These diodes prevent current conduction from drain to source whena voltage vDS is applied.

Current Flow Channel


Figure 2

Device Operation (contd) A positive gate voltage (vGS) repels the holes of the substrate under the gate, leaving

behind a carrier depletion region, populated by negative charge.

Positive gate voltage attracts electrons from the n+ source and drain regions (where theyare in abundance) into the channel region. When sufficient number of electronsaccumulate near the surface of the substrate under the gate, an n region is in effectcreated, connecting the source and drain regions.

If a voltage is applied between the drain and source, current flows through this induced n


region, carried by electron. The induced n region thus forms a channel for current flowfrom drain to source and is aptly called so. Correspondingly, the MOSFET is called an n-channel MOSFET of an NMOS transistor.

An n-channel MOSFET is formed in a p-type substrate. The channel is created byinverting the substrate surface from p type to n type and hence is also called an inversionlayer.

The value of vGS at which a sufficient number of mobile electrons accumulate in thechannel region to form a conducting channel is called the threshold voltage and denotedas VT.

Device Operation (contd) The gate and body of the MOSFET form a parallel plate capacitor with oxide layer being

the dielectric. The positive gate voltage causes positive charge to accumulate on the topplate of the capacitor. The corresponding negative charge on the bottom plate is formedby the electrons in the induced channel.

An electric field develops in the vertical direction. It is this field that controls the amount ofcharge in the channel and thus it determines the channel conductivity and in turn thecurrent that will flow through the channel when a voltage vDS is applied.

Applying small v


Applying small vDS Having induced a channel, if a positive voltage vDS is applied between the drain and

source. The voltage vDS causes a current iD to flow through the induced n channel. Currentis carried by free electrons traveling from source to drain as illustrated in Figure 3(a).

The magnitude of iD depends on the density of electrons in the channel, which in turndepends on the magnitude of vGS. Specifically, for vGS = VT the channel is just induced andthe current conducted is still negligibly small. As vGS exceeds VT more electrons areattracted into the channel and increases the charge carriers with increasing channel depthor conductance. The fact that the conductance of the channel increases with the excessgate voltage (vGS-VT), also known as the effective voltage.

Device Operation (contd) Figure 3(b) shows the sketch of iD versus vDS for various values of vGS.


Figure 3(a) Figure 3(b) From Figure 3, it is noted that for the MOSFET to conduct, a channel has to be induced.

Increasing vGS above VT, enhances the channel, hence the name enhancement modeoperation. Finally it is observed that the current that leaves the source terminal (iS) is equal tothe current that enters the drain terminal (iD) and the gate current iG =0.

Device Operation (contd)Increasing vDS

With vGS held constant to a value of greater than VT and vDS is increased across thechannel from source to drain as illustrated in Figure 4(a), the voltage increases from 0 tovDS. Thus the voltage between the gate and points along the channel decreases from vGSat the source end to vGS vDS at the drain end. Since the channel depth depends on thisvoltage, the channel is no longer of uniform depth, rather the channel takes a tapered formas shown in Figure 4(a).

University of Malaya KEEE 4469 HRK 9/20Figure 4(a) Figure 4(b)

Device Operation (contd) As vDS is increased, the channel becomes more tapered an its resistance correspondingly

increases. Thus the iD-vDS curve does not continue as a straight line but bends as shownin Figure 4(b).

Eventually when vDS is increased to the value that reduces the voltage between gate andchannel at the drain end to VT that is vGS vDS = VT the channel depth at the drain enddecreases to almost zero and the channel is said to be pinched off.

Increasing vDS beyond this value has little effect on the channel shape and the current


through the channel remains constant at the value reached for vDS = vGS VT. The draincurrent saturates at this value and the MOSFET is said to have entered the saturationregion of operation.

The voltage vDS at which saturation occurs is denoted vDSsat,

The device operates in saturation region if vDS vDS,sat. The region of the iD-vDScharacteristic obtained for vDS < vDS,sat is called the triode region.

DS,sat GS Tv v V=

CMOS


Figure 5

Figure 5 shows a cross section of a CMOS chip illustrating how the PMOS and NMOStransistors are fabricated. Observe that while the NMOS transistor is implemented directlyin the p-type substrate, the PMOS transistor is fabricated in a specially created n region,known as an n well. The two devices are isolated from each other by a thick region ofoxide that functions as an insulator.

Circuit SymbolNMOS


PMOS

iD-vDS Characteristic


Figure 6(a)

Figure 6(b) The characteristic curves in Figure 6(b) indicate that there are three distinct regions of

operation: the cutoff region, the triode region and the saturation region. The saturationregion is used if the FET operates as an amplifier. For operation as a switch, the cutoffand triode region are utilized.

NMOS Current Equation

Triode region :

Saturation region :

( ) 2D n x GS T DS DSW 1i C v V v vL 2

=

( )2D n x GS T1 Wi C v V2 L

=


( )2 L

where, iD = Drain current

n = Electron mobility

Cox = Capacitance per unit area

W = Width

L = Length

vGS = Gate-source voltage

VT = Threshold voltage

ID Derivation

Triode region of operation is defined as one in which Vgs is large enough to guarantee theformation of an inversion layer. From (1), zero charge occurs :

The charge density thus first becomes zero at the drain end at some particular voltage.

( ) ( ){ }n ox gs TQ y WC V V x V= (1)where is the capacitance per unit area.ox x xC t =

( )gs TV V x V 0 =


The charge density thus first becomes zero at the drain end at some particular voltage.The boundary for the triode region is defined by :

As long as Vds < Vdsat, the device will be in linear region.

Substituting (1) into (2) and given that

ds gs T dsatV V V V=

n

n

I Q vQ E

=

= (2)where is the mobility of charge carriers and E is the electric field.

E dV dx=

With no bias voltage applied to the gate, two back-to-back diodes exist in series betweenthe drain and source. These diodes prevent current conduction from drain to source whena voltage Vds is applied.

( ){ }VL ds x n gs T0 0I dx WC V V y V dV =

ID Derivation (contd)

( ) 2D x n gs T ds dsW 1I C V V V VL 2

=

(3)


a voltage Vds is applied.

When Vds is high enough so that the inversion layer does not extend all the way fro,source to drain, the channel is said to be pinched off. In this case, the field felt by thechannel charge ceases to increase, causing the total current to remain constant despiteincreases in Vds.

Calculating the value of this current is easy; all that is needed to do is to substitute Vdsat forVds in (3):

( )2x nD gs TC WI V V2 L

= (4)

Circuit Condition Summary- NMOS

Operation Region Condition

Cutoff

Triode

GS Tv V

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