Week 3 Week 3 PresentationPresentation

Kevin CheungKevin CheungMichael GlowackiMichael Glowacki

Alex RomineAlex RomineDave SextonDave Sexton

OpcodesOpcodesregister-register instructions (R-type) OPCODE FUNCTsll = r,0x04 000000 000100srl = r,0x06 000000 000110sra = r,0x07 000000 000111add = r,0x20 000000 100000addu = r,0x21 000000 100001sub = r,0x22 000000 100010subu = r,0x23 000000 100011and = r,0x24 000000 100100or = r,0x25 000000 100101xor = r,0x26 000000 100110seq = r,0x28 000000 101000sne = r,0x29 000000 101001slt = r,0x2a 000000 101010sgt = r,0x2b 000000 101011sle = r,0x2c 000000 101100sge = r,0x2d 000000 101101movi2s = r,0x30 000000 110000movs2i = r,0x31 000000 110001movf = r,0x32 000000 110010movd = r,0x33 000000 110011movfp2i = r,0x34 000000 110100movi2fp = r,0x35 000000 110101movi2t = r,0x36 000000 110110movi2i = r,0x37 000000 110111sltu = r,0x3a 000000 111010sgtu = r,0x3b 000000 111011sleu = r,0x3c 000000 111100sgeu = r,0x3d 000000 111101

Opcodes – cont.Opcodes – cont.floating-point instructions (R-type)addf = f,0x00 000001 000000subf = f,0x01 000001 000001multf = f,0x02 000001 000010divf = f,0x03 000001 000011addd = f,0x04 000001 000100subd = f,0x05 000001 000101multd = f,0x06 000001 000110divd = f,0x07 000001 000111cvtf2d = f,0x08 000001 001000cvtf2i = f,0x09 000001 001001cvtd2f = f,0x0a 000001 001010cvtd2i = f,0x0b 000001 001011cvti2f = f,0x0c 000001 001100cvti2d = f,0x0d 000001 001101mult = f,0x0e 000001 001110div = f,0x0f 000001 001111eqf = f2,0x10 000001 010000nef = f2,0x11 000001 010001ltf = f2,0x12 000001 010010gtf = f2,0x13 000001 010011lef = f2,0x14 000001 010100gef = f2,0x15 000001 010101multu = f,0x16 000001 010110divu = f,0x17 000001 010111eqd = f2,0x18 000001 011000ned = f2,0x19 000001 011001ltd = f2,0x1a 000001 011010gtd = f2,0x1b 000001 011011led = f2,0x1c 000001 011100ged = f2,0x1d 000001 011101

Opcodes – cont.Opcodes – cont.general instruction OPCODEj = j,0x02 J 000010jal = j,0x03 J 000011beqz = b,0x04 I 000100bnez = b,0x05 I 000101bfpt = b0,0x06 I 000110

bfpf = b0,0x07 I 000111

addi = i,0x08 I 001000addui = i,0x09 I 001001subi = i,0x0a I 001010subui = i,0x0b I 001011andi = i,0x0c I 001100ori = i,0x0d I 001101xori = i,0x0e I 001110lhi = i1,0x0f I 001111rfe = n,0x10 J 010000trap = t,0x11 J 010001jr = jr,0x12 I 010010jalr = jr,0x13 I 010011slli = i,0x14 I 010100nop = n,0x15 R 010101srli = i,0x16 I 010110srai = i,0x17 I 010111seqi = i,0x18 I 011000

OPCODEsnei = i,0x19 I 011001 n/aslti = i,0x1a I 011010 n/asgti = i,0x1b I 011011 n/aslei = i,0x1c I 011100 n/asgei = i,0x1d I 011101 n/alb = l,0x20 I 100000 n/alh = l,0x21 I 100001 n/alw = l,0x23 I 100011 n/albu = l,0x24 I 100100 n/alhu = l,0x25 I 100101 n/alf = l,0x26 I 100110 n/ald = l,0x27 I 100111 n/asb = s,0x28 I 101000 n/ash = s,0x29 I 101001 n/asw = s,0x2b I 101011 n/asf = s,0x2e I 101110 n/asd = s,0x2f I 101111 n/asltui = s,0x3a I 111010 n/asgtui = s,0x3b I 111011 n/asleui = s,0x3c I 111100 n/asgeui = s,0x3d I 111101 n/a

Zero ExtenderZero Extender

Zero Extender - TraceZero Extender - Trace

SRL ShifterSRL Shifter

SRL Shifter - TraceSRL Shifter - Trace

SRA ShifterSRA Shifter

SRA Shifter - TraceSRA Shifter - Trace

Register FileRegister File

Register File – TraceRegister File – Trace

1 Bit ALU – Implemented 1 Bit ALU – Implemented XORXOR

1 Bit ALU Trace 1 Bit ALU Trace

32 Bit ALU32 Bit ALU

32 Bit ALU - Trace32 Bit ALU - Trace

Week 4 Week 5 Week 6

1/27/08 - 2/2/08 2/3/08 - 2/9/08 2/10/08 - 2/16/08

Add Registers Between Steps

Plan layout of entire processor

Control Signals

Hazards

MULT

Loads

Stores

Moves

Set Conditionals

Branches

Jumps

Trap/RFE

Plan Layout of ProcessorPlan Layout of Processor

Control SignalsControl Signals

Implement a PLA that interprets the Implement a PLA that interprets the opcode of the DLX processor.opcode of the DLX processor.

Need to decide what control signals Need to decide what control signals we will need and what they will be we will need and what they will be for each instruction.for each instruction.

HazardsHazards

DataData Detection: Test if destination register of Detection: Test if destination register of

previous instructions are the same as previous instructions are the same as the source register of the current the source register of the current instruction.instruction.

Handling: Forward the data from the Handling: Forward the data from the previous instruction.previous instruction.

HazardsHazards

StructuralStructural Detection: Happens if 2 registers would Detection: Happens if 2 registers would

need to write a register at the same need to write a register at the same time.time.

Handling: Insert a stallHandling: Insert a stall

HazardsHazards

ControlControl Detection: Any conditional branchDetection: Any conditional branch Handling: Stall the pipeline until the Handling: Stall the pipeline until the

branch result is known.branch result is known.