indico.bnl.gov · Web viewUS ATLAS. HL-LHC. Upgrade. BASIS of ESTIMATE (BoE) Date of Est:...

US ATLASHL-LHC Upgrade BASIS of ESTIMATE (BoE)

Date of Est: 12/22/2017Prepared by: Tim Andeen Responsible Inst: UT AustinDocdb #: HL-LHC-doc-232

WBS number: 6.4.1 WBS Title: Liquid Argon Frontend ASIC Development and Production

WBS Dictionary Definition: This BOE covers the design, prototyping and production of new Application Specific Integrated Circuits (ASICs) for the frontend electronics for the LAr calorimeter system as part of the HL-LHC upgrade of the ATLAS detector. This work will be done at Columbia University, Nevis Laboratories (Columbia), Southern Methodist University (SMU) and the University of Texas at Austin (UT Austin). Columbia and UT Austin are collaborating to develop a custom Analog-to-Digital Converter (ADC) chip. SMU, is has collaboraedting as part of a CERN-centered group on the lpGBT and VL+ projects, to and will develop and produce the serializer and optical transmitter using the lpGBT and VL+ to transmit the FEB2 data off of the detector and the control signals from the FEB2..

During the prototype phase, sufficient ASICs will be produced to populate 20 prototype FEB2 boards for a system test that will serve to validate the design and performance as a major milestone before the PRR and the launch of production. A total of 1524 production FEB2 boards, each instrumenting 128 LAr calorimeter channels, is required to equip the entire LAr calorimeter system (for quantities and explanation, see Table 1). Each FEB2 board will require 32 ADC chips, and 22 lpGBT chips and 6 VL+ optical transmitters for the data readout. Additional, bi-directional control links for each FEB2 board are necessary, requiring an additional 2 VL+ and lpGBT devices each. Therefore, the deliverable for this BOE is 48.8k ADC chips, 36.6k lpGBT chips, and 12.2k VL+ transmitters. The BOE also includes the costs of prototypes and the intermediate steps required to validate the designs.

Estimate Type (check all that apply – see BOE Report for estimate type by activity):

___ Existing Purchase Order or Work Complete___ Engineering Build-up_X_ Extrapolating from Actuals_X_ Analogy_X_ Expert Opinion

Supporting Documents (including but not limited to):

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Details of the Base Estimate (Explanation of the Work)This WBS covers the prototyping, production, and testing of ASICs for the front-end

electronics for the LAr calorimeter HL-LHC upgrade. These ASICs provide the digitization of the calorimeter signals, as well as serialization and off-detector optical transmission of the resulting data. The digitization is done by an ADC ASIC under development. The serialization is done by the lpGBT, a serializer-deserializer ASIC being developed through a CERN-centered common project. The optical transmitter array (OTx) is done by a module that is being developed through the CERN-centered Versatile Link+ (VL+) common project. Given the on-detector location of these three devices, they must be radiation-tolerant according to HL-LHC specifications.

This work will be carried out at Columbia, SMU and UT Austin. Columbia produced the FEB and several ASICS for the original construction, as well as the ADC for the Phase-I upgrade. UT Austin members contributed to the Phase-I ADC as well. SMU contributed to the optical links in the original ATLAS FEBs and in the Phase-I upgrade and is a member of the lpGBT and VL+ project collaborations.

The ASIC development proceeds in several stages, described below, in parallel for the ADC and optical components. The ADC ASIC will be developed using the TSMC 65 nm CMOS technology, the same technology being targeted by the LAr PA/shaper development of WBS 6.4.5. The ADC will include an interface compatible with the lpGBT chip. SMU is contributing circuit design and testing to the lpGBT and has contributed testing and design to the VL+ projects. Once prototypes are available, SMU will integrate the components into a final design for the FEB2 data and control links.

This BOE is organized as follows: we first discus the ADC development and then the Optics development. Then we discuss costs and labor split by institution, again starting with the ADC (Columbia and UT Austin) and then the Optics (SMU).

I. ADC Chip DevelopmentThe custom ADC chip will be used to digitize the shaped calorimeter signals at the bunch

crossing rate of 40 MHz, with two overlapping gain scales, each with a 14-bit dynamic range and 12-bit precision. The work to develop the ADC ASIC will be performed by Columbia and UT Austin. Columbia is responsible for the development of a Dynamic Range Enhancing (DRE) block and chip services and integration (I/O, control, etc.), as well as the production of the custom ADC ASIC. UT Austin will develop the 12-bit Successive Approximation Register (SAR) ADC block and perform radiation and performance testing of the ADC ASIC during prototyping and production. The SAR is a 12-bit pipelined ADC (internally two SAR stages form the pipeline), while the DRE extends the range of the SAR across the full 14-bit dynamic range required. The deliverable will be an eight-channel ADC, to be integrated in the FEB2 boards. Each ADC channel will digitize one gain of a LAr calorimeter channel, therefore the eight-channel ADC digitizes both gains of four LAr calorimeter channels.

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Pre-MREFC Phase

R&D PhaseThe DRE block is being developed in collaboration between Nevis Labs and an Electrical

Engineering (EE) group at Columbia University while the SAR block is being developed in collaboration between the physics and an EE groups at UT-Austin. The integration of the blocks is done at Columbia, which and both UT Austin and Columbia is alsoare designing the chip services.

Table 1. Overview of system specifications and requirements.System Quantity Notes

FEB2 Boards Required 1524

FEB2 Boards (Production) 1627 Including 6% spares + 16 yield loss

FEB2 Boards (Prototypes) 20

LAr channels per board 128

Sampling Rate (MHz) 40 The bunch crossing rate

Gains per channel 2

Dynamic range (bits) 14

Raw data rate per ADC channel (Mbps) 640 (14 bits + 2 bits BCID) x 40 MHz

Raw data rate per FEB2 (Gbps) 163.84

Total raw data rate (Tbps) 249.69

Table 2. Overview of ADC and number of chips required and produced.ADC Quantity Notes

Dynamic range (bits) 14

Channels per ADC chip 8

ADC channels per FEB2 256 1 LAr channel = 2 ADC channels (2 gains/channel)

ADC chips per FEB2 32

ADC Packaging Yield (fraction) 0.9 Assume approximately 90% yield from Phase-I

ADC chips on prototype FEB2 640 Needed on prototype

ADC chips produced for prototype FEB2 725 Includes packaging yield

ADC chips on production FEB2 on detector 48768 Installed on detector

ADC chips on FEB2, including FEB2 spares 52064 Installed on detector and spares

ADC chips including 6% shelf spares 55188 Installed on detector and spares and shelf spares

ADC chips produced including yield 62000 Assume approximately 90% yield from Phase-I

The first pre-prototype ADC chip (Pre-prototype 1, WBS 6.4.1.1.1, 6.4.1.1.2, 6.4.1.2.1) was submitted to the foundry in May 2017 and received for testing in September of 2017. The goal of this

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test chip is was to test a single channel of a complete DRE+SAR ADC. The testing will focused on the precision and performance of the SAR and the DRE, both as stand-alone blocks and together within the integrated chip. Test jigs were designed and built by engineers at Columbia and UT-Austin, and the chip was irradiated in October 2017.

A yearly schedule of increasingly complete chip submissions and testing is anticipated until the prototype phase in 2020. In spring 2018 a two-channel chip will wasbe submitted (Pre-prototype 2 WBS 6.4.1.2.2, 6.4.1.2.3, 6.4.1.1.3, 6.4.1.1.4), with a fully integrated DRE+ADC, PLL, BCID, internal clock circuitry, slow control over I2 C, and reference voltage drivers,digital data processing unit, eLink (a CERN developed readout standard) communications for compatibility with the prototype lpGBT chip and refinements in the design. This chip will provide a larger focuses on the performance of the entire chip, and the necessity requirements forof a calibration will be assessedalgorithm. The performance of this chip will be the subject of the ATLAS PDR.

A third design iteration is foreseen in spring 2019 (Pre-prototype 3 WBS 6.4.1.1.5, 6.4.1.1.6, 6.4.1.2.4, 6.4.1.2.5), when an eight-channel chip will be submitted, with all chip control and services implemented, including reference voltage, eLink (a CERN developed readout standard) communications for compatibility with the lpGBT chip and further design refinements. This will be the first chip with the complete functionality that fulfills the design specification and . will be included on the FEB2 slice test board for verification of its performance within the larger system. The results from the testing of this chip will be the subject of the ATLAS FDR.

MREFC Construction Project

Prototype PhaseA full functionality eight-channel prototype chip will be submitted in 2020 and its performance

verified in the FE crate test (WBS 6.4.1.1.7, 6.4.1.1.8, 6.4.1.2.6, 6.4.1.2.7). Following this, it will be integrated on the pprototype FEB2 board. The FEB2 prototype will be integrated with the trigger and calibration boards in a system test of a half-crate of FE electronics. The ADC will be tested in this environment as part of a milestone before the ATLAS PRR.

Production PhasesAfter passing the PRR review, ADC production will be launched (WBS 6.4.1.1.9, 6.4.1.2.8,

6.4.1.2.9). Before submission, the design may be iterated a final time to incorporate any necessary performance optimization and other small changes learned in the FE crate test and PRR.

The ADC chips will be tested in batches during the period 2022-2023 (WBS 6.4.1.1.10, WBS 6.4.1.2.10). They will be shipped to UT-Austin for testing. Basic performance tests are planned for every chip, with a fraction selected for more in-depth testing. The chips that pass the tests will be shipped to Columbia for integration on the production FEB2 boards. The arrival of the chips at Columbia for assembly on the FEB2 concludes the production, and the needed at CERN date is reflected in the FEB2 schedule.

II. Optical Link DevelopmentThe optical link development covers the prototyping, production, and testing of the data and

control link components for the FEB2 boards. The deliverables for WBS 6.04.01.03 are the lpGBT Serializer chips (WBS 6.04.01.03.01 - WBS 6.04.01.03.03), and the tested VL+ OTx modules (WBS 6.04.01.03.04) and their integration to provide data and control links for the FEB2 boards (WBS 6.04.01.05 - WBS 6.04.01.03.98).

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SMU is has been a member in both the lpGBT and VL+ common projects, and contributeds to both ASIC designs and prototype testing. For the lpGBT chip, SMU is designing the phase aligner in the eLink receiver, the phase shifter in the recovered clock output, the equalizer in the deserializer input, and the SLVS receiver. The custom VL+ transceiver (VTRx+) provides an interface between the lpGBT and the optical fiber plant and SMU was involved in prototype testing.

For the FEB2, SMU will design data and control links based on lpGBT and VL+. On the board, these links come immediately after the ADC, which will be designed to provide a compatible interface with the lpGBT. SMU will evaluate and test the lpGBT and VL+ and integrate these devices into a FEB2 data link. After the design is finalized SMU will ensure the quality and performance of the data link through the production period of the FEB2.

The lpGBT can transmit up to 8.96 Gbps of user data over 14 eLinks (at 640 Mbps per eLink). Each elink is mapped to one of the 256 ADC channels. The number of bits transmitted is increased by the implementation of the Bunch Crossing ID (BCID) counter and ADC frame signal serialization, and the coupling efficiency between the ADC and lpGBT. The baseline mapping requires 22 lpGBT chips (Table 3) and 6, quad-link VL+ OTx modules for the data link (Table 4).

Each FEB2 requires redundant bi-directional control links, implemented using 2 VL+ single link transceivers and 2 lpGBT chips. To develop the control link, additional work will be required to distribute the clock, provide configuration and controls via I2C, provide a BCID reset, and assemble the monitoring information to be transmitted off of the FEB2 boards.

Pre-MREFC Phase

R&D PhaseThe prototype first lpGBT ASIC design is planned to bewas submitted for prototype fabrication

in the early fall Julyof 20187 (Table 5). The VL+ OTx has a conceptual design with the first prototype scheduled be available for summer by the end of 20187 (Table 6). The submission of these devices is done by the lpGBT and VL+ collaborations respectively, and is external to the US ATLAS project. However, SMU is involved in design work for the lpGBT submissions.

SMU will continue working on designing blocks for the lpGBT chip, andchip and will also contribute to the testing of the lpGBT and to quality assurance testing for the VL+ OTx module. Leveraging the knowledge from these the projectss, SMU will design the FEB2 pre-prototype data and control links based on the lpGBT and VL+ specifications (WBS 6.4.1.3.5, 6.4.1.3.7). The data links will use the earliest prototypes of lpGBT and VL+ for an ATLAS PDR. A nearly final design with a full-scale prototype evaluation that includes the ADC prototype chips will then be developed for the ATLAS FDR.

Table 3. Overview of lpGBT and number of chips required and produced for data and control links.lpGBT Quantity Notes

User Data per lpGBT (Gbps) 8.96

eLinks per lpGBT at 640 Mbps 14

lpGBT per FEB2, ideal for data link 19 Raw data rate divided by data rate per lpGBT

lpGBT per FEB2 including mapping for data link 22 Data overhead including mapping, frame, BCID

lpGBT per FEB2 for control link 2

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lpGBT per FEB2 total 24

lpGBT on FEB2 prototype 480 Needed on prototype

lpGBT on production FEB2 on detector 36576 Installed on detector

lpGBT on FEB2 including FEB2 spares 39048 Installed on detector and spares

lpGBT on FEB2 including FEB2 and shelf spares 41400 Approximately 6% shelf spares

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Table 4. Overview of VL+ and number of OTx required and purchased for data and control links.VL+ Links Quantity Notes

VL+ Quad Tx per FEB2 data links 6 quad-link device, 1 VL+ per four lpGBT

VL+ Single Tx per FEB2 control links 2 single-link device, 1 VL+ per lpGBT for control link

VL+ quad-Tx on FEB2 prototype 120 Needed on prototype

VL+ single-Tx on FEB2 prototype 40 Needed on prototype

VL+ quad-Tx on FEB2 on detector 9144 Installed on detector

VL+ quad-Tx on FEB2 including FEB2 spares 9762 Installed on detector and spares

VL+ quad-Tx on FEB2 with shelf spares 10400 Approximately 6% shelf spares

VL+ single-Tx on FEB2 on detector 3048 Installed on detector

VL+ single-Tx on FEB2 including FEB2 spares 3254 Installed on detector and spares

VL+ single-Tx on FEB2 with shelf spares 3500 Approximately 6% shelf spares

Table 5. lpGBT project schedule. WBS begins with design work before submission.

MREFC Construction Project

Prototype PhaseIn the prototype phase SMU will iterate and improve the FEB2 data and control link pre-(pre)

prototype (WBS 6.4.1.3.5, 6.4.1.3.6, 6.4.1.3.76.4.1.3.8) with close-to-final or early production versions of lpGBT and OTx from the two common projects. A nearly final design with a full-scale prototype evaluation that includes the ADC prototype chips will then be developed for the ATLAS FDR.

The data link prototype will be finalized together with the ADC prototype (the ADC ATLAS PRR). The 20 FEB2 prototype boards will require 480 lpGBT chips and 160 VL+ modules (120 quad link and 40 single link).

Preproduction and Production PhasesAfter the ATLAS PRR, SMU will work on integrating the data and control links onto the FEB2

prototypes, providing system level debugging and support (WBS 6.4.1.3.98). Experience from the current FEB optical link indicates that it is essential to allocate adequate time for debugging (or link prototype iteration) to ensure a robust FEB readout system. This is especially critical for the fast links on the complex FEB2 board. The FEB2 PCB has both high precision analog and high speed digital circuits, and will need to reliably work in a radiation environment, with little access for repairs and a limited

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Iteration SubmissionDate Testing Related WBSPrototype Chip (available) MPW Q14

2019720198 WBS: 6.04.01.03.01

Engineering Chip (submission) MPW Q44 201919

202019 WBS: 6.04.01.03.02

Production Chip (completed) MPW Q31 20210

20210 WBS: 6.04.01.03.03

number of spares. The production concludes when the links are integrated on the FEB2 at Columbia, and the needed at CERN date is reflected in the FEB2 schedule.

Table 6. VL+ project schedule. Iteration Goal Date Available s Related WBSPhase 2 Prototype feasibility

DdemonstrationQ43 2015 – Q2 20172018

NA

Phase 3Engineering Run

Pre-production readiness Q22 2017 – Q4 20182020

WBS: 6.04.01.03.04

Production Target start Completion Q3 2021~2019 WBS: 6.04.01.03.04

Cost Estimate:The cost estimate for this work, which will be performed at Columbia University Nevis Labs,

UT-Austin, and SMU is summarized in the tables below. (formatting will be beautified for later versions)

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Sum of ValueLbr Hours Mat Base

Trav Base

Pre-MREFC 31,812 375,060 42,2006.04.01.01.01 / COL LAr FE ADC Pre-Prototype 1 Cycle 2,468 72,000 2,00001 Pre-prototype 1 Cycle 2,468 72,000 2,000ENG 2,376EQUIP 72,000TECH 92TRAVF 2,000 6.04.01.01.02 / COL LAr FE ADC Pre-Prototype 1 Cycle Test 1,915 35,500 4,00002 Pre-prototype 1 Cycle Test 1,915 35,500 4,000ENG 1,305EQUIP 35,500TECH 260TRAVF 4,000UNCOST 350 6.04.01.01.03 / COL LAr FE ADC Pre-Prototype 2 Chip Cycle 2,122 72,000 2,00003 Pre-prototype 2 Chip Cycle 2,122 72,000 2,000ENG 2,058EQUIP 72,000TECH 64TRAVF 2,000 6.04.01.01.04 / COL LAr FE ADC Pre-Prototype 2 Chip Test 1,485 15,500 2,00004 Pre-prototype 2 Chip Test 1,485 15,500 2,000ENG 1,003EQUIP 15,500TECH 182TRAVF 2,000UNCOST 300 6.04.01.01.05 / COL LAr FE ADC Pre-Prototype 3 Chip Cycle 2,134 72,000 4,00005 Pre-prototype 3 Chip Cycle 2,134 72,000 4,000ENG 2,071EQUIP 72,000TECH 63TRAVF 4,000 6.04.01.01.06 / COL LAr FE ADC Pre-Prototype 3 Chip Test 1,484 16,500 2,00006 Pre-prototype 3 Chip Test 1,484 16,500 2,000ENG 1,002EQUIP 16,500TECH 182TRAVF 2,000UNCOST 300

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6.04.01.02.01 / UTAU LAr FE ADC Pre-Prototype 1 Chip Cycle 1,875 8,000 2,350 1,875 8,000 2,350ENG 1,606EQUIP 8,000TRAVD 2,350UNCOST 269 6.04.01.02.02 / UTAU LAr FE ADC Pre-Prototype 2 Chip Cycle 848 1,500 650 848 1,500 650ENG 848EQUIP 1,500TRAVD 650 6.04.01.02.03 / UTAU LAr FE ADC Pre-Prototype 2 Chip Irradiation Test 1,451 19,500 5,600

1,451 19,500 5,600ENG 855EQUIP 19,500TRAVD 3,000TRAVF 2,600UNCOST 596 6.04.01.02.04 / UTAU LAr FE ADC Pre-Prototype 3 Chip Cycle 1,250 1,500 2,600 1,250 1,500 2,600ENG 1,250EQUIP 1,500TRAVF 2,600 6.04.01.02.05 / UTAU LAr FE ADC Pre-Prototype 3 Chip Irradiation Test 2,449 19,500 4,950 2,449 19,500 4,950ENG 1,859EQUIP 19,500TRAVD 2,350TRAVF 2,600UNCOST 590 6.04.01.03.01 / SMU FE Electronics-SMU lpGBT Prototype 3,045 10,050 3,045 10,050ENG 2,170TECH 247TRAVF 10,050UNCOST 628 6.04.01.03.02 / SMU FE Electronics-SMU lpGBT Engineering Chip 1,476 1,476ENG 1,156TECH 144UNCOST 176 6.04.01.03.04 / SMU FE Electronics-SMU VL+ 897 897

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ENG 528UNCOST 369 6.04.01.03.05 / SMU FE Electronics-SMU FEB Datalink Pre-Prototype 5,296 23,940

5,296 23,940ENG 1,830MAT 23,940TECH 991UNCOST 2,475 6.04.01.03.07 / SMU FE Electronics-SMU FEB Control-link Prototype 737 17,620 737 17,620ENG 205MAT 17,620TECH 215UNCOST 317 6.04.01.1M / UTAU FE Electronics Management 8801M FE Electronics Management 880UNCOST 880 MREFC 48,758 3,882,975 34,7906.04.01.01.07 / COL LAr FE ADC Prototype Chip Cycle 2,903 412,500 2,00007 Prototype Chip Cycle 2,903 412,500 2,000ENG 2,579EQUIP 412,500TECH 324TRAVF 2,000 6.04.01.01.08 / COL LAr FE ADC Prototype Chip Test 2,678 34,000 2,00008 Prototype Chip Test 2,678 34,000 2,000ENG 1,469EQUIP 34,000TECH 909TRAVF 2,000UNCOST 300 6.04.01.01.09 / COL LAr FE ADC Production Chip Cycle 3,735 1,393,360 2,00009 Production Chip Cycle 3,735 1,393,360 2,000ENG 2,825EQUIP 1,393,360TECH 910TRAVF 2,000 6.04.01.01.10 / COL LAr FE ADC Production 6,173 4,00010 Production 25% 1,891 1,000ENG 869EQUIP 1,000TECH 1,02211 Production 50% 1,334 1,000

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ENG 445EQUIP 1,000TECH 88912 Production 75% 1,348 1,000ENG 449EQUIP 1,000TECH 89913 Production 100% 1,600 1,000ENG 625EQUIP 1,000TECH 975 6.04.01.02.06 / UTAU LAr FE ADC Prototype Chip Cycle 1,156 1,500 2,600 <Empty> 1,156 1,500 2,600ENG 1,156EQUIP 1,500TRAVF 2,600 6.04.01.02.07 / UTAU LAr FE ADC Prototype Chip Irradiation Test 2,939 27,500 4,950

2,939 27,500 4,950ENG 2,330EQUIP 27,500TRAVD 2,350TRAVF 2,600UNCOST 609 6.04.01.02.08 / UTAU LAr FE ADC Production Chip Cycle 1,423 2,600

1,423 2,600ENG 1,423TRAVF 2,600 6.04.01.02.09 / UTAU LAr FE ADC Production Qualification Test 1,828 22,500 3,900 1,828 22,500 3,900ENG 1,506EQUIP 22,500TRAVD 1,300TRAVF 2,600UNCOST 322 6.04.01.02.10 / UTAU LAr FE ADC Production Evaluation 4,536 27,000 3,400

4,536 27,000 3,400ENG 2,856EQUIP 27,000TRAVD 3,400UNCOST 1,680 6.04.01.03.03 / SMU FE Electronics-SMU lpGBT Production 4,774 956,195

4,774 956,195ENG 1,422EQUIP 956,195

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TECH 1,528UNCOST 1,824 6.04.01.03.04 / SMU FE Electronics-SMU VL+ 4,123 956,760 4,123 956,760ENG 1,178EQUIP 941,160MAT 15,600TECH 1,246UNCOST 1,699 6.04.01.03.06 / SMU FE Electronics-SMU FEB Datalink Prototype 4,962 20,160

4,962 20,160ENG 1,590MAT 20,160TECH 1,328UNCOST 2,044 6.04.01.03.07 / SMU FE Electronics-SMU FEB Control-link Prototype 609 27,500 7,560

609 27,500 7,560ENG 242MAT 27,500TECH 105TRAVD 7,560UNCOST 262 6.04.01.03.08 / SMU FE Electronics-SMU Data and Control Links for FEB2 4,983 3,780 4,983 3,780ENG 1,899TECH 1,032TRAVF 3,780UNCOST 2,052 6.04.01.1M / UTAU FE Electronics Management 1,9361M FE Electronics Management 1,936UNCOST 1,936 Grand Total 80,570 4,258,035 76,990

Labor Hours

Material Direct

Travel Direct

Pre-MREFC 31,573 495,079 42,2006.04.01 FE Electronics 31,573 495,079 42,2006.04.01.01 FE Electronics-Columbia 11,608 359,779 16,0006.04.01.01.01 / COL LAr FE ADC Pre-Prototype 1 Cycle 2,468 72,000 2,000ENG 2,376EQUIP 72,000TECH 92

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TRAVF 2,000 6.04.01.01.02 / COL LAr FE ADC Pre-Prototype 1 Cycle Test 1,915 35,500 4,000ENG 1,305EQUIP 35,500TECH 260TRAVF 4,000UNCOST 350 6.04.01.01.03 / COL LAr FE ADC Pre-Prototype 2 Chip Cycle 2,122 72,000 2,000ENG 2,058EQUIP 72,000TECH 64TRAVF 2,000 6.04.01.01.04 / COL LAr FE ADC Pre-Prototype 2 Chip Test 1,485 15,500 2,000ENG 1,003EQUIP 15,500TECH 182TRAVF 2,000UNCOST 300 6.04.01.01.05 / COL LAr FE ADC Pre-Prototype 3 Chip Cycle 2,134 72,000 4,000ENG 2,071EQUIP 72,000TECH 63TRAVF 4,000 6.04.01.01.06 / COL LAr FE ADC Pre-Prototype 3 Chip Test 1,484 16,500 2,000ENG 1,002EQUIP 16,500TECH 182TRAVF 2,000UNCOST 300 6.04.01.01.11 / COL LAr FE ADC Other 76,279EQUIP 76,279 6.04.01.02 FE Electronics-UTAustin 8,864 93,740 16,1506.04.01.02.01 / UTAU LAr FE ADC Pre-Prototype 1 Chip Cycle 1,875 8,000 2,350ENG 1,606EQUIP 8,000TRAVD 2,350UNCOST 269 6.04.01.02.02 / UTAU LAr FE ADC Pre-Prototype 2 Chip Cycle 848 1,500 650

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ENG 848EQUIP 1,500TRAVD 650 6.04.01.02.03 / UTAU LAr FE ADC Pre-Prototype 2 Chip Irradiation Test

2,000 19,500 5,600

ENG 1,404EQUIP 19,500TRAVD 3,000TRAVF 2,600UNCOST 596 6.04.01.02.04 / UTAU LAr FE ADC Pre-Prototype 3 Chip Cycle 1,830 1,500 2,600ENG 1,830EQUIP 1,500TRAVF 2,600 6.04.01.02.05 / UTAU LAr FE ADC Pre-Prototype 3 Chip Irradiation Test

2,311 19,500 4,950

ENG 1,721EQUIP 19,500TRAVD 2,350TRAVF 2,600UNCOST 590 6.04.01.02.11 / UTAU LAr FE ADC Other 43,740EQUIP 43,740 6.04.01.03 FE Electronics-SMU 10,222 41,560 10,0506.04.01.03.01 / SMU FE Electronics-SMU lpGBT Prototype 3,045 10,050ENG 2,170TECH 247TRAVF 10,050UNCOST 628 6.04.01.03.02 / SMU FE Electronics-SMU lpGBT Engineering Chip 1,048ENG 1,048 6.04.01.03.04 / SMU FE Electronics-SMU VL+ 897ENG 528UNCOST 369 6.04.01.03.05 / SMU FE Electronics-SMU FEB Datalink Pre-Prototype

4,495 23,940

ENG 1,772MAT 23,940

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TECH 707UNCOST 2,016 6.04.01.03.07 / SMU FE Electronics-SMU FEB Control-link Pre-Prototype

737 17,620

ENG 205MAT 17,620TECH 215UNCOST 317 6.04.01.90 L3 Project Management 8796.04.01.90 / UTAU L3 Project Management 879UNCOST 879 MREFC 50,468 3,949,6

2134,790

6.04.01 FE Electronics 50,468 3,949,621

34,790

6.04.01.01 FE Electronics-Columbia 15,489 1,887,349

6,000

6.04.01.01.07 / COL LAr FE ADC Prototype Chip Cycle 2,903 412,500 2,000ENG 2,579EQUIP 412,500TECH 324TRAVF 2,000 6.04.01.01.08 / COL LAr FE ADC Prototype Chip Test 2,678 34,000 2,000ENG 1,469EQUIP 34,000TECH 909TRAVF 2,000UNCOST 300 6.04.01.01.09 / COL LAr FE ADC Production Chip Cycle 3,735 1,393,3

602,000

ENG 2,825EQUIP 1,393,3

60TECH 910TRAVF 2,000 6.04.01.01.10 / COL LAr FE ADC Production 6,173 4,000ENG 2,388EQUIP 4,000TECH 3,785

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6.04.01.01.11 / COL LAr FE ADC Other 43,489EQUIP 43,489 6.04.01.02 FE Electronics-UTAustin 11,882 101,657 17,4506.04.01.02.06 / UTAU LAr FE ADC Prototype Chip Cycle 1,156 1,500 2,600ENG 1,156EQUIP 1,500TRAVF 2,600 6.04.01.02.07 / UTAU LAr FE ADC Prototype Chip Irradiation Test

2,939 27,500 4,950

ENG 2,330EQUIP 27,500TRAVD 2,350TRAVF 2,600UNCOST 609 6.04.01.02.08 / UTAU LAr FE ADC Production Chip Cycle 1,423 2,600ENG 1,423TRAVF 2,600 6.04.01.02.09 / UTAU LAr FE ADC Production Qualification Test 1,828 22,500 3,900ENG 1,506EQUIP 22,500TRAVD 1,300TRAVF 2,600UNCOST 322 6.04.01.02.10 / UTAU LAr FE ADC Production Evaluation 4,536 27,000 3,400ENG 2,856EQUIP 27,000TRAVD 3,400UNCOST 1,680 6.04.01.02.11 / UTAU LAr FE ADC Other 23,157EQUIP 23,157 6.04.01.03 FE Electronics-SMU 21,160 1,960,6

1511,340

6.04.01.03.03 / SMU FE Electronics-SMU lpGBT Production 5,202 956,195ENG 1,530EQUIP 956,195TECH 1,672UNCOST 2,000 6.04.01.03.04 / SMU FE Electronics-SMU VL+ 2,353 956,760

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ENG 1,074EQUIP 941,160MAT 15,600TECH 310UNCOST 969 6.04.01.03.06 / SMU FE Electronics-SMU FEB Datalink Prototype 6,243 20,160ENG 2,128MAT 20,160TECH 1,612UNCOST 2,503 6.04.01.03.08 / SMU FE Electronics-SMU FEB Control-link Prototype

609 27,500 7,560

ENG 242MAT 27,500TECH 105TRAVD 7,560UNCOST 262 6.04.01.03.09 / SMU FE Electronics-SMU Data and Control Links for FEB2

6,753 3,780

ENG 2,003TECH 1,968TRAVF 3,780UNCOST 2,782 6.04.01.90 L3 Project Management 1,9376.04.01.90 / UTAU L3 Project Management 1,937UNCOST 1,937 Grand Total 82,041 4,444,7

0076,990

M&S Costs

ADC Chip:

R&D CostsThe ADC chip is being designed in the 65 nm CMOS process available from TSMC. The ASIC

cost is based on current estimates for this process (attachment 3). Based on estimates from the DRE+SAR block on the first prototype chip, we assume a chip area of 16 mm2 for the 65 nm ADC chip.

During the design phase, we anticipate a new prototype to be submitted each year via a multi-project wafer (MPW) run (WBS: 6.04.01.01.01, WBS: 6.04.01.01.03, WBS: 6.04.01.01.05). These costs are not escalated given that the CERN Frame Contract has fixed prices. We estimate the packaging costs

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to be about $2.5k (attachment 2). Costs for the design and production of test-jigs (yearly) is also included (WBS: 6.04.01.01.02, WBS: 6.04.01.01.04, WBS: 6.04.01.01.06, WBS: 6.04.01.02.03. WBS: 6.04.01.02.05). The test-jig costs are estimated from similar test-jigs created for the development of the Phase-I 130 nm ADC and one board for this 65 nm development. The cost of the PCB is estimated from recent (2012-2017) boards produced (attachment 5), ranging in cost from $6.8k for a relatively simple board, to $15.5k for a more complex design. The PCB itself (typically ~$1k) and the FPGA (up to $2.8k) drive the material costs of these PCBs, and we anticipate that will remain the same for the HL-LHC upgrade. We estimate ~$16k for the precision test board, taking the high end of range as this is the actual cost of the board used for this 65 nm development. For the irradiation board we also take the high endhigh-end estimate (~$11k), again because this corresponds to the most recent, relevant experience. The material costs include beam time for an annual irradiation test at the facility of Massachusetts General Hospital (MGH) (attachment 7) as well as shipping and travel costs for material to and from MGH.

The ASIC development at Columbia requires use of the CADENCE commercial software suite. Columbia receives a CADENCE license with an annual fee of $9k (attachment 4). This fee is split evenly between Nevis Labs and the EE department. The cost of $4.5k/year borne by Nevis is included in the M&S costs.

At UT-Austin the cost for the licenses for development tools is assessed per user, and is $1.5k/year, included in the M&S costs.

Prototype CostsIn FY20, ADC chips need to be produced to have sufficient quantities to be able to populate the

FEB2 prototypes (WBS: 6.04.01.01.07, WBS: 6.04.01.02.07). The cost of ordering this quantity via an MPW run is estimated to be $413.0k (attachment 3). For testing the prototypes, two more complicated test-jigs will be required (~$32 (precision, WBS: 6.04.01.01.08) and ~$12k (irradiation, WBS: 6.04.01.02.08) is budgeted for production of the required test-jigs, estimated by extrapolating from the cost of the precision test board adding functionality for testing several chips simultaneously. The test-jigs cost includes the PCB and circuit components, FPGA and software, USB readout and filters.

Production CostsA dedicated run will be used to fabricate the production ADC chips. , as well as the other 65 nm

LAr chips, namely the PA/shaper of WBS 6.4.5. The NRE cost for production of the full mask set is $760k (attachment 3) which, due to the sharing of the masks for the LAr chips, will only be required to be paid once. This one-time NRE charge is included in this BOE in the ADC production cost (WBS: 6.04.01.01.09). In addition, production of each additional 25 wafers costs $85k. We include in the estimate the M&S cost of producing an additional 75 wafers (Table 7). (Nb. The cost here and in the RLS are from quotes more than a year old. Work is ongoing to have updated, formal quotes from CERN for these costs.) These costs are not escalated given that the CERN Frame Contract has fixed prices.

Table 7. Chip sizes and chips per wafer. Chip

(65 nm TSMC)Die Width

(mm)Die Height

(mm)Die Area

(mm2)No. per Wafer* Wafers needed*

ADC 4.00 4.00 16.00 3879 16Preamp/Shaper 4.86 4.4 21.38 2903 20

*Note: Assuming 300 mm wafer, wafers/chip calculated using http://anysilicon.com/ calculator. Wafers purchased in 25 wafer lots.

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http://anysilicon.com/

The cost for packaging the ADC chips is estimated based on a quotation from Quik-Pak (see attached) for packaging the ADC in a QFN-72 package, namely $6 per chip. We assume a yield of 90%, informed by the experience in the 130 nm ADC design in Phase-I, where a 90% yield was observed. A more conservative estimate of 70% is taken as a risk due to the uncertainty in moving to the 65 nm technology, as well as the increased precision (14-bit) required compared to the Phase-I ADC (12-bit). Putting this together, the estimated ADC production cost is $760k (NRE) + $255k (75 wafers) + $374 (packaging), for a total of $1,389k. Note that this cost also includes the cost of producing (but not packaging) the LAr PA/shaper. We include ~$24k (WBS 6.4.1.2.9) to produce the required QA/QC test-jigs.

Optics:

R&D CostsBased on our Phase-I experience, we allocate ~$20k each for fabrication of the PCB for the data

and control link tests (WBS: 6.04.01.03.05, 6.04.01.03.07) (see attachment 5 for costs of similar PCBs produced by Columbia for Phase 1Phase-I, and attachment 8, 12, 13, 14 of SMU Phase 1Phase-I costs).

Prototype CostsFor the FEB2 prototypes we will purchase lpGBT and VL+ devices (see Tables 2 and 3 for

quantities). Both the lpGBT chips and VL+ modules are currently in the design prototype phase. We use a CERN provided estimate of $35 per lpGBT chip and $120 per quad-channel link and $30 per single-channel link, respectively to determine the cost (see attachment 6). We allocate ~$22k (WBS 6.4.1.3.33), based on our Phase-I experience (see attachment 8, 12, 13, 14 of Phase 1Phase-I costs) for producing required the lpGBT engineer run QA/QC QA/QC test-jigs stands for the data and control links. To reduce effort and costs, this development will re-use as much as possible the test infrastructure that is being set up for Phase-I.

For the control and data links, based on our Phase-I experience, we allocate ~$2016k each for fabrication of the PCB for testing (WBS: 6.04.01.03.06, 6.04.01.03.087) (see attachment 5 for costs of similar PCBs produced by Columbia for Phase 1Phase-I, and attachments 8, 12, 13, 14 of SMU Phase 1Phase-I costs)

Production CostsFor lpGBT chips and VL+ OTx modules, and using the above estimates, the production amounts

to a total cost of $917k for lpGBT chips (WBS 6.4.1.3.3) and $941k for the VL+ single link and quad link modules (WBS 6.4.1.3.4). This total assumes a cost share for US ATLAS of 67% of this value, which is included in these values, with the remainder to be contributed by international collaborators. This cost share is very similar to what was implemented for the original FEB production, where collaborators made in-kind contributions (e.g. purchasing commercial components) to the FEB production which was performed by Columbia. This share is considered a good estimate for the lpGBT and VL+ purchasing, given the interests of other collaborators in participating in the upgrade, and also the rough expectation for the overall US contribution to the LAr HL-LHC upgrade. These costs are escalated at the standard 3% per year rate.

Manpower Costs

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ADC - The manpower costs for the ADC development are based on the actual labor used for the Phase 1Phase-I ADC development. Taking a typical Phase 1Phase-I chip development + test cycle (shown in Table 8), we compare to a Pre-prototype development cycle (again, as a typical cycle) for this ADC. The total labor hours are similar, as expected since the development work is similar. In the production phase (not shown in the table), the labor is larger, again as expected given the significantly larger number of chips to be tested.

Table 8. Labor for ADC development Phase 1Phase-I and HL-LHC, comparing similar development and test cycles.

Activity, WBS and Labor Type Labor (hrs) Sum (hrs)Phase 1Phase-I - 130 nm ADC WBS 1.1.3.2.1.2 ADC Prototype 6484

Engineer 2444Inst-Phys 720Tech 584Students + Postdoc 2736

HL-LHC - 65 nm ADC 68696416 COL - WBS: 6.04.01.01.05 and 6.04.01.01.065 LAr FE ADC Pre-Prototype 3 33303318

Engineer 1 3703Engineer 2 61721Engineer 3 36970Tech 245Student 17171721

UTAUS - WBS: 6.04.01.02.04 and 6.04.01.02.05 LAr FE ADC Pre-Prototype 3 3551086 Engineering Associate 1623366 Electrical Engineer Grad Student 1928720

The labor reflects the addition of a second EE graduate student. In addition to being a very cost-effective source of engineering, the EE students’ professors add their expert advice and deep design knowledge, serving essentially as uncosted support for the EE labor.

COLUMBIA UNIVERSITY The estimate for the ADC development uses actual manpower levels from the development of

the custom ADC ASIC for the Phase IPhase-I upgrade and was developed bottom-up. As with the Phase IPhase-I ADC, the development is performed by a collaboration of our engineering team and a group in the Columbia EE department specializing in low-voltage ADC design. As part of this arrangement, we provide support for 1 FTE EE Ph.D. student in EE group during the design phase and through the prototype stage in FY20.

The manpower estimate includes ~1.5~4/5 FTE per year of engineering effort per year and ~0.151/8 FTE technician effort per year during the R&D phase. These effort levels increase to ~21 2/5 FTE per year of engineering effort and ~1 FTE technician effort per year during the Prototype and Preproduction phase. During the approximately two year-long production phase, the engineering effort is minimal while the technician effort increases to ~1.5 2/5 FTE per year.

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The estimated manpower costs also include some limited (and low cost) use of undergraduate students. We plan to provide opportunities for undergraduate students to work in the lab during the summer periods. This plan both provides the students with an excellent opportunity to gain valuable experience in state-of-the-art instrumentation development, and provides a low-cost manpower source to supplement the technical workforce required for the production.

UT AUSTINLike at Columbia, the SAR ADC development at UT-Austin is performed by a collaboration

between the physics group and a group specializing in ADC design in the UT Austin ECE department. As part of this arrangement, we provide support for 1 FTE EE Ph.D. student during the design phase and through the prototyping stage in FY20.

In addition to the design work, during the R&D phase UT-Austin will do performance testing of the SAR ADC, and perform testing and radiation qualification of the overall ADC chip. This work includes writing readout and testing software, design and production of PCB boards for testing, and performance of the tests both locally and at irradiation facilities.

In the prototype and production phases, irradiation and batch testing will be performed on prototype (production) ADCs using specially designed test-jigs. An engineer is required for the design and programming of these test-jigs and the testing setup. Production testing will be partially performed by undergraduates, supervised by the engineer.

During the production phase an ADC QA/QC testing station will be setup so that the procedure can be easily run by anyone completing a modest training process. The large number of chips to be tested can then be completed by shifts of a variety of individuals, from undergraduates to graduate students, postdocs, and faculty members, allowing everyone to share in the effort. We assume that the bulk of the testing will be performed by undergrads (costed), with the grad students, postdocs and faculty contributing where necessary (uncosted).

Based on prior experience performing radiation testing and performance evaluation of the 130 nm ADC chip developed for the LAr Phase IPhase-I upgrade (see Table 8), the UT-Austin labor needs are estimated as ~1.5~4/5 FTE engineer per year during the R&D phase and ~1 FTE during the prototype and production phase. An engineer will behas been hired identified for this role, and the labor costs are estimated using existing rates for similar positions in the experimental HEP group at UT-Austin.

SMUFor the lpGBT development and lpGBT and VL+ testing and integration into of the data and

control links, SMU anticipates an ASIC designer needed for the design, as well as a Sr. and Jr. engineer and Sr. technician for testing the ASIC prototypes, preparing the QA test setup to screen each chip, and for design and evaluation of the link system. Table 9 shows this effort across FY, with a total from the project of ~11 FTE. This can be compared to (in Table 10) the Phase 1Phase-I effort, summed as well as split by WBS.

Table 9: SMU Labor by person and year. SMU Labor FY17 FY18 FY19 FY20 FY21 FY22 Project Total

Designer 0.8890 0.040 0.6525 0.2930 0.010 0.00 1.825 of 41

Jr. EE 0.133 0.0120 0.4520 0.4340 1.3015 0.1515 2.443

Sr. EE 0.145 0.1640 0.76540 0.54101.0.909

1 0.3940 2.952.66 Sr. ET 0.00 0.0024 0.5267 0.6245 1.9830 0.8173 3.8888

Sum 1.1580.171.2

5 21.2581 1.8550 43.3383 1.3625 110.1082

Table 10: SMU Labor compared to Phase 1Phase-I.Activity FTE

HL-LHC: lpGBT, VL+ and integration total110.108

2Phase 1Phase-I Optical links total 8.95 Total labor FTE 1.01.03..04.01 ADC-Optical link interface and Serialization ASIC 4.91 Total labor FTE 1.01.03..04.02 Laser Driver ASIC 2.09 Total labor FTE 1.01.03..04.03 MTx Otx Subassembly 0.88 Total labor FTE 1.01.03..04.03 MTx Otx Subassembly 1.07

Travel Costs

COLUMBIA UNIVERSITY Travel costs include typically 2-3 (11 total) international trips to CERN per year for the

engineers to participate in meetings with the collaboration (design reviews, upgrade meetings). Based on recent experience, the cost for a five-day trip to CERN is estimated to be a total of $2000 (not including overhead), including $1300 for the round-trip flight ticket, $350 for accommodation in the CERN Hostel, $150 in per diem allowance, and $200 to cover other miscellaneous expenses, such as local transportation, etc.

Table 11: Approximate cost for five-day trip to CERN for each institute. Airfare determined from average of recent trips (in appendix). Institute CostColumbia $2,000.00SMU $2,500.00UT-Austin $2,600.00

UT AUSTIN Travel costs include typically annual (7 total) international travel for engineers to CERN for

meetings with the collaboration and technical reviews, as well as 6 domestic trips to the MGH in Boston for irradiation tests and 8 domestic trips to Nevis for collaboration between engineers). Based on recent experience, the cost for a five-day trip to CERN is estimated to be a total of $2600 (not including

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overhead), including $1900 for the round-trip flight ticket, $350 for accommodation in the CERN Hostel, $150 in per diem allowance, and $200 to cover other miscellaneous expenses, such as local transportation, etc. Travel costs to Boston from Austin for 2 people for 3 nights are estimated at $1700 (not including overhead). Travel costs to NY from Austin for 1 person for 7 nights are estimated at $650 (not including overhead). This is particularly low because the accommodations are provided by Nevis.

SMUTravel funds are allocated each year for engineers to participate in technical reviews and SEU

tests. We budget 3 trips per year to participate in the VL+ and lpGBT collaborations. Based on recent experience, the cost for a five-day trip to CERN is estimated to be a total of $2500 (not including overhead), including $1800 for the round-trip flight ticket, $350 for accommodation in the CERN Hostel, $150 in per diem allowance, and $200 to cover other miscellaneous expenses, such as local transportation, etc.

The lpGBT project decided that the initial tests will take place at CERN. As a key contributor SMU will need to send a designer to CERN for this first evaluation. During this time, valuable experience will be gained in testing (and running) lpGBT. This experience will be critical in developing the FEB2 link. Past experience on the GBTx testing indicate that this is a task of about 6 months. (WBS 6.4.1.34.1)

Uncosted Labor

COLUMBIA UNIVERSITYThe electronics development performed at Nevis is an excellent opportunity for physicists early

in their career to gain valuable experience and expertise in state-of-the-art instrumentation development. We have a long history of involving postdocs and graduate students in our hardware developments.

We anticipate having ~20 weeks (0.4 FTE) of graduate student contribution each year, mostly in the summer periods when we typically have 2 graduate students (who have not yet completed their coursework and therefore have not yet moved to CERN) spend 10 weeks each working in the lab at Nevis.

The physicists’ role will be primarily in testing. The data analysis skills of the physicists are critical for understanding the testing results. Graduate students and postdocs will setup the test stand, write software and carry out the testing of the devices during development.

UT-AUSTIN We benefit from having 10 weeks (0.4 FTE) of graduate student contribution each year, mostly

in the summer periods when we typically have 2 graduate students (who have not yet completed their coursework and therefore have not yet moved to CERN) spend 10 weeks each working in the lab at UT Austin. We also have undergrads (outside of QA/QC testing) working on the testing, when a suitable project is found that matches their experience.

The physicists’ role will be primarily in testing. The data analysis skills of the physicists are critical for understanding the testing results. Graduate students and postdocs will setup the test stand, write software and carry out the testing of the devices during development. They will also conduct the irradiation tests. During the production phase physicists will setup the large-scale test stations and oversee undergraduates in testing the chips.

SMU of 41

The SMU upgrade projects offers grad students (~1/summer) an opportunity to gain experience with electronics development. They will be trained in testing in the lab, and contribute during all phases of the project. The physicists’ role will be primarily in testing. The data analysis skills of the physicists are critical for understanding the testing results. During the production period, graduate students (3.0 FTE) will be needed to carry out the screening of the chips in the QA process (lpGBT screening).

Estimating Method: UPDATE

2%

22%

42%

34%

Estimating Method

Existing PO or Work CompleteExtrapolating from ActualsAnalogyExpert Opinion

Assumptions: o We assume a baseline FEB2 architecture with digitization and read out of all LAr

channels at 40 MHz and that the chips are produced in the 65 nm TMSC CMOS technology through CERN. (Risks ADC 1 and 2)

o We assume that the lpGBT and VL+ projects will meet their target milestones (Risk lpGBT 1 and VL+ 1)

Schedule:

Based on the Phase-I experience, in which subsequent iteration of chip designs were submitted in, we anticipate a yearly schedule of Pre-prototype chip submissions from 2017 through 2020, and continuing annually for the Prototype and Production submissions. This includes three Pre-prototype chips (Pre-prototype chip 2 and 3 the ATLAS PDR and ATLAS FDR respectively), and the Prototype chip, used to populate the prototype FEB2 board.

Following the PRR review, we anticipate a final iteration (allowing approximately 6 months) of the designs, before production begins. For the optical link components production takes place from 2021 to 2022. For the ADC chip, production extends from 2022 through 2023, due to the larger number of chips produced.

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Summary: 1. start of project – early 2018: Pre-prototype chip 1, submitted mid-2017, testing late 20172. start of 2018 – early 2019: Pre-prototype chip 2, Milestone: ATLAS PDR late-20183. start of 2019 – early 2020: Pre-prototype chip 3, Milestone: ATLAS FDR late-20194. start of 2020 – 2021: Prototype chip for FEB2 prototype, Milestone: ATLAS PRR late-20205. start of 2022 – 2023: Production followed by testing in batches.

Risk Analysis:

In Risk Register

List of Attachments 1. Summary of Estimated FedEx Shipping Costs per Shipment, for Various Destinations2. QuickPak quote for ADC packaging3. Mask and wafer quote from CERN4. Quote for license for CADENCE design software for Columbia5. Test Jigs for ADC, 5 spreadsheets of actual costs.6. Quote for GBTx and VLTX and VLRX7. MGH beam quote8. Test jig for Phase 1Phase-I optics. 9. SMU flight cost table10. UT Austin flight cost table 11. List of purchases in CHF12. SMU Quotation for PCB board purchase13. SMU actual purchase of QFN sockets 14. SMU Quotation for SMU PCB assembly

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Attachments:

COLUMBIA UNIVERSITY

1. Summary of Estimated FedEx Shipping Costs per Shipment, for Various Destinations

FEDEX SHIPPING QUOTES 12/11/15

DESTINATION WEIGHT DIMS VALUE SERVICE CLASS COST

AUSTIN, TX 78712 328 LBS 48X48X48 $40,000.004-DAY ECONOMY 150 $979.23

BNL, NY 11973 328 LBS 48X48X48 $40,000.004-DAY ECONOMY $448.04

PARIS, FR 91405 328 LBS 48X48X48 $40,000.00

7-8 DY INTL ECONOMY $5,136.35

GVA CH 1211 328 LBS 48X48X48 $40,000.00

7-8 DY INTL ECON $6,003.00

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Attachment 2

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Attachment 3 – trying to get something more up-to-date and formal

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Attachment 4 (above)

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Attachment 5 (below):

NEVIS12 ADC Radiation Testboard PCB Fabrication Costs Non-Recurring Engineering (NRE) $550.00

Quantity and Cost per PCB6 X

323.13 $1,938.78 PCB Assembly Costs Non-Recurring Enginneering (NRE) $550.00


290.00 $1,450.00 Component Costs $2,395.17 Total Cost $6,883.95

NEVIS13 ADC Radiation Testboard PCB Fabrication Costs Non-Recurring Engineering (NRE) $600.00


279.80 $1,399.00 PCB Assembly Costs Non-Recurring Engineering (NRE) $875.00



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LArTDS Radiation Testboard PCB Fabrication Costs Non-Recurring Engineering (NRE) $650.00


890.30 $4,451.50 PCB Assembly Costs Non-Recurring Engineering (NRE) $500.00 Quantity and Cost per PCB 2 X 750 $1,500.00 Component Costs $3,055.31 Total Cost $10,156.81

NEVIS PhaseI ADC QA/QC Testboard PCB Fabrication Costs Non-Recurring Engineering (NRE) $600.00


180.63 $1,445.04 PCB Assembly Costs Non-Recurring Engineering (NRE) $1,500.00



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COLUTA65V1 ADC Testboard PCB Fabrication Costs Non-Recurring Engineering (NRE) $1,250.00


343.58 $3,435.80 PCB Assembly Costs Non-Recurring Engineering (NRE) $1,950.00



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Attachment 6:

Updated: 5/3/2017---------------------Hi John,

Here are a few estimates (note these are estimates and could change):

- lpGBT. We assume a similar cost as the GBTX, i.e. 35 CHF per chip- VL+. It is assumed 30 CHF per fibre channel, i.e. 120 CHF for a quad link- the GBT chipset cost is:- GBTX 35 CHF- GBT-SCA 20 CHF- VTTX 100 CHF- VTRX 130 CHF- The cost of access to TSMC technos (130 and 65 nm) is going to beupdated soon. It will decrease. As soon as we have news, I’ll let you know.

Cheers, Philippe--------------------

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Attachment 7UT AUSTIN

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Attachment 8 SMU costs for PCB assembly for Phase 1Phase-I LOC (part of Phase 1Phase-I optics development). From US ATLAS PHASE I Upgrade BOE ADC-Optical Link interface & Data Serialization ASIC LOCx2.

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Attachment 9SMU flight costs to CERN 2016-2017

Date Cost 6-Jul-17 $3,084.06

10-Jun-17 $1,560.86 19-May-17 $1,706.66 31-Mar-17 $2,079.86 25-Mar-17 $1,715.16 10-Feb-17 $1,336.06 27-Jan-17 $1,826.26

3-Jan-17 $1,336.76 21-Sep-16 $1,328.86 12-Jul-16 $1,851.96

Average $1,782.65

Attachment 10UT Austin flight costs to CERN.Date Cost

1-Jul-17 $3,134.1622-May-17 $2,133.6614-Feb-17 $1,183.1628-Nov-17 $2,637.2612-May-16 $1,512.46

4-May-16 $1,591.0627-Feb-16 $1,278.26

Average $1,924.29

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Attachment 11 – List of purchases in CHFColumbia

FEE410040M Material for Pre-Prototype 1 ADC SubmissionFEE410190M Material for Pre-Prototype 2 ADC SubmissionFEE410300M Material for Pre-Prototype 3 ADC SubmissionFEE410410M Material for Prototype ADC SubmissionFEE410520M Material for Production ADC Submission SMU6.04.01.03.03 NEW Material : lpGBT for FEB2 prototype, 480 @ $35

FEE30345M Material: lpGBT Production - 41,400 IpGBT @ $35 each , 67% cost sharingFEE30495M Material: VL+ OTX For FEB2 prototype - 160 VL+ @ $120 eachFEE30555M Material: VL+OTX production - 13,800 VL @120 each, 67% cost sharing

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Attachment 12SMU Quotation for PCB board purchase

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Attachment 13SMU actual purchase of QFN sockets

\

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Attachment 14Quotation for SMU PCB assembly

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