UNIT-V-PART-II

Fault ModelA Fault Model is a description, at the digital logic level, of the effects of some fault or combination of faults in th e underlying circuitry. The use of fault models has some advantages and also some disadvantages. · Advantages o Technology independant. o Works quite well in practice. · Disadvantages o May fail to identify certain process specific faults, for instance CMOS floating gates.

Detects static faults only. Types of Fault models

Stuck at 0 fault Stuck at 1 fault Bridging fault Stuck open fault Stuck closed fault

1 Fault models :A defect is a manufacturing flaw or physical imperfection that may lead to a fault, a fault can cause a circuit error, and a circuit error can result in a failure of the device or system. Because of the diversity of defects, it is difficult to generate tests for real defects. Fault models are necessary for generating and evaluating test patterns. Generally, a good fault model should satisfy two criteria: (1) it should accurately reflect the behavior of defects and (2) it should be computationally efficient in terms of time required for fault simulation and test generation.

fault models for general sequential logic

1. Gate-level stuck-at fault model: The stuck-at fault is a logical fault model that has been used successfully for decades. A stuck-at fault transforms the correct value on the faulty signal line to appear to be stuck-

at a constant logic value, either logic 0 or 1, referred to as stuck-at-0 (SA0) or stuck-at-1 (SA1), respectively. This model is commonly referred to as the line stuck-at fault model where any line can be SA0 or SA1, and also referred to as the gate-level stuck-at fault model where any input or output of any gate can be SA0 or SA1. 2. Transistor-level stuck fault model: At the switch level, a transistor can be stuck-off or stuck-on, also referred to as stuck-open or stuck short, respectively. The line stuck-at fault model cannot accurately reflect the behavior of stuck-off and stuck-on transistor faults in complementary metal oxide semiconductor (CMOS) logic circuits because of the multiple transistors used to construct CMOS logic gates. A stuck open transistor fault in a CMOS combinational logic gate can cause the gate to behave like a level-sensitive latch. Stuck-short faults, on the other hand, can produce a conducting path between power (VDD) and ground (VSS) and may be detected by monitoring the power supply current during steady state, referred to as IDDQ. This technique of monitoring the steady state power supply current to detect transistor stuck-short faults is called IDDQ testing.

3. Bridging fault models: Defects can also include opens and shorts in the wires that interconnect the transistors that form the circuit. Opens tend to behave like line stuck-at faults. However, a resistive open does not behave the same as a transistor or line stuck-at fault, but instead affects the propagation delay of the signal path. A short between two wires is commonly referred to as a bridging fault. The case of a wire being shorted to VDD or VSS is equivalent to the line stuck-at fault model. However, when two signal wires are shorted together, bridging fault models are needed; the three most commonly used bridging fault models are illustrated in Figure The first bridging fault model proposed was the wired-AND/wired-OR bridging fault model, which was originally developed for bipolar technology and does not accurately reflect the behavior of bridging faults typically found in CMOS devices. Therefore, the dominant bridging fault model was proposed for CMOS where one driver is assumed to dominate the logic value on the two shorted nets. However, the dominant bridging fault model does not accurately reflect the behavior of a resistive short in some cases. The most recent bridging fault model, called the 4-way bridging fault model and also known as the dominant-AND/dominant-OR

bridging fault model, assumes that one driver dominates the logic value of the shorted nets for one logic value only .

Follow the regular notes for diagrams

Test vector generation techniques for combinational circuits:

a) Fault tables b) Fault simulation

c) Boolean differencesd) Path sensitization

Path Sensitizing

Figure illustrates a path from input w1 to output f , through three gates, whichconsists of wires a, b, c, and f . The path is activated by ensuring that other paths in the circuit do not determine the value of the output f . Thus the input w2 must be set to 1 so that the signal at b depends only on the value at a. The input w3 must be 0 so that it does

not affect the NOR gate, and w4 must be 1 to not affect the AND gate. Then if w1 = 0 the output will be f = 1, whereas w1 = 1 will cause f = 0. Instead of saying that the path from w1 to f is activated, a more specific term is used in technical literature, which says that the path is sensitized.To sensitize a path through an input of an AND or NAND gate, all other inputs must be set to 1. To sensitize a path through an input of an OR or NOR gate, all other inputs must be 0.Consider now the effect of faults along a sensitized path. The fault a/0 in Figure will cause f = 1 even if w1 = 1. The same effect occurs if the faults b/0 or c/1 arepresent. Thus the test w1w2w3w4 = 1101 detects the occurrence of faults a/0, b/0, and c/1.Similarly, if w1 = 0, the output should be f = 1. But if any of the faults a/1, b/1,

or c/0 is present, the output will be f = 0. Hence these three faults are detectable using the test 0101. The presence of any stuck-at fault along the sensitized path is detectable by applying only two tests.

Design for Testability

DFT makes it possible to: Assure the detection of all faults in a circuit Reduce the cost and time associated with test development Reduce the execution time of performing test on fabricated chips

Chip level DFT technique is called Built-in self-test (BIST) (used for digitallogic and memory.)At the system level, DFT includes boundary scan and analog test bus.

A synchronous sequential circuit comprises the combinational circuit that implements the output and next-state functions, as well as the flip-flops that hold the state information during a clock cycle. A general model for the sequential circuits is shown in Figure The inputs to the combinational network are the primary inputs, w1 through wn, and the present state variables, y1 through yk . The outputs of the network are the primary outputs, z1

through zm, and the next-state variables, Y1 through Yk . The combinational network p[;;could be tested using the techniques presented in the previous sections if it were possible to apply tests on all of its inputs and observe the results on all of its outputs. Applying the test vectors to the primary inputs poses no difficulty. Also, it is easy to observe the values on the primary outputs. The question is how to apply the test vectors on the present-state inputs and how to observe the values on the next-state outputs.A possible approach is to include a two-way multiplexer in the path of each present-state variable so that the input to the combinational network can be either the value of the state variable or the value that is a part of the test vector.

Scan-Path TechniqueA popular technique, called the scan path, uses multiplexers on flip-flop inputs to allow the flip-flops to be used either independently during normal operation of the sequential circuit, or as a part of a shift register for testing purposes. Figure presents the general scan-path structure for a circuit with three flip-flops. A 2-to-1 multiplexer connects the D input of each flip-flop either to the corresponding next-state variable or to the serial path that connects all flip-flops into a shift register.

The control signal Normal/Scan selects the active input of the multiplexer. During the normal operation the flip-flop inputs are driven by the next-state variables, Y1, Y2, and Y3.For testing purposes the shift-register connection is used to scan in the portion of each test vector that involves the present-state variables, y1, y2, and y3. This connection has Qi connected to Di+1. The input to the first flip-flop is the externally accessible pin Scan-in. The output comes from the last flip-flop, which is provided on the Scan-out pin.The scan-path technique involves the following steps:

1. The operation of the flip-flops is tested by scanning into them a pattern of 0s and 1s,

for example, 01011001, in consecutive clock cycles, and observing whether the same pattern is scanned out.2. The combinational circuit is tested by applying test vectors on w1w2 ・ ・ ・wny1y2y3 and observing the values generated on z1z2 ・ ・ ・ zmY1Y2Y3. This is done as follows:• The y1y2y3 portion of the test vector is scanned into the flip-flops during threeclock cycles, using Normal/Scan = 1.• The w1w2 ・ ・ ・wn portion of the test vector is applied as usual and the normal operation of the sequential circuit is performed for one clock cycle, by setting Normal/Scan = 0. The outputs z1z2 ・ ・ ・ zm are observed. The generated values of Y1Y2Y3 are loaded into the flip-flops at this time.• The select input is changed to Normal/Scan = 1, and the contents of theflip-flops are scanned out during the next three clock cycles, which makes the Y1Y2Y3 portion of the test result observable externally. At the same time, the nexttest vector can be scanned in to reduce the total time needed to test the circuit.The next example shows a specific circuit that is designed for scan-path testing.

Built-in Self-TestFigure shows a possible BIST arrangement in which a test vector generatorproduces the test vectors that must be applied to the circuit under test.For each test vector applied to the circuit, it is

necessary to determine the required response of the circuit. The expected responses to the applied tests must be stored on the chip so that a comparison can be made when the circuit is being tested.A practical approach for generating the test vectors on-chip is to use pseudorandom tests, which have the same characteristics as random tests but are produced deterministically and can be repeated at will. The generator for pseudorandom tests is easily constructed using a feedback shift-register circuit. A small example of a possible generator is given in Figure. A four-bit shift register, with the signals from the first and fourth stages fed back through an XOR gate, generates 15 different patterns during successive clock cycles.If the shift register is set at the beginning to x3x2x1x0 = 1000, then the generated patterns are as shown in part (b) of the figure. Observe that the pattern 0000 cannot be used, because the circuit would be locked in this pattern indefinitely.The circuit in Figure is representative of a class of circuits known as linearfeedback shift registers (LFSRs). Using feedback from the various stages of an n-bit shift register, connected to the first stage by means of XOR gates, it is possible to generate a

sequence of 2n − 1 patterns that have the characteristics of randomly generated numbers.The pseudorandom binary sequence generator (PRBSG) gives a simple method ofgenerating tests. A practical solution is to compress the results of the tests into a single pattern. This can be done using an LFSR circuit. Instead of just providing the feedback signals as the input, a compressor circuit includes the output signals produced by the circuit under test.Figure shows a single-input compressor circuit (SIC), which uses the same feedback connections as the PRBSG of Figure. The input p is the output of a circuit under test. After applying a number of test vectors, the resulting values of p drive the SIC and, coupled with the LFSR functionality, produce a four-bit pattern. The pattern generated by the SIC is called a signature of the tested circuit for the given sequence of tests. The signature represents a single pattern that may be interpreted as a result of all the applied tests. It can be compared against a predetermined pattern to see if the tested circuit is working properly.If the circuit under test has more than one output, then an LSFR with multiple inputs can be used. Figure illustrates how four inputs, p0 through p3, can be added to the basic circuit of Figure. Again the four-bit signature provides a good mechanism for distinguishing among different sequences of four-bit patterns that may appear on the inputs of this multiple-input compressor circuit (MIC).

A complete BIST scheme for a sequential circuit may be implemented as indicated in Figure. The scan-path approach is used to provide a testable circuit. The test patterns that would normally be applied on the primary inputs W = w1w2 ・ ・ ・wn are generated internally as the patterns on X = x1x2 ・ ・ ・ xn. Multiplexers are needed to allow switching from W to X , as inputs to the combinational circuit.

A pseudorandom binary sequence generator, PRBSG-X , generates the test patterns for X . The portion of the tests applied via the next-state signals, y, is generated by the second PRBS generator, PRBSG-y. These patterns are scanned into the flip-flops .The test outputs are compressed using the two compressor circuits. The patterns onthe primary outputs, Z = z1z2 ・ ・ ・ zm, are compressed using the MIC circuit, and those on the next-state wires Y = Y1Y2 ・ ・ ・ Yk , by the SIC circuit. These circuits produce the Z-signature and Y -signature, respectively. at the end of the testing process the two signatures are compared with the stored patterns.

The effectiveness of the BIST approach depends on the length of the LFSR generator and compressor circuits.

Built-in Logic Block Observer

The essence of BIST is to have internal capability for generation of tests and for compression of the results. Instead of using separate circuits for these two functions, it is possible to design a single circuit that serves both purposes. Figure shows the structure of a possible circuit, known as the built-in logic block observer (BILBO) .This four-bit circuit has the same feedback connections as the circuit of Figure. The BILBO circuit has four modes of operation, which are controlled by the mode bits, C0 and C1. The modes are as follows:

. An efficient way of using BILBO circuits is presented in Figure. A combinationalcircuit can be tested by partitioning it into two (or more) parts. A BILBO circuit is used to provide inputs to one part and to accept outputs from the other part. The testing process involves a two-phase approach. First, BILBO1 is used as a PRBS generator that provides test patterns for combinational network 1 (CN1). During this time BILBO2 acts as a compressor and produces a signature for the test. The signature is shifted out by placing BILBO2 into the shift-register mode. Next, the roles of BILBO1 and BILBO2 are reversed, and the process is repeated to test CN2.

Boundary scan test (BST)This is a technique involving scan path and self-testing to resolve the problems associated with the testing of boards carrying VLSI circuits and/or surface-mounted devices (SMD). Printed circuit boards (PCBs) are becoming very dense and complex, especially with SMD circuits, so that most test equipment cannot guarantee a good fault coverage.BST consists of placing a scan path (shift register) cell adjacent to each component pin and to interconnect the cells so as to form a chain around the border of the circuit. The BST circuits contained on one board are then connected together to form a single path. The general idea is illustrated in Figure .The boundary scan path is provided with serial input and output pads and appropriate clock pads which make it possible to:

• test the interconnections between the various chips on the board;• deliver test data to the chips on the board for self-testing;• test the chips themselves with internal self-test facilities.

The advantages of BST are seen as follows:• no need for complex testers in PCB testing;• the test engineer's work is simplified and efficient;• the time spent on test pattern generation and application is reduced;• fault coverage is increased.