Web publication On-chip ESD protection for High Voltage

Web publication On-chip ESD protection for High Voltage

applications in TSMC BCD technology

EETimes March 5th, 2012

A growing set of IC applications require a high voltage interface. Examples include power management, power conversion and automotive chips with interfaces typically between 12 V and 100 V. Also, mobile devices like cell phones and personal navigation devices today include interfaces above 10 V to, e.g., control and sense MEMS gyroscopic or compass sensors. And most LCD/OLED display technologies require driving voltages between 10 and 40 V. Besides the power, MEMS, and display interfaces, many devices include some sort of motor like the optical zoom lens and shutter control of digital cameras or the ‘silent mode’ vibrator in cell phones…

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On-chip ESD protection for High Voltageapplications in TSMC BCD technology

B. Keppens, K. Verhaege

3/5/2012 10:14 AM EST

IntroductionA growing set of IC applications require a high voltage interface. Examples include power management,

power conversion and automotive chips with interfaces typically between 12 V and 100 V. Also, mobile

devices like cell phones and personal navigation devices today include interfaces above 10 V to, e.g., control

and sense MEMS gyroscopic or compass sensors. And most LCD/OLED display technologies require

driving voltages between 10 and 40 V. Besides the power, MEMS, and display interfaces, many devices

include some sort of motor like the optical zoom lens and shutter control of digital cameras or the ‘silentmode’ vibrator in cell phones.

Though these applications represent fast-growth markets, the underlying silicon process technologies lack

standardized high-performance ESD solutions. The purpose of ESD protection is to provide a safe, robust

current path while limiting the voltage drop below the critical voltage determined by the circuit to beprotected. Today, different protection clamp types are used in the industry, each with significant performance

and cost burdens that prevent generic use. The main problems with traditional solutions are high leakage

current, large silicon area consumption, and extensive custom (trial and error) development cycles for each

process/fab change.

Despite the efforts from the ‘ESD council’ to reduce the component-level ESD performance levels [1-2],there is an opposing trend to push system-related ESD/latch-up requirements down to the IC design level in

order to reduce system failures and improve user safety [3-4]. This is most prevalent in automotive, industrialand consumer electronics markets. OEMs request very robust and latch-up immune on-chip ESD protection

devices [5].

Requirements for high voltage ESD clampsForemost, an ESD clamp needs to protect the chip circuitry. The circuit can be an entire power domain

(supply pin protection) or a single input, output, or I/O circuit (I/O pin protection).

ESD protection is typically qualified using human-body model (HBM), machine model (MM), and charged-

device model (CDM) testers. For an in-depth analysis however, Transmission Line Pulse (TLP) testers are

used to characterize the ESD relevant performance parameters of the protection clamps as shown in Figure

1.



Figure 1: Generic clamp behavior based on TLP analysis. The clamp remains off until the trigger voltage ‘Vt1’

is reached. The clamping mode is characterized by a holding voltage ‘Vh’ and the on-resistance ‘Ron’. Theclamp failure current is called ‘It2’.

While ESD devices are routinely characterized with TLP to determine their optimal design, additional analysis

is required. There are 4 main problems with TLP measurements that are relevant for this discussion:

The TLP characteristic is based on averaged values of voltage and current waveforms versus time;hence the TLP IV curve hides relevant time dependent behavior [6-8].

The TLP pulse width is typically limited to 100 ns; that is enough for ESD-relevant analysis, but it is notrelevant for electrical overstress (EOS), which has a much larger timeframe.TLP measurements are performed on 2 pins, leaving other pins floating. No bias is applied at VDD

and many latch-up issues remain undetected [9].Most commercial TLP systems have 50-Ω characteristic impedance, not suited for analysis of high-

voltage snapback clamps [8, 10].

Therefore, in addition to standard TLP analysis, it is important for high-voltage applications to look carefully

into the full waveform information and to include longer pulse durations in the evaluation. This is evident fromFigure 2: the voltage versus time waveform of the High Voltage SCR (large anode-cathode spacing) shows

that the device has a clamping regime well above VDD for the first 100 ns (TLP time domain – highlighted bythe rectangle). However the clamp voltage decreases below the VDD voltage for longer pulse duration. This

means that latch-up issues may occur when this device is used as ESD protection clamp under transient latch-up situations like some EOS and IEC 61000-4-2 stress situations.



Figure 2: Voltage versus time waveform characterization of a basic high-voltage SCR device in 0.35-µm 15-

V CMOS. The voltage waveform is measured with a TLP-like setup using solid-state pulse generators with amuch longer pulse width (500 ns instead of the TLP standard 100 ns duration). Within the 100-ns TLP

window, the measured holding voltage is high enough, however the voltage drops below the supply level after

250 ns… which can lead to latch-up.

Other measurement approaches exist to verify the transient latch-up susceptibility. Professor Ker fromTaiwan, for instance, tends to use a system depicted in Figure 3 [11-13]. First, a DC bias of VDD (40 V in

the example) is applied to the device under test. Secondly, a sharp pulse is superimposed on the DC level byconnecting a charged capacitor to the biased device. Such a test has many different names depending on

actual conditions: Vlatch, Charged Capacitance Latch-up (CCL) [14], transient latch-up [15], orESD/Machine Model (MM) under powered conditions. It can also be simulated with a multi-level TLP

approach [16]. Due to this pulse, the ESD protection clamp will turn on to shunt the ESD current. If theclamp is latch-up immune, the voltage returns to the initial DC bias level once the superimposed MM pulse isover. When performing such transient latch-up tests, it is important to use a fast and low-resistance power

supply for the DC bias.

When such a test is applied on a HV grounded-gate (gg) NMOS device, the latch-up problem is clearlydemonstrated (Figure 3 bottom). After the ESD pulse, the voltage quickly drops to a low value of about 7 V

and remains latched at that low value until the end of the test or failure of the NMOS device.



Figure 3: Transient latch-up setup described by professor Ker (top). A charged 200-pF capacitor isdischarged into a biased device under test. When such a pulse is imposed on a HV-NMOS device in a 40-V

technology, the latch-up problem is clearly visible (bottom).

Finally, in real world applications, end-user systems can receive multiple ESD stress pulses over the productlifetime. HV-NMOS-based protection devices are prone to degradation issues. The example given below

(Figure 4) shows two TLP measurements of identical grounded-gate HV NMOS snapback clamps in a 0.5-

um (43-V) technology [17].

After snapback, at roughly 73 V, a clear and steady degradation is visible in the leakage current. Different

TLP stress step levels are used. The data shows that the final failure current (device leakage in µA order of

magnitude) is dependent on the pulse density [18]. When a small stress step is applied, the failure current ismuch lower.



Figure 4: TLP curves on HV-NMOS devices in a 0.5-um 43-V process technology. The TLP stress isapplied to 2 identical devices, one with large steps (low pulse density) and one with small steps (high pulse

density). Due to the degradation effect, the number of stress pulses strongly influences the failure current It2.

BCD technology

Most foundries provide a complete portfolio of process technologies and options targeted at high-voltage

applications like display driver ICs, power management, and automotive applications. Process options

typically include high-voltage capacitors, resistors, Zener diodes, and thick top metals. Ultra-High Voltage(UHV) options ranging from 500 to 800 V are also available for "green technology" switching mode power

supply designs. The power management market in particular is quickly growing as every electronic device

needs one. Bipolar-CMOS-DMOS (double-diffused MOS) – or BCD – platforms are good candidates for

all kinds of automotive ICs, another fast-growing segment.

In high-voltage IC applications, process flexibility is an important aspect. Every high-voltage interface has its

own set of requirements; each project is different. Therefore TSMC has defined a modular approach whereIC designers can select the most appropriate modules and voltage domains. In the 0.25um BCD platform for

instance designers can use different transistor modules (2.5V, 5V, 12V, 24V, 40V and 60V) and have 3

options for the core gate voltage (2.5, 5 or 12V).

Sofics has compared different protection concepts first on TSMC’s 0.35-µm 15-V process. Next, with thehelp of TSMC9000™ IP and Library/IP Quality Management Program LQMP divisions, Sofics has

performed a full characterization on TSMC’s 0.25-µm BCD and 0.18-µm BCD platforms.

Comparison of traditional ESD solutionsToday IC designers use a variety of ESD protection devices to protect integrated circuits against ESD stress.The following non-exhaustive overview highlights the main types.

1. Zener diodes

Zener-based protection devices have been around for a long time. The characteristic behavior is depicted in

Figure 5 (type ‘a’). The breakdown and holding voltage are above the supply voltage level ensuring latch-up-immune ESD protection. Zener diodes can be applied in many technology nodes, though there are many

drawbacks for ESD protection:



The ESD robustness level per micron device width is rather low, which leads to a large device size.

The large device size means that the capacitance and leakage values are higher than any other device

type when scaled to the same protection level.For many circuits, the Zener device cannot provide effective protection due to too high a holding

voltage.

2. RC-MOS (or BIGfet)This dynamically-triggered MOS transistor is extensively used in low-voltage technology nodes for general-

purpose I/O libraries [19, 20]. The characteristic behavior is depicted in Figure 5 (type ‘b’). The MOS

device is biased such that all the ESD current is shunted in the active MOS conduction mode while it is turned

off during normal operation. Many different configurations exist to tune the device behavior (timing, boosted

bias, false-trigger prevention). However, in high-voltage technologies, the application of RC-MOS devices is

less straightforward, typically leading to large area consumption, even for a low ESD HBM protection level[21, 22].

3. PMOS, PNP

The HV-PMOS device has a characteristic similar to the Zener device (Figure 5, type ‘a’), however the ESD

performance is very process-dependent. In ‘good’ technology nodes, the robustness level per micron device

width is higher than the Zener device due to the bipolar PNP action. This results in a somewhat better

performance for the leakage and silicon area consumption. Moreover, due to a lower breakdown and holdingvoltage as compared to the Zener diode, the device is typically better suited to protect sensitive circuits.

4. NMOS, NPN

Designers use NMOS and NPN based approaches because the It2 robustness level is higher compared to

the 3 previous device types, leading to smaller silicon area and reduced leakage. However, degradation

issues due to non-uniform triggering are a major problem, as reported and documented by various sources

(see Figure 4) [5, 17, 23]. In addition, a key issue is latch-up weakness due to a low holding voltage,typically far below the supply voltage. This characteristic behavior is depicted in Figure 5-c.

5. SCR

Finally, for some high-voltage signal pins it is possible to rely on Silicon Controlled Rectifier (SCR)-based

protection devices [5, 24]. SCRs have superb ESD characteristics with low leakage and low capacitance but

require careful holding and trigger current control to avoid latch-up problems [14]. The characteristic

behavior of the basic SCR device is depicted in Figure 5 (type ‘d’) while an improved latch-up high-holding-

current (HHI) SCR approach is shown as type ‘e’ [14, 17, 25, 26].

This overview is based on benchmarking of devices across high-voltage technologies from various foundries

and IDMs. Exceptions exist where, e.g., a process is modified to enhance the ESD properties of the Zener

diode [5]. Clearly, within the existing device pool there is no generic and no optimal solution. It basically

comes down to a selection between a cost-effective design (NPN, SCR) with major latch-up immunity

weakness or a guaranteed latch-up-immune design that occupies a huge chip area (Zener diode, PMOS). A

single, generic device that solves all the different aspects would greatly simplify IC design in HVCMOS andBCD process technology.



Figure 5: Simplified behavior of the main ESD solution types used for protection of high voltage interfaces: (a)

Zener diode, (b) RC MOS, (c) NMOS or NPN device, (d) Basic SCR, (e) HHI-SCR, (f) Novel hebistor

clamp

Herbistor clamps for ESD protectionAn improved clamp, referred to here as a “hebistor” clamp, is designed to be extremely flexible. The key

behavioral parameters like trigger voltage, holding voltage, and failure current can be set independently from

each other as graphically shown on Figure 6. Separate control circuits are used for the holding (Vh) and

trigger (Vt1) voltage. The size of the clamp body determines the failure current (It2). All variations are based

on layout changes only, there is no process tuning involved.

Figure 6: Generic overview of a hebistor device: thanks to separate control circuits for the trigger and holding

voltage the key parameters can be set independently.



For instance, the trigger voltage Vt1 can be set to meet specific requirements. Some high-voltage interfacesoperating at 20 V, for instance, require a trigger voltage above 40 V. This trigger-voltage tuning is obtained

through the connection of external (separate from the clamp body) and interchangeable trigger circuits. The

trigger circuits are based on well-known basic building blocks available in the process technology like

forward diodes, Zener diodes, MOS transistors, RC timing filters, or combinations of these elements.

Secondly, the holding voltage of the hebistor clamps can be defined by layout changes in the holding circuit.

The holding voltage can then be further optimized through layout adaptations in the holding circuit.

As explained in section I, during the development of ESD devices in high-voltage technology, one should use

other equipment besides TLP testers to validate latch-up properties and leakage. Therefore, extensive

waveform analysis was performed (see Figure 7 for a 40-V clamp example) to investigate the holding voltage

under long-duration stress. Clearly, the holding voltage does not drop below the supply voltage even under

longer pulse durations.

Figure 7: The voltage waveform for a 40-V clamp after triggering shows that the holding voltage remains

above 50 V even for long pulses.

The hebistor device behavior was also checked with various transient latch-up approaches. One such test

consisted of a 100-ns TLP pulse of 1 ampere that is superimposed on a 50-V DC bias level. Figure 8 shows

the voltage and current waveforms captured during the test for the 40-V reference clamp. At about 100 ns

from the start of the measurement, the biased (50-V) device is stressed with a high-amplitude (1-A) TLP

pulse. The bottom (green) waveform shows the current flowing through the device. After the TLP pulse is

over, the bias voltage is restored to 50 V while the current through the device is reduced to the level before

the ESD stress (hebistor leakage current). The overshoot and undershoot are related to a combination ofdevice response and test system parasitic inductance.



Figure 8: Transient latch-up test where a 1-Ampere TLP pulse is superimposed on a 50-V bias level. Afterthe TLP pulse, the voltage returns to 50 V while the current through the clamp returns to the (leakage) level

before the TLP pulse. The hebistor clamp does not remain latched.

Conclusion

While high-voltage interfaces are used in many IC applications like motor control, power management and

conversion, LCD panel drivers, and automotive systems, IC designers still lack a low-leakage, cost-effective

and latch-up immune ESD protection clamp.

IC designers worldwide continue to produce very creative systems and applications based on HVCMOS or

BCD technology nodes, but the ESD protection clamps have almost not evolved: the industry is still using

large-area, highly leaky clamps that typically require extensive process tuning and time-consuming trial-and-

error experiments and analysis.

One example of a novel ESD clamp is Sofics’ hebistor clamp, evaluated through extensive analysis on

TSMC’s high-voltage platforms like 0.35-µm 15-V, 0.25-µm and 0.18-µm BCD technology. It is currentlyused in the development of products on TSMC’s 0.35-µm 15-V and 0.18-µm 18-V BCD platforms. It is

also being evaluated for automotive products in TSMC’s 0.25-µm 40-V technology. The 40-V solution has

passed very severe automotive requirements like a 45-V load dump (ISO 7637-2) and various transient

latch-up conditions.

The hebistor devices provide immunity for various industry standard requirements, including transient latch-

up, long pulse durations, and high temperature conditions and allow customization for any set of requirements.

References

[1] White Paper, “A case for lowering component level HBM/MM ESD specification and requirements”,

2007 http://www.esdforum.de/

[2] White Paper, “Recommended ESD-CDM Target Levels”, 2009, JEP157.

http://www.jedec.org/standards-documents/results/JEP157ESD council

[3] P. Besse (Freescale), “ESD / EMC in an automotive environment”, IEW 2010

[4] C. Lippert (Audi), “Future Challenges of ESD Protection – an Automotive OEM’s Point of View”,IEW 2010

[5] M. Mergens et al., “ESD Protection Considerations in Advanced High-Voltage Technologies for

Automotive”, EOS/ESD 2006

[6] G. Wybo et al., “Characterizing the Transient Device Behavior of SCRs by means of VFTLP



Waveform Analysis”, EOS/ESD 2007

http://www.sofics.com/files/paper/2007%20ESD%20SCR%20transient%20X.pdf

[7] B. Keppens et al., “Using the Voltage and Current Waveforms from VFTLP systems to study transient

device behavior”, RCJ 2006 http://www.sofics.com/files/paper/2006%20RCJ%20VFTLP%20X.pdf

[8] M. Scholz et al, “ESD on-wafer characterization: Is TLP still the right measurement tool?”, IEEE

Transactions on Instrumentation and Measurement, 2009

[9] G. Wybo et al., “Analysis Methodology for Latch-up: Realistic Worst Case Stress Conditions for theCurrent Injection ‘I-test’”, RCJ 2008

http://www.sofics.com/files/paper/2008%20RCJ%20latchup%20X.pdf

[10] M. Scholz et al, “HBM Transient Safe Operating Area –A case study”, accepted for presentation at

EOS/ESD 2010

[11] M.D. Ker et al., “Transient-induced latchup in CMOS technology: physical mechanism and device

simulation”, IEDM 2004

[12] M.D. Ker et al., “Evaluation on Board-Level Noise Filter Networks to Suppress Transient-InducedLatchup under System-Level ESD Test”, EOS/ESD 2005

[13] M.D. Ker et al., "Design on Latchup-Free Power-Rail ESD Clamp Circuit in High-Voltage CMOS

ICs", EOS/ESD 2004

[14] Y. Fukuda et al., “Solving the problems with traditional Silicon Controlled Rectifier (SCR) approaches

for ESD”, RCJ 2008 http://www.sofics.com/files/paper/2008%20RCJ%20SCR%20X.pdf

[15] ESDA Working group 5.4 “Transient-induced latchup in CMOS technology: physical mechanism and

device simulation”, 2000[16] T. Daenen et al., "Multilevel Transmission Line Pulse (MTLP) Tester", EOS/ESD 2004

[17] B. Keppens et al., “ESD Protection Solutions for High Voltage Technologies”, EOS/ESD 2004

http://www.sofics.com/files/paper/2006%20JMR%20HV%20X.pdf

[18] B. Keppens et al., “Contributions to standardization of transmission line pulse testing methodology”,

EOS/ESD 2001

[19] M. Stockinger et al., “Boosted and distributed rail clamp networks for ESD protection in Advanced

CMOS technologies”, EOS/ESD 2003

[20] S. Poon et al., “New Considerations for MOSFET Power Clamps”, EOS/ESD 2002[21] O. Quittard et al., “ESD protections for the High-Voltage CMOS Technology”, EOS/ESD 2006

[22] G. Notermans et al., "Designing HV Active Clamps for HBM Robustness", EOS/ESD 2007

[23] M.Mergens et al., "Analysis of 40V-LDMOS Power Devices under ESD stress conditions", IEEE

Transactions on electron devices, 2000

[24] K. Reynders, "Design and Characterization of a High Voltage SCR with High trigger current",

EOS/ESD 2005

[25] M. Mergens et al., “High Holding Current SCRs (HHI-SCR) for ESD Protection and Latch-upImmune IC Operation”, EOS/ESD 2002

http://www.sofics.com/files/paper/2002%20ESD%20HHISCR%20X.pdf

[26] B. Sorgeloos et al., “On-Chip ESD Protection with Improved High Holding Current SCR (HHISCR)

Achieving IEC 8kV Contact System Level” IEW 2010 and EOS/ESD 2010

http://www.sofics.com/files/paper/2010%20EOSESD%20IEC%208kV.pdf

Bart Keppens received an Engineer degree in Electronics from the TechnicalUniversity Groep T, Leuven in 1996. His master thesis, together with his colleague

Steven Servaes, ‘Transmission Line Pulsing (TLP) technique for analyzing ESD

reliability’, performed at IMEC, Leuven, Belgium, received the BARCO-award

for best Industrial Engineer thesis in 1996. In 1996 Bart joined IMEC and was

responsible for device electrical characterization, support for the ESD group and

for the Non Volatile Memories group for layout and testing.



From May 2002 he joined Sarnoff Europe, Belgium, solving ESD related problems for customers worldwide,first as ESD engineer, later as technical leader, ESD design specialist. From 2006, Bart supports the Business

Development initiatives. After a management buy-out in June 2009, Sarnoff Europe became 'SOFICS -

Solutions for ICs' where Bart is Director Technical Marketing working with companies worldwide.

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Sofics Proprietary – ©2012

About Sofics

Sofics (www.sofics.com) is the world leader in on-chip ESD protection. Its patented technology is proven in more than a thousand IC designs across all major foundries and process nodes. IC companies of all sizes rely on Sofics for off-the-shelf or custom-crafted solutions to protect overvoltage I/Os, other non-standard I/Os, and high-voltage ICs, including those that require system-level protection on the chip. Sofics technology produces smaller I/Os than any generic ESD configuration. It also permits twice the IC performance in high-frequency and high-speed applications. Sofics ESD solutions and service begin where the foundry design manual ends.

Our service and support

Our business models include

Single-use, multi-use or royalty bearing license for ESD clamps

Services to customize ESD protection o Enable unique requirements for Latch-up, ESD, EOS o Layout, metallization and aspect ratio customization o Area, capacitance, leakage optimization

Transfer of individual clamps to another target technology

Develop custom ESD clamps for foundry or proprietary process

Debugging and correcting an existing IC or IO

ESD testing and analysis

Notes

As is the case with many published ESD design solutions, the techniques and protection solutions described in this data sheet are protected by patents and patents pending and cannot be copied freely. PowerQubic, TakeCharge, and Sofics are trademarks of Sofics BVBA.

Version

December 2012

ESD SOLUTIONS AT YOUR FINGERTIPS

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B-9880 Aalter, Belgium (tel) +32-9-21-68-333 (fax) +32-9-37-46-846

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Web publication On-chip ESD protection for High Voltage

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