Warpage Mechanism of Thin Embedded LSI Packages · 2013. 7. 3. · 47 [Technical Paper] Warpage...
Transcript of Warpage Mechanism of Thin Embedded LSI Packages · 2013. 7. 3. · 47 [Technical Paper] Warpage...
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[Technical Paper]
Warpage Mechanism of Thin Embedded LSI PackagesYoshiki Nakashima*, Katsumi Kikuchi*, Kentaro Mori*, Daisuke Ohshima**, and Shintaro Yamamichi*
*Device Platforms Research Laboratories, NEC Corporation, 1120 Shimokuzawa, Sagamihara 229-1198, Japan
**System Jisso Research Laboratories, NEC Corporation, 1120 Shimokuzawa, Sagamihara 229-1198, Japan
(Received June 29, 2010; accepted October 1, 2010)
Abstract
The warpage mechanism of a thin embedded LSI package with a thick Cu plate was investigated for various Cu plate
thicknesses. The package warpage increased gradually as the Cu plate was made thinner. Even structures with a balanced
Cu and resin layer configuration for the top and bottom portions of the embedded chip showed substantial warpage, espe-
cially in the chip region, that was greater than that for an unbalanced layer configuration. This indicates the existence
of other warpage factors as well as unbalanced residual stress between the top and bottom of the chip. A ‘Birth & Death’
finite element method simulation showed that the thermal residual stresses induced by the coefficient of thermal expan-
sion mismatch for the LSI chip and embedding resin were concentrated in the resin surrounding the lateral sides of the
chip and that the stresses increased with decreasing Cu thickness. The release of these tensile stresses resulted in pack-
age warpage.
Keywords: Advanced Packaging, Embedded Device Technology, SiP, Simulation, Residual Stress
1. IntroductionLSI packaging technologies are needed for fabricating
thinner and higher-pin-count LSI packages to meet the
market demands for thinner, smaller, and more functional
mobile devices.[1] One way to achieve a thinner, higher-
pin-count LSI packaging structure is to realize a thinner
alternative to conventional flip-chip ball-grid array
(FCBGA) packaging. Our ‘SIRRIUS’ (seamless intercon-
nect for re-routing LSI using substrate) technology,[2–5]
for example, is well suited to fabricating those alternatives,
as shown in Fig. 1. The specifications of the embedded LSI
and SIRRIUS packages are shown in Table 1. While
several organizations have been developing packaging
technologies that have structures similar to that of
SIRRIUS,[6–9] SIRRIUS features the ability to embed a high-
pin-count LSI with a comparably thin structure and suffi-
cient reliability.
A reference FCBGA package and a SIRRIUS package
were prepared for LSI chips with the same specifications.
The total vertical thicknesses of these packages were 1.9
and 0.71 mm, respectively. This remarkable reduction in
thickness was achieved by using a thinner LSI chip (only
50 μm), a coreless structure, and seamless copper posts
Fig. 1 Comparison of (a) Structure A, reference FCBGApackage and (b) Structure B, our SIRRIUS package.
Table 1 SIRRIUS package specifications.
LSI
Size (mm) 9 × 9
Thickness (μm) 50
LSI pad count 1500
LSI pad pitch (μm) 160 (staggered area array)
Package
Size (mm) 27 × 27
BGA pad count 625
BGA pad pitch (mm) 1.0 (area array)
Wiring layer 3
BGA ball size (mm) 0.6
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for the interconnections instead of solder bumps.
However, the continuing market trend makes it neces-
sary to examine the possibility of making the SIRRIUS
structure even thinner. Thinning or removing the charac-
teristic 500-μm-thick Cu plate is a valid approach to making
the package thinner. However, since the plate is used to
control package warpage and remove LSI heat, research
into ways to make the SIRRIUS package thinner must
address the control of package warpage with a thinner Cu
plate.
We have now investigated several SIRRIUS package
structures with thinner Cu plates or without any Cu plate
in order to clarify the warpage mechanism. We performed
a ‘birth & death’ finite element method (FEM) analysis for
further discussion on fabrication process flows and struc-
tures, though this thermal stress analysis is conventionally
used to predict reliability after fabrication.[10, 11] We
found that the Cu plate thickness reduction created resid-
ual tensile stress in the resin layers surrounding the chip,
mainly in the areas lateral to the chip. The release of these
tensile stresses, along with the release of the compressive
stress in the chip, caused the package to warp.
2. Structures and Experimental ProcessesAs mentioned above, one approach to thinning the struc-
ture is to thin or remove the Cu plate while retaining the
embedding resin and wiring structure, as shown in Fig. 2.
We used this approach to fabricate several structures for
evaluation. The first structure, ‘Structure C’ in Fig. 2 (b),
had three wiring layers on the lower side of the LSI chip
and a thinner or no Cu plate on the upper side of the chip,
with an adhesive layer between the plate and the chip. The
thickness of the thinned Cu plate was set to slightly less
than half the original thickness. There are two factors that
make Structure C susceptible to warpage: the structure is
vertically asymmetric, so there is a vertical imbalance in
the residual thermal stresses caused by the coefficient of
thermal expansion (CTE) mismatch; and there is little in
the structure besides the Cu plate to keep the package flat
and stiff.
The next structure fabricated, Structure D, is not
affected by these two warpage factors. It is compared with
Structure C on the same scale in Fig. 3. Vertical asymme-
try was eliminated by introducing ‘balance resin’ and
‘remaining Cu’ layers above the chip. The remaining Cu
layer was only 10 μm thick, approximately the same thick-
ness as that of the first wiring layer. A glass cloth (GC)
sheet was added to the same layer as the LSI chip to
reinforce that layer so as to improve flatness and stiffness.
The fabrication process flow for Structure C is shown in
Fig. 4. Note that the direction of the cross-sectional illus-
trations is upside-down compared with Figs. 1 to 3. The
LSI chips were pre-processed to form Cu posts on the LSI
pads by semi-additive metallization. This was followed by
back-grinding to make them 50 μm thick, 20-μm-thick
adhesive layer lamination on the backside, and dicing to
form 9-mm-square chips. The first process step was LSI
chip mounting, as shown in Fig. 4 (a). The chips were sta-
bilized by curing the adhesive layer. The CTE for the adhe-
sive layers was 80 ppm. The chips were then embedded in
90-μm-thick epoxy resin using a simple vacuum lamination
process, as shown in Fig. 4 (b). The CTE for the epoxy
layer was 60 ppm. The Cu posts were then exposed by
grinding the epoxy resin surface, as shown in Fig. 4 (c). A
microscopic photo of the exposed Cu posts is shown in
Fig. 5 (a). Next, the wiring layers were fabricated. The first
Fig. 2 Comparison of (a) Structure B, our initial SIRRIUSpackage and (b) Structure C, our SIRRIUS package withthinned or removed Cu plate.
Fig. 3 Comparison of (a) Structure C, our SIRRIUS packagewith thinned or removed Cu plate and (b) Structure D, anti-warpage structure.
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fan-out wiring layer was fabricated using semi-additive
metallization, as shown in Fig. 4 (d). A photo of the wiring
layer is shown in Fig. 5 (b). Then, the second and third fan-
out wiring layers were fabricated, with resin layers that
had the same physical properties as the cover resin and
balance resin layers. This process was followed by solder
resist (SR) formation and package dicing, as shown in
Figs. 4 (e) and (f), respectively. The last process was Cu
plate etching, as shown in Fig. 4 (g).
The fabrication process flow for Structure D is shown in
Fig. 6. The first step was balance resin layer lamination, as
shown in Fig. 6 (a). The same resin used for chip embed-
ding with Structure C was laminated on the Cu plate by
simple vacuum lamination to a thickness of 20 μm. Next
was LSI chip mounting. The chips were the same as those
used for Structure D. The next step, resin-GC sheet and
cover resin lamination started with the formation of square
holes for the chips on 50-μm-thick resin-GC sheets, or
epoxy resin sheets reinforced by GC. Then the resin-GC
sheet and a 20-μm-thick epoxy resin sheet were laminated,
and the LSI chips were embedded in the layers, as shown
in Fig. 6 (c). The laminated resin-GC sheet created a ‘rein-
forcement layer,’ which had a CTE of 24 ppm. The epoxy
resin sheet, which is called the ‘cover resin’ layer, was
composed of the same material as the ‘balance resin’ layer.
Once the LSI chips had been embedded into the resin lay-
ers, the Cu posts were exposed using the same grinding
process as that used for Structure C, as shown in Fig. 6
(d). A microscopic photo of the posts is shown in Fig. 7 (a).
The cover resin layer thickness is the same as the Cu post
thickness between the surface of the chip passivation film
(PF) resin and the surface of the cover resin. We mea-
sured the cover resin layer thicknesses at the center of
four chips after the grinding. The thicknesses of the four
chips selected near the four edges of the work were 10.5,
12.1, 13.1 and 13.4 μm respectively. The variation of the
thickness is within approximately 3 μm. Next, the first wir-
ing layer was fabricated using the same process as that
used for Structure C, as shown in Fig. 6 (e). A photo of the
layer is shown in Fig. 7 (b). We omitted the second and
third wiring layer formation processes for Structure D
because the vertical balance effect was the focus in this
experiment. In the last step, the Cu plate was etched so
that a Cu layer about 10 μm thick remained, as shown in
Fig. 6 (f). The resulting structure is basically unsusceptible
to the warpage factors.
We measured the average thicknesses of the balance
resin layer, cover resin layer, reinforcement layer, adhe-
sive layer, and LSI layer with PF resin in Structure D at the
center, at the chip edge, and at the package edge after the
process flow. As shown in Table 2, the cover resin layer
was thicker at the package edge than at the center while
the balance resin layer was thicker at the center than at the
package edge. This tendency is explained by the shrink-
age of the Cu plate, which causes the chips to take an arch
form, after step (c) in Fig. 6.
Fig. 4 Steps in fabrication of Structure C.
Fig. 5 Photos of Structure C: (a) microscopic photo ofexposed Cu posts; (b) photo of first wiring layer.
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3. Results and Discussion3.1 Structures C and D
To enable detailed discussion of the warpage, we defined
two partial warpage values (Fig. 8). Warpage ‘Wp’ is com-
plete-package warpage and is the vertical distance between
the highest and lowest points, excepting the embedded LSI
chip region. Warpage ‘Wc’ is embedded-chip-region war-
page and is the vertical distance between the highest and
lowest points of the region. The directions of the two war-
pages differed for the fabricated Structure C and Structure
D samples. When warpage Wp exceeds warpage Wc, the
warpage for the package was defined as Wp, as shown in
Fig. 8 (a), and vice versa, as shown in Fig. 8 (b). The war-
pages for Structures C and D, as measured after Cu plate
etching using the shadow Moiré technique and a stylus
surface profiler, respectively, are shown in Table 3. The
common warpage measurement line for both structures is
shown in Fig. 9. In these measurements, the fan-out wiring
layer side was up, as shown in Figs. 4 (g) and 6 (f).
The warpage profiles after Cu-plate etching for Structure
C, with Cu plate thicknesses of 250, 100, and 0 μm, and for
Structure D, with a 10-μm-thick copper layer, are shown in
Figs. 10 (a) and (b), respectively.
Fig. 6 Steps in fabrication of Structure D.
Fig. 7 Photos of Structure D; (a) microscopic photo ofexposed Cu posts; and (b) photo of first wiring layer.
Table 2 Average layer thicknesses for Structure D.
LayerThickness (μm)
PKG Edge Chip Edge Center Average
Cover Resin 16.2 16.8 12.7 15.3
LSI (w/PF) – 62.8 61.7 62.3
Adhesive – 20.1 19.8 19.9
Reinforcement 84.0 82.9 – 83.4
Balance Resin 13.8 18.7 19.3 17.2
Total 113.9 118.4 113.6 115.3
Fig. 8 Two partial warpage definitions: (a) package warpageWp is larger than chip region warpage Wc; (a) Wc is largerthan Wp.
Table 3 Average warpage for Structures C and D after Cuplate etching.
Structure Structure-C Structure-D
Cu plate thickness (μm) 250 100 0 10
Warpage [Wp or Wc] (μm)135
[Wp]362
[Wp]316
[Wc]370
[Wc]
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The warpage for Structure C with Cu plate 100 μm thick
or less was significant. When the Cu plate thickness was
100 μm or more, the concave warpage, Wp, exceeded the
convex warpage, Wc. This indicates that, with Cu plates,
the CTE mismatch between the resin for the three fan-out
wiring layers and the Cu plate was the dominant factor
causing warpage. In contrast, without the Cu plate, the
concave warpage, Wc, exceeded convex warpage, Wp.
This indicates that the CTE mismatch between the LSI
chip and the resin in the three fan-out wiring layers was
the dominant factor causing the warpage. These results for
Structure C were as expected.
The warpage for Structure D was also remarkable, as
shown in Fig. 10 (b). Convex warpage, Wc, exceeded con-
cave warpage, Wp. Comparing warpage Wc for Structure C
without the Cu plate with that for Structure D, we see that
the warpage for Structure D, 370 μm, was larger than that
for Structure C, 316 μm, as shown in Table 3. In our dis-
cussion here of warpage Wc, we focus on the thermal
residual stress factors of the chip-embedding 9 × 9 mm
central region of the 27 × 27 mm package.
For Structure C, the main warpage factor, especially for
the chip-embedding region, should be the imbalance
between the Si for the LSI chip and the resin for the three
fan-out wiring layers. The resin for the fan-out layers was
140 μm thick, and they were only on the upper side of the
LSI chip, as shown in Figs. 4 (g) and 6 (f). The CTE for the
resin is much larger than that for the Si, which would
result in comparable shrinkage for the three resin layers
during the cooling phase following curing. Moreover,
there was no stiff material to suppress the warpage after
the Cu plate etching. These configuration and physical
properties explain the observation of the large concave
Wc.
For Structure D, the resin layers for the chip-embedding
region were on the upper and lower sides of the chip and
had the same thickness. Therefore, if the resin layers
shrank during the cooling phase, the shrink force should
have been balanced. Moreover, the chip layer was rein-
forced to suppress warpage. Therefore, the larger warpage
than for Structure C needed more explanation.
We thus considered other factors which might explain
the results for Structure D.
3.2 Factor Analysis and Discussion of Other Possi-ble Warpage Factors
We considered two other possible warpage factors for
Structure D, which are illustrated in Fig. 11: the imbalance
in the thermal history of the resin layers and the thermal
stress in the adhesive layer. The balance resin layer was
first laminated and cured on the Cu plate. Next, after LSI
mounting, the reinforcement layer and cover resin layer
were laminated and cured, as was the balance resin layer.
Therefore, the balance resin layer was cured twice while
the upper two layers were cured only once, resulting in an
imbalance in the thermal history. The thermal stress in the
adhesive layer likely caused the layer to shrink, resulting
in convex warpage of the chips. To investigate the effect of
these two factors, we performed an additional factor analy-
sis experiment in which the wiring layer was not included.
Cross-sectional illustrations of the two structures fabri-
cated for the experiment are shown in Fig. 12. Both struc-
Fig. 9 Common warpage measurement line.
Fig. 10 Warpage forms for (a) Structure C and (b) StructureD samples.
Fig. 11 Other two warpage factors investigated: imbalance inthermal history and thermal stress in adhesive layer.
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tures had embedded bare Si chips, simulating LSI chips.
They were the same thickness and size as the LSI chips
used for Structures C and D. The control sample structure,
‘Structure E,’ is shown in Fig. 13 (a). It had the same resin
configuration and was fabricated in the same way as Struc-
ture D. The experimental structure, ‘Structure F,’ is shown
in Fig. 13 (b). It was fabricated using a ‘simultaneous lam-
ination’ process to eliminate the two remaining factors.
First, bare Si chips and a reinforcement layer with chip
holes were set in place. Then, the two resin layers were
laminated onto the upper and lower sides of the chip and
reinforcement layer simultaneously. Next, the entire pack-
age was cured all at once. As a result, the thermal history
was balanced, and there was no need for an adhesive layer.
The warpage profiles for Structures E and F are shown
in Fig. 13. As these warpage were too large for a stylus sur-
face profiler or the shadow Moiré technique, we used a
microscope that enabled us to measure the vertical level of
the focus point and focused on certain points on the mea-
surement line (Fig. 9). The warpages for the two struc-
tures were almost the same. They exceeded warpage Wc
for both structures. These results indicate that these two
other factors, imbalance in the thermal history of the resin
layers and thermal stress in the adhesive layer, were not
the main factors in the package warpage.
Obviously, Structure D was warped by another mecha-
nism. To identify candidate factors, we performed a FEM
simulation.
4. FEM SimulationFirst, we identified an appropriate structure for the FEM
simulation. The pros and cons for possible structures are
listed in Table 4. Structure E was not considered because
its process flow and resin configuration are the same as
those for Structure D. As shown in Table 4, the fabrication
process flow for Structure C has already been developed,
so fabrication is not a problem. However, the measured
warpage is basically explained already, so this structure is
not suitable for further warpage investigation. The fabrica-
tion process flow for Structure D has also been developed.
Moreover, the warpage factor for this structure is not fully
explained by a known mechanism. Additionally, with this
structure, we can discuss the other two factors. The war-
page mechanism for Structure F is also unknown, but a
fabrication process with wiring has not been developed.
We thus used Structure D for our thermo-mechanical FEM
simulation using ANSYS mechanical.
The model used for the simulation is illustrated in Figs.
14 and 15. The subject of the simulation was a work of sev-
eral 27 × 27 mm packages, and by setting symmetric
boundaries in the simulation model, we calculated the
model of one package in a practical manner.
We set the fan-out wiring layer on the top, just as illus-
trated in Fig. 6. As shown in Fig. 14, we divided the first
fan-out wiring layer (CAD design shown in Fig. 14 (a)) in
the model into nine parts, and set the physical properties
of the parts between Cu and air on the basis of the area
ratio of the wirings, as shown in Fig. 14 (b). The cross-
section line on the model shown in Fig. 14 (b) defines the
Fig. 12 Cross-sectional illustrations of (a) Structure E and(b) Structure F.
Fig. 13 Results of factor analysis experiment: (a) warpageform for Structure E and (b) for Structure F.
Table 4 Pros and cons of three possible structures for FEManalysis.
Pros➘ Realization
for thefabrication
➘ Realization forthe fabrication
➘ Remaining twofactors’ and further
warpage mechanismdiscussion
➘ Further warpagemechanismdiscussion
Cons➘ Known warpage
mechanismdiscussion
➘ No realizationfor the wiring
fabrication
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cross-sectional maps of the residual stress contour maps.
Figure 15 shows cross-sectional views of (a) the actual
components in the LSI chip margin area and (b) the mate-
rials defined for the simulation. The first fan-out wiring
layer, labeled ‘9’ in Fig. 15 (a), corresponds to the ‘Cu + air’
material in Fig. 15 (b), which means that, in this layer,
there is no insulation material but air between the Cu wir-
ings.
We used the ‘birth & death’ method [12] to simulate the
fabrication process flow. In this method, insulator materi-
als such as resin and adhesive layers appear (are ‘born’) at
the same time that these components are cured in the
actual procedure, as shown in Table 5. The Cu plate disap-
pears (‘dies’) when it is etched out in the actual procedure.
Other materials, such as Cu and Si, appear (are ‘born’)
with the insulator materials, or between processes. In this
simulation, the physical properties of the material, such as
Young’s modulus, the CTE values, the Poisson ratio, and
the glass transition temperature, were used as parameters
in the calculation. However, the chemical shrinkage fac-
tors of the resins were not parameterized. Therefore, we
were unable to verify the thermal history imbalance in this
simulation. The points labeled I–VII on the thermal condi-
tion chart in Table 5 are the process points at which the
residual stresses were observed. Three observation points
were set for the Cu plate etching process to enable
detailed analysis of the warpage mechanism.
Contour maps of the residual stresses at the observation
points (I–VII) are shown in Figs. 16 and 17 as seen from
the cross section line in Fig. 14 (b). The scale for the resid-
ual stress is shown to the right of Fig. 16. The black and
white shadings correspond to compressive and tensile
residual stress, respectively.
The first residual stress map, Fig. 16 I, is for the room
temperature point after curing the balance-resin layer. The
resin layer showed about 300–400 MPa tensile stress due
to shrinkage. The second map, Fig. 16 II, is for the room
temperature point after mounting the LSI. Due to the CTE
gap between Cu and Si, the Cu plate showed 0–600 MPa
tensile stress, and the LSI chip showed −100 to 0 MPa
compressive stress. The third map, Fig. 16 III, is for the
room temperature point after lamination and curing of the
reinforcement and cover-resin layers. The reinforcement
Fig. 14 (a) Top view of Structure D package wiring layer and(b) top view of FEM model for ANSYS mechanical analysis,which is divided into nine parts on basis of Cu area ratio of wir-ing.
Fig. 15 Cross-sectional views of embedded LSI components:(a) material configuration defined using ANSYS mechanicaland (b) actual component configuration.
Table 5 ‘Birth and Death’ simulation processes for Structure D.
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layer showed 0–100 MPa tensile stress.
Maps IV–VII show the residual stress distributions for
the Cu plate-etching process. At the earlier points of the
process (IV-V), there was 100–200 MPa tensile stress for
the reinforcement layer. At the following point (VI), 100–
200 MPa tensile stress remained in almost all regions of
the reinforcement layer; however, in the vicinity of the LSI
chip, tensile stress was greater than 400 MPa. At the last
point (VII), there was almost zero stress in the reinforce-
ment layer while there was stress greater than 500 MPa
near the LSI chip.
These results indicate that compressive stress in the LSI
chip and/or Cu plate, caused by reinforcement layer
shrinkage, gradually concentrated in the vicinity of the LSI
chip as the Cu plate was etched. The compressive stresses
were mainly balanced by the reaction force of the thick Cu
plate before point V.
Figures 18 (a) and (b) shown enlarged images of the VI
and VII contour maps, with vertically enhanced deforma-
tion or warpage. Figure 18 (a) shows the contour map for
a sample with a Cu plate one-third the original size, and
Fig. 18 (b) shows the map for a sample without a Cu plate.
The lower side of the LSI chip showed tensile stress of
around 600–700 MPa for both maps, meaning that this part
had no effect on the warpage. The upper side of the LSI
chip showed tensile stress of between 600 and 700 MPa for
both maps, so this part also had little effect on the war-
page.
However, lateral to the chip, the tensile stress distribu-
tion was clearly different. Along with the Cu-etching pro-
cess, the upper parts of the lateral sides of the chip showed
stronger tensile stresses while the lower parts of the lateral
sides showed weaker tensile stresses. This means that the
tensile stresses on the lateral sides of the chip were
released in the lower parts. This caused the chip to warp
convexly on its lateral side, as shown in Fig. 18 (b).
To discuss the directions of the stress in the chip itself
and in its vicinity, as shown in Fig. 18 (b), we use Fig. 19
(a), which shows an overhead view of the ANSYS simula-
tion model for the entire Structure D package after Cu-
plate etching. The chip and its surrounding region are
enlarged in Fig. 19 (b) and shown as a map of the maxi-
mum principal stress vectors for each mesh of the model.
The meshes in the map are located in the central region of
the middle layer of the package, including the LSI chip
meshes. The principal stress vectors are set to be positive
Fig. 16 Residual stress contour maps of cross-sectional viewsfor process points I (balance resin layer lamination), II (LSImounting), and III (LSI embedding).
Fig. 17 Residual stress contour maps of cross-sectional viewsfor process points IV–VII (Cu plate etch-out).
Fig. 18 Residual stress contour maps of cross-sectional viewswith enhanced vertical deformation for last two process pointsshown in Fig. 17: (a) VI and (b) VII.
Fig. 19 Overhead views of Structure D at process point afterCu plate etch out: (a) complete package simulation model, (b)maximum principal stress vector map for central region, mid-dle layer meshes of chip and surrounding resin, and (c)enlarged and simplified figure of nearside edge of (b).
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in tensile, and negative in compressive, just as for Figs. 16,
17, and 18. Figure 19 (c) shows an enlarged and simplified
illustration of four meshes at the near edge of the map in
Fig. 19 (b). The mesh with ‘Vector A’ is for a part of the
chip, and the other three meshes are for parts of the sur-
rounding resin-GC area. As these vectors in Fig. 19 (c)
show, the resin-GC meshes have tensile stresses parallel
to the chip side as maximum principal stresses. In con-
trast, the maximum principal stress for the chip mesh is
compressive stress in the vertical direction (‘Vector A’).
This means that the minimum and middle principal
stresses for the chip, which should be larger compressive
stresses than the maximum principal stress shown as
‘Vector A’, are in horizontal directions.
In short, these tensile stresses were caused by the
shrinkage of the resin and GC surrounding the LSI chip.,
For the stress balance of these tensile stresses, the com-
pressive stresses were generated in the chip horizontally.
Therefore, from Fig. 18 (b), we can understand that the
tensile stresses surrounding the chip (Figs. 19 (b) and (c))
were partially released in the lower parts of the structure
lateral to the chip after Cu-plate etching. This stress
release created substantial convex warpage in the region
surrounding the chip. Also, the compressive stresses cre-
ated in the chip caused the entire chip to warp convexly,
as shown in Fig. 18 (b).
We thus conclude that for Structure D, the Cu-plate
etching created residual tensile stress in the resin layers
surrounding the chip, mainly in the areas lateral to the
chip. The package warpage was caused by the release of
these tensile stresses, along with the release of the com-
pressive stress in the chip. This mechanism can also be
applied to the warpage for Structure F. In the resin-curing
process after the simultaneous lamination, tensile stress
was created in the areas lateral to the chip, which was
immediately released by the package warpage.
5. ConclusionWe fabricated several different structures to investigate
the warpage mechanism for thin embedded LSI packages.
We found that such warpage factors as an imbalance in the
resin configuration above and below the LSI chip, the
reduced use of stiff materials, an imbalance in the thermal
history, and thermal stress in the adhesive layer were not
the dominant factors. The results of a ‘birth and death’
FEM simulation showed that, after the Cu-plate etching,
the tensile residual stresses in the embedded LSI layer
gradually concentrated in the area surrounding the chip,
that the stresses increased with decreasing Cu-plate thick-
ness, and that the warpage was caused by the release of
these tensile stresses, along with the compressive stress in
the chip. Therefore, simple structural considerations are
insufficient for obtaining a reduced-warpage structure. In
this study, when the Cu plate thickness was 100 μm or
less, we did not find a package without substantial war-
page, which was the case with Structures D and F as well.
The material properties should also be considered, which
could change these balanced structures into reduced-
warpage structures. One possible consideration for the
material properties is the use of a resin with less tensile
stress in the areas lateral to the LSI chips. The resin could
be stiffer to reduce the CTE mismatch or softer to reduce
the elastic modulus.
AcknowledgmentsWe thank Dr. Yasunori Mochizuki, Mr. Kazuhiro Baba,
Mr. Tomoo Murakami, Mr. Masanobu Hashimoto, and Dr.
Takashi Harada of NEC Corporation, and Dr. Hideki
Sasaki of Renesas Electronics Corporation for their
encouragement and useful feedback and suggestions. We
also thank Mr. Seiicihro Ohkawa and Ms. Keiko Kishino of
NEC Informatec Systems Ltd. for their guidance on the
simulation.
References
[1] ITRS 2009, Assembly and Packaging White Paper.
[2] K. Mori, et al., “A Novel Ultra-Thin Package for
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