Walive Pathiranage Manula Randhika Pathirana, Matthew Ridder, and Luis Lopez Ruiz University of...
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Transcript of Walive Pathiranage Manula Randhika Pathirana, Matthew Ridder, and Luis Lopez Ruiz University of...
Walive Pathiranage Manula Randhika Pathirana,Matthew Ridder,and Luis Lopez RuizUniversity of Virginia, Dept. of Electrical Engineering
Dec 11, 2015
A Comparison of FET Devices: FinFETs vs. Traditional CMOS
MOSFET and FinFET Structure
• 3D structure• Conducting channel on 3 sides.• Very little leakage.• High potential for large
improvements in power
• 2D structure• Conducting channel only on the
surface.• As the channel decreases, the
control over the device is reduced.
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Related Work
• 22 and 45nm technology comparisons for 6T SRAM cells
• Power reduction and faster performance
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Our Project
16nm technology
Setup
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NAND
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NAND ResultsCMOS
FinFET
Finfet CMOSA B Pleakage(nW) Pleakage(nW)0 0 0.82 2.980 1 0.91 3.401 0 0.79 2.481 1 0.73 2.34
Input
Transition Finfet delay(ps) CMOS delay(ps)01→11 42 33011→10 60 48201→11 27 36111→01 52 444
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NOR
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NOR ResultsCMOS
FinFET
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XOR
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XOR Results16nm CMOS
16nm finFET
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Flip Flop
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Flip Flop ResultsCMOS
FinFET
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4-bit Adder
Finfet delay(ps) CMOS delay(ps)tpLH 52 744tpHL 54 733
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4-bit Adder ResultsCMOS
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4-bit Adder ResultsFinFET
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MUXMUX 4to1 Schematic
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MUXMUX 4to1 Testbench
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MUX Results16nm CMOS Technology – Transient Analysis
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MUX Results16nm finFET Technology – Transient Analysis
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MUX ResultsDelay and Power Measurements Comparisson
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Conclusions and Future Work• FinFET devices show a high improvement over traditional
CMOS in terms of both delay and leakage. XOR: finFET 11x faster and 8x less leakage. MUX: finFET 12x faster and 10x less leakage NAND:FinFET 8x faster and 3x less leakage Adder:FinFET 14x faster and 4x less leakage
• Next steps would be to obtain access to layout and do area analysis and comparison between technologies by including parasitic effect
• Despite the improvements shown, there are challenges to fully adopt this new technology: resources for modeling and designing, fabrication, cost, etc.